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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: vahle.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6503.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e3d2d70-5773-45ff-f60f-08db14c6182c X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Feb 2023 11:15:24.4580 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 251574ce-9f08-4528-b17a-70ad2956ff08 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fnFM7AJHjgeuXpV4vnZHC9t11a4IAvjUqMQ/eep3Lu2czPLWjrlGx1JTp6b51yS4Z6R/55dPcBcifCfwuiALG2svA9xyg3qsHB6NEtx2N8Q= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8832 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_031531_319729_B2A26274 X-CRM114-Status: GOOD ( 16.77 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.8 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH 2/3] ARM: IMX8MP: add initial support for Variscite DT8MCustomBoard with iMX8MP X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) Hi Sasha,=0A= =0A= thanks for your remarks on my patches. I agree with your comments.=0A= I will rework the patches and submit a second version soon.=0A= =0A= I added a small reply to the memory node remark to point out,=0A= that I have no possibility to test my solution with other hardware=0A= configurations and I am unsure whether I choose the best solution.=0A= =0A= On Tue, Feb 21, 2023 at 10:20AM +0100, Sascha Hauer wrote:=0A= =0A= [snip]=0A= =0A= >> diff --git a/arch/arm/dts/imx8mp-var-dart-dt8mcustomboard.dts b/arch/arm= /dts/imx8mp-var-dart-dt8mcustomboard.dts=0A= >> new file mode 100644=0A= >> index 0000000000..704289aa0b=0A= >> --- /dev/null=0A= >> +++ b/arch/arm/dts/imx8mp-var-dart-dt8mcustomboard.dts=0A= >> @@ -0,0 +1,680 @@=0A= >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0A= >> +/*=0A= >> + * Copyright 2019 NXP=0A= >> + * Copyright 2020-2021 Variscite Ltd.=0A= >> + * Copyright 2023 VAHLE Automation GmbH=0A= >> + */=0A= >> +=0A= >> +#include "imx8mp-var-dart.dtsi"=0A= >> +=0A= >> +/ {=0A= >> + model =3D "Variscite DART-MX8M-PLUS on DT8MCustomBoard 2.x";=0A= >> +=0A= >> + // use the memory controller instead=0A= >> + /delete-node/ memory@40000000;=0A= >=0A= > Better don't add this node to the dtsi file. Is the memory size detected= =0A= > correctly? The dtsi file describes 6 GiB of memory which is rather=0A= > unusual. Is that what your board has?=0A= >=0A= =0A= I will delete the memory node.=0A= =0A= As for the memory size:=0A= Those modules are sold with RAM ranging from 1 to 8 GiB, my module actually= =0A= has 4GiB of RAM. The dtsi used was taken from Variscites provided linux sou= rces.=0A= Hence I thought it might be nice to rely on the memory controller to figure= the actual=0A= configuration out. I ran "memtest" successfully and used "devinfo mem0" to= =0A= validate, that it does see 4GiB of RAM for this node.=0A= But I haven't checked whether some other RAM size option gets detected corr= ectly=0A= as well, as I only have this one SOM at hand.=0A= =0A= >> +&edacmc {=0A= >> + status =3D "okay";=0A= >> +};=0A= >=0A= > You can drop this. It's already enabled in imx8mp.dtsi.=0A= >=0A= =0A= [snip]=0A= =0A= By the way, I have base those patches on the "next" branch, but I realized= =0A= that I have no clue what is preferred by the project's maintainers.=0A= Shall I base those patches on "master" instead?=0A= =0A= Michael=