barebox MIPS start code considerations

barebox MIPS start code considerations

[Antony Pavlov]

Hi!

Here is my barebox MIPS start code considerations.
If you get the time would you please review this text.


Barebox normally must be linked to RAM region, cached region KSEG0 is preferred.
This make possible to run fast (because cache used) and skip MMU support.

After reset MIPS CPU starting to fetch instructions from 0xBFC00000.

This remark from ARM code can be used for MIPS start.S:
----
Code running immediately after reset runs at an address it is not linked
to: "runtime address != link address". You should only use branches and
do not refer to fixed data. This implies the use of assembler code only.
After MIPS CPU reset cache and MMU are in random state. They are unusable.
----

barebox MIPS initialisation sequence:

 * set the CP0 STATUS register to some known and sensible state.
Now you can load and store reliably in uncached space.

 * call a function \<mach_init_lowlevel\> (if not disabled).
do some special things required only on specific CPU
 (e. g. init RAM controller, disable watchdog)

 * call a function \<board_init_lowlevel\> (if not disable).
do some special things required only on specific board
 (e. g. setup GPIO to required state).

   ** It is desirable to have some debug code to make some contact
 with the outside world from assembler code
(e.g. debug_ll-like functions to write to rs232 console).

 * check integity of barebox RAM execute location;
 * copy barebox to RAM execute location;

 * configure cache;

 * setup stack;

   ** after ths point you can call a standard C routine.

 * setup exception vectors in RAM;
 * setup CP0 STATUS to switch exception vector address to RAM;

 * call start_barebox()

-- 
Best regards,
  Antony Pavlov

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox