[PATCH] Patch to fix bootm barebox load address alignment to acomodate ADRP instruction

[Thaison Phan <tsphan42@gmail.com>]

Hi,

The aarch64 bootm image handler for barebox can choose a load address
that is not 4KB aligned. This can result in unexpected behavior with
the ADRP instruction that is available in 64 bit ARM architectures.
ADRP forms a PC-relative address to a 4KB page where the bottom 12
bits of the current PC will be masked out. When the load address of
the barebox image is not 4KB aligned ADRP can end up forming an
address that starts from an invalid page of memory or the wrong page
of memory that was expected to be formed. The following patch aligns
the load address for the next barebox image to be 4KB aligned to
accommodate the ADRP instruction.

Thanks,
Thaison

---
 arch/arm/lib64/armlinux.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/lib64/armlinux.c b/arch/arm/lib64/armlinux.c
index 8382ffdf1b..d66963dae5 100644
--- a/arch/arm/lib64/armlinux.c
+++ b/arch/arm/lib64/armlinux.c
@@ -43,6 +43,8 @@ static struct image_handler aarch64_fit_handler = {
        .filetype = filetype_oftree,
 };

+#define ADRP_PAGE_MASK 0x1000
+
 static int do_bootm_barebox(struct image_data *data)
 {
        void (*fn)(unsigned long x0, unsigned long x1, unsigned long x2,
@@ -55,7 +57,7 @@ static int do_bootm_barebox(struct image_data *data)
        if (ret)
                goto out;

-       barebox = start;
+       barebox = ALIGN(start, ADRP_PAGE_MASK);

        ret = bootm_load_os(data, barebox);
        if (ret)
--
2.25.1