Re: [PATCH 22/58] PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2

[Andrey Smirnov <andrew.smirnov@gmail.com>]

On Wed, Dec 12, 2018 at 11:12 PM Andrey Smirnov
<andrew.smirnov@gmail.com> wrote:
>
> Port of a Linux commit fe48cb8538421fbd16ecf8bf95829faf8d8c001e
>
>   Most of the platforms have 3 or more viewports.  For such platforms, We do
>   not need to share viewports between IO and CFG.  Assign viewport 2 to IO
>   transactions in such cases.
>
>   Tested-by: Dong Bo <dongbo4@huawei.com>
>   Signed-off-by: Pratyush Anand <pratyush.anand@gmail.com>
>   Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>   Acked-by: Rob Herring <robh@kernel.org>
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  drivers/pci/pcie-designware.c | 26 +++++++++++++++++++-------
>  drivers/pci/pcie-designware.h |  1 +
>  2 files changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
> index 6de9fa7e3..cf1b3032e 100644
> --- a/drivers/pci/pcie-designware.c
> +++ b/drivers/pci/pcie-designware.c
> @@ -61,6 +61,7 @@
>  #define PCIE_ATU_VIEWPORT              0x900
>  #define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
>  #define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> +#define PCIE_ATU_REGION_INDEX2         (0x2 << 0)
>  #define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
>  #define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
>  #define PCIE_ATU_CR1                   0x904
> @@ -330,6 +331,10 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>         if (ret)
>                 pp->lanes = 0;
>
> +       ret = of_property_read_u32(np, "num-viewport", &pp->num_viewport);
> +       if (ret)
> +               pp->num_viewport = 2;
> +
>         if (pp->ops->host_init)
>                 pp->ops->host_init(pp);
>
> @@ -376,9 +381,10 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>                                   type, cpu_addr,
>                                   busdev, cfg_size);
>         ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
> -       dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
> -                                 PCIE_ATU_TYPE_IO, pp->io_mod_base,
> -                                 pp->io_bus_addr, pp->io_size);
> +       if (pp->num_viewport <= 2)
> +               dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
> +                                         PCIE_ATU_TYPE_IO, pp->io_mod_base,
> +                                         pp->io_bus_addr, pp->io_size);
>
>         return ret;
>  }
> @@ -414,9 +420,10 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>                                   type, cpu_addr,
>                                   busdev, cfg_size);
>         ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
> -       dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
> -                                 PCIE_ATU_TYPE_IO, pp->io_mod_base,
> -                                 pp->io_bus_addr, pp->io_size);
> +       if (pp->num_viewport <= 2)
> +               dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
> +                                         PCIE_ATU_TYPE_IO, pp->io_mod_base,
> +                                         pp->io_bus_addr, pp->io_size);
>
>         return ret;
>  }
> @@ -564,10 +571,15 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>          * uses its own address translation component rather than ATU, so
>          * we should not program the ATU here.
>          */
> -       if (!pp->ops->rd_other_conf)
> +       if (!pp->ops->rd_other_conf) {
>                 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
>                                           PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
>                                           pp->mem_bus_addr, pp->mem_size);
> +               if (pp->num_viewport <= 2)

Ugh, this is incorrect. Should be pp->num_viewport > 2, instead. Will fix in v2.

Thanks,
Andrey Smirnov

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