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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: "barebox@lists.infradead.org" <barebox@lists.infradead.org>,
	Chris Healy <cphealy@gmail.com>
Subject: Re: [PATCH 0/3] Fix "i.MX: vf610: Ramp CPU clock to maximum frequency"
Date: Tue, 20 Jun 2017 20:41:59 -0700	[thread overview]
Message-ID: <CAHQ1cqGe_1cq_0XVOgG=oVXPg7bnoZ5t0cTT+5j8rruLiTOKVQ@mail.gmail.com> (raw)
In-Reply-To: <20170620073505.5j424abxcpezwizd@pengutronix.de>

On Tue, Jun 20, 2017 at 12:35 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Mon, Jun 19, 2017 at 07:40:36AM -0700, Andrey Smirnov wrote:
>> Everyone,
>>
>> It looks like my test setup was somehow contaminated -- possibly by
>> using JTAG to initalize SoC and upload Barebox binary -- so
>> 21921f7f419dfaabcd385595ada24f0352310f1a ("i.MX: vf610: Ramp CPU clock
>> to maximum frequency") didn't actually work as I thought it was and
>> instead it made Barebox not boot on Vybrid.
>>
>> This patch series contains all of the changes I had to make in order
>> to make CPU clock switching work/"unbreak" Barebox on Vybrid.
>
> You mean you want to have this series on master, right?
>

I didn't really think about it, but yeah It probably would make sense
to apply it to master.

Thanks,
Andrey Smirnov

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  reply	other threads:[~2017-06-21  3:42 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-19 14:40 Andrey Smirnov
2017-06-19 14:40 ` [PATCH 1/3] clk-vf610: Mark all of CCSR muxes with CLK_OPS_PARENT_ENABLE Andrey Smirnov
2017-06-19 14:40 ` [PATCH 2/3] i.MX: clk-pllv3: Do not touch PLL_BYPASS bit Andrey Smirnov
2017-06-19 14:40 ` [PATCH 3/3] i.MX: clk: Remove imx_clk_pllv3_locked() Andrey Smirnov
2017-06-20  7:35 ` [PATCH 0/3] Fix "i.MX: vf610: Ramp CPU clock to maximum frequency" Sascha Hauer
2017-06-21  3:41   ` Andrey Smirnov [this message]
2017-06-21  8:44     ` Sascha Hauer

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