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Content preview: Il giorno mer 19 ago 2026 alle ore 09:16 Sascha Hauer ha scritto: > > Hi Uwe, > > On 2026-08-18 10:44, Uwe Kleine-König wrote: > > > > > > The only difference I can spot here between this function [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:631 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [famlauro93l(at)gmail.com] -0.0 DMARC_PASS DMARC pass policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Rspamd-Action: no action X-Rspamd-Server: mx1 X-Stat-Signature: uaworu49imw3untxoyhfhio4rzjjdh3z X-Spamd-Result: default: False [-8.91 / 15.00]; BAYES_HAM(-3.00)[100.00%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; ARC_ALLOW(-1.00)[google.com:s=arc-20260327:i=1]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; DMARC_POLICY_ALLOW(-0.50)[gmail.com,none]; R_SPF_ALLOW(-0.20)[+mx:c]; MAILLIST(-0.20)[mailman]; RCVD_IN_DNSWL_MED(-0.20)[2607:7c80:54:3::133:from]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,gmail.com:s=20251104]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RECEIVED_HELO_LOCALHOST(0.00)[]; RCVD_COUNT_THREE(0.00)[3]; FORGED_SENDER(0.00)[famlauro93l@gmail.com,barebox-bounces@lists.infradead.org]; FORWARDED(0.00)[barebox@lists.infradead.org]; DWL_DNSWL_NONE(0.00)[gmail.com:dkim]; RCVD_TLS_LAST(0.00)[]; FREEMAIL_FROM(0.00)[gmail.com]; MIME_TRACE(0.00)[0:+]; TO_DN_ALL(0.00)[]; DKIM_TRACE(0.00)[lists.infradead.org:+,gmail.com:+]; RCVD_IN_DNSWL_NONE(0.00)[2a00:1450:4864:20::631:received]; FORGED_SENDER_FORWARDING(0.00)[]; PREVIOUSLY_DELIVERED(0.00)[barebox@lists.infradead.org]; FROM_NEQ_ENVFROM(0.00)[famlauro93l@gmail.com,barebox-bounces@lists.infradead.org]; FROM_HAS_DN(0.00)[]; TAGGED_FROM(0.00)[lore=pengutronix.de]; NEURAL_HAM(-0.00)[-1.000]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; MID_RHS_MATCH_FROMTLD(0.00)[]; RCPT_COUNT_THREE(0.00)[3]; MISSING_XM_UA(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Queue-Id: AFE51201D0E Il giorno mer 19 ago 2026 alle ore 09:16 Sascha Hauer ha scritto: > > Hi Uwe, > > On 2026-08-18 10:44, Uwe Kleine-K=C3=B6nig wrote: > > > > > > The only difference I can spot here between this function and the > > > existing variant in arch/arm/mach-mvebu/common.c is: > > > > > > #define DDR_SIZE_MASK 0xff000000 > > > > > > whereas the common.c variant uses: > > > > > > #define ARMADA_370_XP_DDR_SIZE_MASK 0xffff0000 > > > > Apart from the different value, the latter name is the better one B-) > > > > > The latter goes down to this: > > > > > > > commit 7351b6b5c59c7a280787998006f39a5cd3a2f18b > > > > Author: Uwe Kleine-K=C3=B6nig > > > > Date: Tue Jun 13 00:37:49 2017 +0200 > > > > > > > > ARM: mvebu: fix size mask for RAM window > > > > > > > > The size field in the window control register occupies bits 31:= 16. So > > > > adapt ARMADA_370_XP_DDR_SIZE_MASK accordingly. This fixes detec= tion of > > > > RAM chips smaller than 32 MiB and so probably doesn't affect an= y > > > > supported machine. > > > > > > > > Signed-off-by: Uwe Kleine-K=C3=B6nig > > > > Signed-off-by: Sascha Hauer > > > > > > > > diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/com= mon.c > > > > index 06bfb72615..fa971da11e 100644 > > > > --- a/arch/arm/mach-mvebu/common.c > > > > +++ b/arch/arm/mach-mvebu/common.c > > > > @@ -47,7 +47,7 @@ > > > > #define ARMADA_370_XP_SDRAM_BASE (IOMEM(MVEBU_REMAP_INT_REG_= BASE) + 0x20000) > > > > #define ARMADA_370_XP_DDR_SIZE_CSn(n) (0x184 + ((n) * 0x8)) > > > > #define ARMADA_370_XP_DDR_SIZE_ENABLED BIT(0) > > > > -#define ARMADA_370_XP_DDR_SIZE_MASK 0xff000000 > > > > +#define ARMADA_370_XP_DDR_SIZE_MASK 0xffff0000 > > > > > > > > /* > > > > * Marvell MVEBU SoC id and revision can be read from any PCIe > > > > > > @Uwe, Where did you get that information from. Could it be that we > > > should just revert this one given that it seems to be untested on you= r > > > side? > > > > 0xffff0000 is in line with > > https://datasheet.datasheetarchive.com/originals/crawler/marvell.com/00= 2fa441a27967d992f905776d519926.pdf > > (page 630). So I'd expect that 0xffff0000 is correct, but I don't care > > much. > > Page 630 describes the register at offset 0x20000. I think the correct > page to look at is 626 which describes 0x20184 aka ARMADA_370_XP_DDR_SIZE= _CSn(0). > > That one has the window size in the upper 8 bit. Looks like we should > just revert 7351b6b5c59c. @Luca, does the SDRAM size detection work for > you with that patch reverted? Hi Sascha, I tested with kwboot on my RN102... SDRAM detection: With the generic lowlevel path (armada_370_xp_barebox_entry) the board does not reach the banner at all; independently from ARMADA_370_XP_DDR_SIZE_MASK value. With the previous workaround-based lowlevel code restored, the board boots reliably and reports the correct 512 MiB of DRAM. So at the moment I cannot verify the generic SDRAM detection on RN102 because the board does not boot with that path. GPIO / LED blink: Even with deep-probe enabled and with explicit of_device_ensure_probed_by_alias("gpio0"), "gpio1" and "gpio2", the GPIO blink logic cannot access the controller registers: WARNING: gpio0 regmap not available The mvebu GPIO controller is not a syscon device, so syscon_node_to_regmap() always returns an error. As a result, the blink logic cannot use regmap to access the GPIO registers, and the LEDs are not initialized in time during early disk power-on. The previous implementation used direct MMIO access to the GPIO registers, which worked correctly on RN102/RN104, but was removed during the cleanup. Without either restoring that path or providing a regmap backend for the mvebu GPIO controller, the LED blink feature cannot function. Let me know which direction you prefer. I can restore the direct MMIO access for the blink logic if that is acceptable. > > Sascha > > -- > Pengutronix e.K. | = | > Steuerwalder Str. 21 | http://www.pengutronix.de/ = | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 = | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 = | >