* Booting mx25 based device from SD and NOR
@ 2012-05-22 12:11 Roberto Nibali
2012-05-22 18:42 ` Sascha Hauer
0 siblings, 1 reply; 24+ messages in thread
From: Roberto Nibali @ 2012-05-22 12:11 UTC (permalink / raw)
To: barebox
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Hi
I have been trying to boot a customized mx25 based device using barebox and
I seem to be missing a few basic pointers, I believe, since it does not
work. I have attached my config and put my current patch-set online:
http://pastebin.com/KUVAwWRk. It's based on git commit 'dadcf5bd8f715'.
I don't know if the way of adding the boatloader to the SD card for later
installing it onto NOR flash is the correct one. I currently issue a:
sudo dd if=barebox.bin of=/dev/sdc bs=512 skip=2 seek=2 && sync
sdc being the SD card. I wonder if the environment has to be put somewhere
into a partition or if it can be glued into the barebox image. Because
loading the barebox.bin as a secondary stage bootloader from within uboot
version 2009.08 works somehow:
Board: SID1 NOAH
registered netconsole as cs1
imx-esdhc@mci0: registered as mci0
imx-esdhc@imx-esdhc0: timeout 1
Cannot reset the SD/MMC card
ehci@ehci0: USB EHCI 1.00
cfi_flash@cfi_flash0: found cfi flash at a0000000, size 67108864
Malloc space: 0x83b00000 -> 0x83efffff (size 4 MB)
Stack space : 0x83af8000 -> 0x83b00000 (size 32 kB)
envfs: wrong magic on /dev/env0
no valid environment found on /dev/env0. Using default environment
running /env/bin/init...
Hit any key to stop autoboot: 3
type update_kernel nor [<imagename>] to update kernel into flash
type update_root nor [<imagename>] to update rootfs into flash
sid1-noah:/
sid1-noah:/ devinfo
devices:
`---- net
`---- imx_serial0
`---- cs0
`---- mem0
`---- 0x00000000-0x03ffffff: /dev/ram0
`---- imx_iim0
`---- 0x00000000-0x0000001f: /dev/imx_iim_bank0
`---- 0x00000000-0x0000001f: /dev/imx_iim_bank1
`---- 0x00000000-0x0000001f: /dev/imx_iim_bank2
`---- 0x00000000-0x0000001f: /dev/imx_iim_bank3
`---- 0x00000000-0x0000001f: /dev/imx_iim_bank4
`---- 0x00000000-0x0000001f: /dev/imx_iim_bank5
`---- 0x00000000-0x0000001f: /dev/imx_iim_bank6
`---- 0x00000000-0x0000001f: /dev/imx_iim_bank7
`---- ramfs0
`---- devfs0
`---- mem1
`---- 0x00000000-0x000017e7: /dev/defaultenv
`---- mem2
`---- 0x00000000-0xfffffffe: /dev/mem
`---- cs1
`---- i2c-imx0
`---- imx-esdhc0
`---- mci0
`---- fec_imx0
`---- miidev0
`---- 0x00000000-0x0000003f: /dev/phy0
`---- eth0
`---- ehci0
`---- cfi_flash0
`---- 0x00000000-0x03ffffff: /dev/nor0
`---- 0x00000000-0x0003ffff: /dev/self
`---- 0x00040000-0x0005ffff: /dev/env0
`---- 0x00000000-0x0003ffff: /dev/nor0.barebox
`---- 0x00040000-0x0005ffff: /dev/nor0.bareboxenv
`---- 0x00060000-0x0035ffff: /dev/nor0.kernel
`---- 0x00360000-0x03ffffff: /dev/nor0.root
drivers:
imx_serial
ramfs
devfs
fat
tftp
imx_iim
fec_imx
miidev
cfi_flash
<NULL>
ehci
ohci
imx_spi
i2c-imx
mci
imx-esdhc
fb
imxfb
at25x
mem
cramfs
sid1-noah:/ meminfo
max system bytes = 516096
system bytes = 516096
in use bytes = 495984
sid1-noah:/ iomem
0x00000000 - 0xfffffffe (size 0xffffffff) iomem
0x43f80000 - 0x43f80fff (size 0x00001000) i2c-imx0
0x43f90000 - 0x43f90fff (size 0x00001000) imx_serial0
0x50038000 - 0x50038fff (size 0x00001000) fec_imx0
0x53fb4000 - 0x53fb4fff (size 0x00001000) imx-esdhc0
0x53ff0000 - 0x53ff0fff (size 0x00001000) imx_iim0
0x53ff4500 - 0x53ff44ff (size 0x00000000) ehci0
0x53ff4540 - 0x53ff453f (size 0x00000000) ehci0
0x80000000 - 0x83ffffff (size 0x04000000) ram0
0x83af8000 - 0x83afffff (size 0x00008000) stack
0x83b00000 - 0x83efffff (size 0x00400000) malloc space
0x83f00000 - 0x83f3fcf4 (size 0x0003fcf5) barebox
0x83f42124 - 0x83f48688 (size 0x00006565) bss
0xa0000000 - 0xa3ffffff (size 0x04000000) cfi_flash0
sid1-noah:/ cpufreq 532
Switched CPU frequency to 532MHz
sid1-noah:/ dump_clocks
mpll: 532000000 Hz
upll: 240000000 Hz
arm: 399000000 Hz
ahb: 133000000 Hz
uart: 33250000 Hz
gpt: 66500000 Hz
nand: 33250000 Hz
lcd: 66500000 Hz
i2c: 120000000 Hz
sdhc1: 66500000 Hz
sid1-noah:/ cpufreq 399
Switched CPU frequency to 399MHz
sid1-noah:/ dump_clocks
mpll: 399000000 Hz
upll: 240000000 Hz
arm: 299250000 Hz
ahb: 99750000 Hz
uart: 24937500 Hz
gpt: 49875000 Hz
nand: 24937500 Hz
lcd: 49875000 Hz
i2c: 120000000 Hz
sdhc1: 49875000 Hz
I'm glad for any pointers.
Best regards
Roberto
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From 459856c3c98c8453e7d0e2f68b354e9817308458 Mon Sep 17 00:00:00 2001
From: Roberto Nibali <rnibali@gmail.com>
Date: Mon, 21 May 2012 12:38:24 +0200
Subject: [PATCH 2/6] Default config file for NOAH
---
arch/arm/configs/noah_defconfig | 97 +++++++++++++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 arch/arm/configs/noah_defconfig
diff --git a/arch/arm/configs/noah_defconfig b/arch/arm/configs/noah_defconfig
new file mode 100644
index 0000000..152f0bf
--- /dev/null
+++ b/arch/arm/configs/noah_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARCH_IMX=y
+CONFIG_ARCH_IMX_EXTERNAL_BOOT=y
+CONFIG_ARCH_IMX25=y
+CONFIG_MACH_MX25_NOAH=y
+CONFIG_IMX_CLKO=y
+CONFIG_IMX_IIM=y
+CONFIG_AEABI=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_BROKEN=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_PROMPT="sid1-noah:"
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/fq-sid1-mx25-noah/env"
+CONFIG_BAREBOXENV_TARGET=y
+CONFIG_ENABLE_FLASH_NOISE=y
+CONFIG_ENABLE_PARTITION_NOISE=y
+CONFIG_ENABLE_DEVICE_NOISE=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_AUTOMOUNT=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_SAVES=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_SHA224SUM=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_MTEST_ALTERNATIVE=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_DRIVER_SPI_IMX=y
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
+CONFIG_DRIVER_CFI=y
+# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
+# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set
+CONFIG_MTD=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_OHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
+CONFIG_DRIVER_VIDEO_IMX=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_EEPROM_AT25=y
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_BZLIB=y
+CONFIG_LZO_DECOMPRESS=y
--
1.7.9.5
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^ permalink raw reply [flat|nested] 24+ messages in thread* Re: Booting mx25 based device from SD and NOR 2012-05-22 12:11 Booting mx25 based device from SD and NOR Roberto Nibali @ 2012-05-22 18:42 ` Sascha Hauer 2012-05-23 10:43 ` Roberto Nibali 0 siblings, 1 reply; 24+ messages in thread From: Sascha Hauer @ 2012-05-22 18:42 UTC (permalink / raw) To: Roberto Nibali; +Cc: barebox Hi Roberto, On Tue, May 22, 2012 at 02:11:46PM +0200, Roberto Nibali wrote: > Hi > > I have been trying to boot a customized mx25 based device using barebox and > I seem to be missing a few basic pointers, I believe, since it does not > work. I have attached my config and put my current patch-set online: > http://pastebin.com/KUVAwWRk. It's based on git commit 'dadcf5bd8f715'. > > I don't know if the way of adding the boatloader to the SD card for later > installing it onto NOR flash is the correct one. I currently issue a: > > sudo dd if=barebox.bin of=/dev/sdc bs=512 skip=2 seek=2 && sync > You have configured barebox for external boot mode. This is not suitable for SD cards, you have to use internal bootmode instead. This requires that you provide a dtd header, see for example the babbage board for how to do this. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-22 18:42 ` Sascha Hauer @ 2012-05-23 10:43 ` Roberto Nibali 2012-05-23 11:47 ` Eric Bénard 0 siblings, 1 reply; 24+ messages in thread From: Roberto Nibali @ 2012-05-23 10:43 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 16810 bytes --] Hi Sascha > I have been trying to boot a customized mx25 based device using barebox > and > > I seem to be missing a few basic pointers, I believe, since it does not > > work. I have attached my config and put my current patch-set online: > > http://pastebin.com/KUVAwWRk. It's based on git commit 'dadcf5bd8f715'. > > > > I don't know if the way of adding the boatloader to the SD card for later > > installing it onto NOR flash is the correct one. I currently issue a: > > > > sudo dd if=barebox.bin of=/dev/sdc bs=512 skip=2 seek=2 && sync > > > > You have configured barebox for external boot mode. This is not suitable > for SD cards, you have to use internal bootmode instead. This requires > that you provide a dtd header, see for example the babbage board for how > to do this. > > To be honest, after reading section 7 in the RM of the mx24, reading dozens of post, your comments in the source code with regard to internal vs. external boot, I still seem to be confused. Nevertheless, your suggestion works!! Also, they way I setup my SD card was slightly wrong; the reserved 2048 sectors on my SD card confused me, but the reason is the 8-byte alignment boundary for speed reasons. To better document things, here are the steps that lead to my mx25 based device booting barebox as first stage boot loader from SD card in internal boot mode (my SD card being detected as /dev/sdc): root@pc-develop:~# fdisk -l /dev/sdc Disk /dev/sdc: 2002 MB, 2002780160 bytes 62 heads, 62 sectors/track, 1017 cylinders, total 3911680 sectors Units = sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disk identifier: 0xfb7a8756 Device Boot Start End Blocks Id System /dev/sdc1 * 2048 4095 1024 83 Linux /dev/sdc2 4096 1052671 524288 b W95 FAT32 /dev/sdc3 1052672 3911679 1429504 83 Linux root@pc-develop:~# umount /media/216B-BCD2 root@pc-develop:~# mkfs.vfat /dev/sdc2 mkfs.vfat 3.0.12 (29 Oct 2011) root@pc-develop:~# mkfs.ext3 /dev/sdc3 mke2fs 1.42 (29-Nov-2011) [...] root@pc-develop:~# dd if=./barebox.bin of=/dev/sdc1 bs=512 553+1 records in 553+1 records out 283144 bytes (283 kB) copied, 0.0504609 s, 5.6 MB/s Set the switches to boot from SD on the mx25 device and power on. It successfully loads barebox and I can mount the fat partition (of course the other partition is unmountable, because there is no ext2/3 support in barebox). Booting from my environment currently fails, but I reckon it has to do with my configuration settings. Here is where it gets so far: [ 0.000000] PID hash table entries: 256 (order: -2, 1024 bytes) [ 0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Memory: 64MB = 64MB total [ 0.000000] Memory: 57860k/57860k available, 7676k reserved, 0K highmem [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] vmalloc : 0xc4800000 - 0xff000000 ( 936 MB) [ 0.000000] lowmem : 0xc0000000 - 0xc4000000 ( 64 MB) [ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB) [ 0.000000] .text : 0xc0008000 - 0xc062e608 (6298 kB) [ 0.000000] .init : 0xc062f000 - 0xc0665000 ( 216 kB) [ 0.000000] .data : 0xc0666000 - 0xc06a4a48 ( 251 kB) [ 0.000000] .bss : 0xc06a4a6c - 0xc06e7084 ( 266 kB) [ 0.000000] SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [ 0.000000] NR_IRQS:336 [ 0.000000] MXC IRQ initialized [ 0.000000] CPU identified as i.MX25, unknown revision [ 0.000000] sched_clock: 32 bits at 66MHz, resolution 15ns, wraps every 64585ms [ 0.000000] Console: colour dummy device 80x30 [ 0.000494] Calibrating delay loop... 199.06 BogoMIPS (lpj=995328) [ 0.070322] pid_max: default: 32768 minimum: 301 [ 0.070847] Mount-cache hash table entries: 512 [ 0.072033] CPU: Testing write buffer coherency: ok [ 0.072302] ftrace: allocating 15086 entries in 45 pages [ 0.168557] Setting up static identity map for 0x80480fc8 - 0x80481004 [ 0.171939] devtmpfs: initialized [ 0.175457] NET: Registered protocol family 16 [ 0.187052] gpiochip_add: registered GPIOs 0 to 31 on device: imx31-gpio.0 [ 0.189598] gpiochip_add: registered GPIOs 32 to 63 on device: imx31-gpio.1 [ 0.191705] gpiochip_add: registered GPIOs 64 to 95 on device: imx31-gpio.2 [ 0.193832] gpiochip_add: registered GPIOs 96 to 127 on device: imx31-gpio.3 [ 0.320820] bio: create slab <bio-0> at 0 [ 0.326517] SCSI subsystem initialized [ 0.330858] usbcore: registered new interface driver usbfs [ 0.331815] usbcore: registered new interface driver hub [ 0.332898] usbcore: registered new device driver usb [ 0.343553] Advanced Linux Sound Architecture Driver Version 1.0.24. [ 0.347646] Bluetooth: Core ver 2.16 [ 0.348460] NET: Registered protocol family 31 [ 0.348508] Bluetooth: HCI device and connection manager initialized [ 0.348556] Bluetooth: HCI socket layer initialized [ 0.348590] Bluetooth: L2CAP socket layer initialized [ 0.348704] Bluetooth: SCO socket layer initialized [ 0.351609] cfg80211: Calling CRDA to update world regulatory domain [ 0.353985] Switching to clocksource mxc_timer1 [ 0.499000] NET: Registered protocol family 2 [ 0.499750] IP route cache hash table entries: 1024 (order: 0, 4096 bytes) [ 0.501890] TCP established hash table entries: 2048 (order: 2, 16384 bytes) [ 0.502117] TCP bind hash table entries: 2048 (order: 1, 8192 bytes) [ 0.502236] TCP: Hash tables configured (established 2048 bind 2048) [ 0.502269] TCP reno registered [ 0.502316] UDP hash table entries: 256 (order: 0, 4096 bytes) [ 0.502402] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) [ 0.503200] NET: Registered protocol family 1 [ 0.504788] RPC: Registered named UNIX socket transport module. [ 0.504838] RPC: Registered udp transport module. [ 0.504867] RPC: Registered tcp transport module. [ 0.504894] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.507432] FQ mxc_sim driver started: v1.1 (2012/02/21) [ 0.585854] NTFS driver 2.1.30 [Flags: R/W]. [ 0.588284] JFFS2 version 2.2. (NAND) ¬© 2001-2006 Red Hat, Inc. [ 0.591345] fuse init (API version 7.18) [ 0.595203] msgmni has been set to 113 [ 0.601501] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) [ 0.601562] io scheduler noop registered [ 0.601755] io scheduler cfq registered (default) [ 0.607105] imx-sdma imx35-sdma: loaded firmware 1.0 [ 0.635752] imx-sdma imx35-sdma: initialized [ 0.637804] Serial: IMX driver [ 0.638199] imx21-uart.0: ttymxc0 at MMIO 0x43f90000 (irq = 45) is a IMX [ 1.089977] console [ttymxc0] enabled [ 1.118473] loop: module loaded [ 1.121838] at24 0-0050: 65024 byte 24c16 EEPROM, writable, 128 bytes/write [ 1.135587] physmap platform flash device: 04000000 at a0000000 [ 1.146468] physmap-flash physmap-flash.0: map_probe failed [ 1.181758] spi_imx_setup: mode 3, 8 bpw, 20000000 hz [ 1.187997] spi_imx imx35-cspi.2: probed [ 1.196679] FEC Ethernet Driver [ 1.207440] fec_enet_mii_bus: probed [ 1.216038] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 1.222774] mxc-ehci mxc-ehci.0: initializing i.MX USB Controller [ 1.254156] mxc-ehci mxc-ehci.0: Freescale On-Chip EHCI Host Controller [ 1.261079] mxc-ehci mxc-ehci.0: new USB bus registered, assigned bus number 1 [ 1.294278] mxc-ehci mxc-ehci.0: irq 37, io mem 0x53ff4000 [ 1.314205] mxc-ehci mxc-ehci.0: USB 2.0 started, EHCI 1.00 [ 1.320074] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.327010] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.334342] usb usb1: Product: Freescale On-Chip EHCI Host Controller [ 1.340823] usb usb1: Manufacturer: Linux 3.3.4-00448-g80850fc-dirty ehci_hcd [ 1.348051] usb usb1: SerialNumber: mxc-ehci.0 [ 1.355432] hub 1-0:1.0: USB hub found [ 1.359293] hub 1-0:1.0: 1 port detected [ 1.363954] mxc-ehci mxc-ehci.1: initializing i.MX USB Controller [ 1.394159] mxc-ehci mxc-ehci.1: Freescale On-Chip EHCI Host Controller [ 1.400983] mxc-ehci mxc-ehci.1: new USB bus registered, assigned bus number 2 [ 1.434279] mxc-ehci mxc-ehci.1: irq 35, io mem 0x53ff4400 [ 1.454377] mxc-ehci mxc-ehci.1: USB 2.0 started, EHCI 1.00 [ 1.460251] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.467188] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.474518] usb usb2: Product: Freescale On-Chip EHCI Host Controller [ 1.480999] usb usb2: Manufacturer: Linux 3.3.4-00448-g80850fc-dirty ehci_hcd [ 1.488224] usb usb2: SerialNumber: mxc-ehci.1 [ 1.495664] hub 2-0:1.0: USB hub found [ 1.499525] hub 2-0:1.0: 1 port detected [ 1.506043] usbcore: registered new interface driver uas [ 1.511399] Initializing USB Mass Storage driver... [ 1.517643] usbcore: registered new interface driver usb-storage [ 1.523694] USB Mass Storage support registered. [ 1.529647] usbcore: registered new interface driver libusual [ 1.537456] usbcore: registered new interface driver usbserial [ 1.544447] USB Serial support registered for generic [ 1.550387] usbcore: registered new interface driver usbserial_generic [ 1.557266] usbserial: USB Serial Driver core [ 1.562532] usbcore: registered new interface driver fq_cpr40 [ 1.569460] usbcore: registered new interface driver sisusb [ 1.579705] imxdi_rtc imxdi_rtc.0: rtc core: registered imxdi_rtc as rtc0 [ 1.587516] i2c /dev entries driver [ 1.592996] Driver for 1-wire Dallas network protocol. [ 1.603270] imx2-wdt imx2-wdt.0: IMX2+ Watchdog Timer enabled. timeout=60s (nowayout=0) [ 1.613364] usbcore: registered new interface driver btusb [ 1.619238] cpuidle: using governor ladder [ 1.623379] cpuidle: using governor menu [ 1.628129] sdhci: Secure Digital Host Controller Interface driver [ 1.634609] sdhci: Copyright(c) Pierre Ossman [ 1.639176] spi_imx_setup: mode 3, 8 bpw, 20000000 hz [ 1.644533] mmc_spi spi2.0: ASSUMING 3.2-3.4 V slot power [ 1.651878] mmc_spi spi2.0: SD/MMC host mmc0, no DMA, no WP, no poweroff [ 1.659804] sdhci-pltfm: SDHCI platform and OF driver helper [ 1.681925] sdhci_pltfm_init: MMC quirks: 651ec000 (1696514048) [ 1.814297] usb 2-1: new full-speed USB device number 2 using mxc-ehci [ 1.838533] sdhci [sdhci_add_host()]: mmc1: Auto-CMD23 unavailable [ 1.985712] usb 2-1: not running at top speed; connect to a high speed hub [ 2.011883] usb 2-1: New USB device found, idVendor=0424, idProduct=2513 [ 2.043754] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.055683] esdhc_set_clock: Current dividers: pre_div=2 div=1 [ 2.077609] mmc1: SDHCI controller on sdhci-esdhc-imx25.0 [sdhci-esdhc-imx25.0] using DMA [ 2.134930] hub 2-1:1.0: USB hub found [ 2.145712] hub 2-1:1.0: 3 ports detected [ 2.176905] usbcore: registered new interface driver usbhid [ 2.182523] usbhid: USB HID core driver [ 4.674272] spi_imx_setup: mode 7, 8 bpw, 20000000 hz [ 4.681104] spi_imx_setup: mode 3, 8 bpw, 20000000 hz [ 4.688547] aic3x_i2c_probe: Probing for TLV320AIC3x (selected model=AIC3101) [ 4.696167] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.701859] aic3x_modinit: Success registering the TLV320AIC3x I2C driver [ 4.713884] aic3x_probe: Probing AIC3x [ 4.718488] aic3x_init: Setting Default Volume, Routes and Mute [ 4.724688] aic3x_probe: Setting AIC3x snd_controls [ 4.729819] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.735520] aic3x_probe: Adding AIC3x widgets [ 4.745137] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.752725] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.759139] asoc: tlv320aic3x-hifi <-> imx-ssi.0 mapping ok [ 4.766926] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.775269] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.780267] mmc0: host doesn't support card's voltages [ 4.787462] ASoC: Platform initialized [ 4.791252] ALSA device list: [ 4.794576] #0: noah-audio [ 4.800269] TCP cubic registered [ 4.803540] NET: Registered protocol family 17 [ 4.808211] mmc0: error -22 whilst initialising SDIO card [ 4.814457] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.819633] Bluetooth: RFCOMM TTY layer initialized [ 4.824939] Bluetooth: RFCOMM socket layer initialized [ 4.830245] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.835465] Bluetooth: RFCOMM ver 1.11 [ 4.839258] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 4.844912] Bluetooth: BNEP filters: protocol multicast [ 4.850216] Bluetooth: HIDP (Human Interface Emulation) ver 1.2 [ 4.856400] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.863768] imxdi_rtc imxdi_rtc.0: setting system clock to 1970-01-01 00:00:03 UTC (3) [ 4.872019] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.877172] mmc0: host doesn't support card's voltages [ 4.882342] mmc0: error -22 whilst initialising SD card [ 4.889411] eth0: Freescale FEC PHY driver [SMSC LAN8710/LAN8720] (mii_bus:phy_addr=imx25-fec-1:00, irq=-1) [ 4.900151] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.906156] spi_imx_setup: mode 3, 8 bpw, 400000 hz [ 4.911135] mmc0: host doesn't support card's voltages [ 4.916461] mmc0: error -22 whilst initialising MMC card [ 4.922858] esdhc_set_clock: Current dividers: pre_div=2 div=1 [ 4.944164] esdhc_set_clock: Current dividers: pre_div=2 div=1 [ 4.950040] esdhc_set_clock: Adjustment 1 dividers: pre_div=16 div=11 [ 4.956510] desired SD clock: 400000, actual=377840 (max=66500000) [ 4.962715] esdhc_set_clock: Adjustment 2 dividers: pre_div=1 div=1 [ 5.010020] mmc1: host does not support reading read-only switch. assuming write-enable. [ 5.019134] esdhc_set_clock: Current dividers: pre_div=2 div=1 [ 5.025008] esdhc_set_clock: Adjustment 1 dividers: pre_div=2 div=1 [ 5.031304] desired SD clock: 50000000, actual=33250000 (max=66500000) [ 5.037857] esdhc_set_clock: Adjustment 2 dividers: pre_div=1 div=1 [ 5.045723] mmc1: new high speed SD card at address 0002 [ 5.052267] blk_limits_max_hw_sectors: set to minimum 8 [ 5.058272] mmcblk0: mmc1:0002 00000 1.86 GiB [ 5.072167] mmcblk0: p1 p2 p3 [ 6.884651] PHY: imx25-fec-1:00 - Link is Up - 100/Full [ 6.924205] Sending DHCP requests ., OK [ 7.934638] IP-Config: Got DHCP answer from 0.0.0.0, my address is 192.168.1.211 [ 7.942931] IP-Config: Complete: [ 7.946490] device=eth0, addr=192.168.1.211, mask=255.255.255.0, gw=192.168.1.1, [ 7.954238] host=192.168.1.211, domain=domini.int, nis-domain=(none), [ 7.961160] bootserver=0.0.0.0, rootserver=192.168.1.23, rootpath= [ 103.029081] VFS: Unable to mount root fs via NFS, trying floppy. [ 103.036763] VFS: Cannot open root device "nfs" or unknown-block(2,0) [ 103.043157] Please append a correct "root=" boot option; here are the available partitions: [ 103.052007] b300 1955840 mmcblk0 driver: mmcblk [ 103.057512] b301 1024 mmcblk0p1 00000000-0000-0000-0000-000000000mmcblk0p1 [ 103.065670] b302 524288 mmcblk0p2 00000000-0000-0000-0000-000000000mmcblk0p2 [ 103.073744] b303 1429504 mmcblk0p3 00000000-0000-0000-0000-000000000mmcblk0p3 [ 103.081904] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(2,0) [ 103.090367] [<c000fb8c>] (unwind_backtrace+0x0/0x13c) from [<c047e360>] (dump_stack+0x20/0x24) [ 103.099148] [<c047e360>] (dump_stack+0x20/0x24) from [<c047e3f0>] (panic+0x8c/0x1d0) [ 103.107044] [<c047e3f0>] (panic+0x8c/0x1d0) from [<c062fc38>] (mount_block_root+0x164/0x214) [ 103.115630] [<c062fc38>] (mount_block_root+0x164/0x214) from [<c062fdc4>] (mount_root+0xdc/0x100) [ 103.124644] [<c062fdc4>] (mount_root+0xdc/0x100) from [<c062ff0c>] (prepare_namespace+0x124/0x188) [ 103.133674] [<c062ff0c>] (prepare_namespace+0x124/0x188) from [<c062f890>] (kernel_init+0xf4/0x128) [ 103.142860] [<c062f890>] (kernel_init+0xf4/0x128) from [<c000a5c8>] (kernel_thread_exit+0x0/0x8) Thank you very much for your pointers. Best regards Roberto [-- Attachment #1.2: Type: text/html, Size: 19969 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-23 10:43 ` Roberto Nibali @ 2012-05-23 11:47 ` Eric Bénard 2012-05-24 12:49 ` Roberto Nibali 0 siblings, 1 reply; 24+ messages in thread From: Eric Bénard @ 2012-05-23 11:47 UTC (permalink / raw) To: barebox Le Wed, 23 May 2012 12:43:47 +0200, Roberto Nibali <rnibali@gmail.com> a écrit : > Set the switches to boot from SD on the mx25 device and power on. It > successfully loads barebox and I can mount the fat partition (of course the > other partition is unmountable, because there is no ext2/3 support in > barebox). Booting from my environment currently fails, but I reckon it has > to do with my configuration settings. Here is where it gets so far: > .../... > [ 103.029081] VFS: Unable to mount root fs via NFS, trying floppy. > [ 103.036763] VFS: Cannot open root device "nfs" or unknown-block(2,0) > [ 103.043157] Please append a correct "root=" boot option; here are the > available partitions: > [ 103.052007] b300 1955840 mmcblk0 driver: mmcblk > [ 103.057512] b301 1024 mmcblk0p1 > 00000000-0000-0000-0000-000000000mmcblk0p1 > [ 103.065670] b302 524288 mmcblk0p2 > 00000000-0000-0000-0000-000000000mmcblk0p2 > [ 103.073744] b303 1429504 mmcblk0p3 > 00000000-0000-0000-0000-000000000mmcblk0p3 > .../... > Thank you very much for your pointers. > add to your bootargs root=/dev/mmcblk0p3 rootfstype=ext3 or something like this Eric _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-23 11:47 ` Eric Bénard @ 2012-05-24 12:49 ` Roberto Nibali 2012-05-24 12:58 ` Eric Bénard 0 siblings, 1 reply; 24+ messages in thread From: Roberto Nibali @ 2012-05-24 12:49 UTC (permalink / raw) To: Eric Bénard; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 3390 bytes --] Hi > > Set the switches to boot from SD on the mx25 device and power on. It > > successfully loads barebox and I can mount the fat partition (of course > the > > other partition is unmountable, because there is no ext2/3 support in > > barebox). Booting from my environment currently fails, but I reckon it > has > > to do with my configuration settings. Here is where it gets so far: > > .../... > > [ 103.029081] VFS: Unable to mount root fs via NFS, trying floppy. > > [ 103.036763] VFS: Cannot open root device "nfs" or unknown-block(2,0) > > [ 103.043157] Please append a correct "root=" boot option; here are the > > available partitions: > > [ 103.052007] b300 1955840 mmcblk0 driver: mmcblk > > [ 103.057512] b301 1024 mmcblk0p1 > > 00000000-0000-0000-0000-000000000mmcblk0p1 > > [ 103.065670] b302 524288 mmcblk0p2 > > 00000000-0000-0000-0000-000000000mmcblk0p2 > > [ 103.073744] b303 1429504 mmcblk0p3 > > 00000000-0000-0000-0000-000000000mmcblk0p3 > > .../... > > Thank you very much for your pointers. > > > add to your bootargs root=/dev/mmcblk0p3 rootfstype=ext3 or something > like this > > I haven't found a combination of root/rootfstype yet that permits me to boot from barebox either from NFS, TFTP, MMC/SD or NOR yet. No matter what I try, the kernel spits back at me. Also I have the problem that my NOR is only detected when using barebox as a second stage boot loader from uboot. If booting from SD into barebox, the NOR is not detected. I have added the following changes to figure out what's going on: diff --git a/drivers/nor/cfi_flash.c b/drivers/nor/cfi_flash.c index 654e647..7884ca4 100644 --- a/drivers/nor/cfi_flash.c +++ b/drivers/nor/cfi_flash.c @@ -990,13 +990,17 @@ static int cfi_probe (struct device_d *dev) info->size = flash_get_size(info); if (info->flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank at 0x%08x - Size = 0x%08lx = %ld MB\n", + printf("## Unknown FLASH on Bank at 0x%08x - Size = 0x%08lx = %ld MB\n", dev->resource[0].start, info->size, info->size << 20); + printf("cfi flash (id=%08lX vend=%06X manu=%06X devid=%06X extid=%06X)\n", + info->flash_id, info->vendor, info->manufacturer_id, info->device_id, + info->device_id2); return -ENODEV; } - dev_info(dev, "found cfi flash at %p, size %ld\n", - info->base, info->size); + dev_info(dev, "cfi flash (id=%08lX vend=%06X manu=%06X devid=%06X extid=%06X) at %p, size %ldMB + info->flash_id, info->vendor, info->manufacturer_id, info->device_id, + info->device_id2, info->base, info->size/1024/1024); info->cdev.name = asprintf("nor%d", dev->id); info->cdev.size = info->size; Loading barebox as second stage bootloader gives me following output: [...] cfi_flash@cfi_flash0: cfi flash (id=01000000 vend=000002 manu=000001 devid=00007E extid=002301) at a0000000, size 64MB [...] Loading barebox as a first stage bootloader directly from SD card results in the following: [...] ## Unknown FLASH on Bank at 0xa0000000 - Size = 0x00000000 = 0 MB cfi flash (id=0000FFFF vend=000000 manu=000000 devid=000000 extid=000000) [...] What's going on here? Best regards Roberto [-- Attachment #1.2: Type: text/html, Size: 4516 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-24 12:49 ` Roberto Nibali @ 2012-05-24 12:58 ` Eric Bénard 2012-05-24 13:18 ` Roberto Nibali 0 siblings, 1 reply; 24+ messages in thread From: Eric Bénard @ 2012-05-24 12:58 UTC (permalink / raw) To: Roberto Nibali; +Cc: barebox Hi Roberto, Le Thu, 24 May 2012 14:49:36 +0200, Roberto Nibali <rnibali@gmail.com> a écrit : > I haven't found a combination of root/rootfstype yet that permits me to > boot from barebox either from NFS, TFTP, MMC/SD or NOR yet. No matter what > I try, the kernel spits back at me. > well NAND boot + nand rootfs works fine here (cpuimx25) and I assume NAND boot + sd rootfs would work as sd is properly detected during boot. > Also I have the problem that my NOR is only detected when using barebox as > a second stage boot loader from uboot. If booting from SD into barebox, the > NOR is not detected. I have added the following changes to figure out > what's going on: > > .../... > What's going on here? > bad iomux and/or bad WEIM configuration Eric _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-24 12:58 ` Eric Bénard @ 2012-05-24 13:18 ` Roberto Nibali 2012-05-24 13:31 ` Eric Bénard 2012-05-24 17:17 ` Sascha Hauer 0 siblings, 2 replies; 24+ messages in thread From: Roberto Nibali @ 2012-05-24 13:18 UTC (permalink / raw) To: Eric Bénard; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 2055 bytes --] Hi Eric On Thu, May 24, 2012 at 2:58 PM, Eric Bénard <eric@eukrea.com> wrote: > Hi Roberto, > > Le Thu, 24 May 2012 14:49:36 +0200, > Roberto Nibali <rnibali@gmail.com> a écrit : > > I haven't found a combination of root/rootfstype yet that permits me to > > boot from barebox either from NFS, TFTP, MMC/SD or NOR yet. No matter > what > > I try, the kernel spits back at me. > > > well NAND boot + nand rootfs works fine here (cpuimx25) and I assume > NAND boot + sd rootfs would work as sd is properly detected during boot. > > Yep, I believe it's more a question of me setting the parameters correctly upon boot. But without a proper low level init (which I don't have because I do not really understand all the details of the low level code), there are other factors which could inhibit the proper boot, as you mention below. > > Also I have the problem that my NOR is only detected when using barebox > as > > a second stage boot loader from uboot. If booting from SD into barebox, > the > > NOR is not detected. I have added the following changes to figure out > > what's going on: > > > > .../... > > What's going on here? > > > bad iomux and/or bad WEIM configuration I support WEIM configuration is done in the low level part, isn't it? Where would I find an appropriate example? I have been reading all the fsl board's low_level codes, but have a hard time figuring out how to apply it to my board. With regard to the IOMUX, I was under the impression that it does not matter much, since after low level code run, the execution path is: late_initcall() mem_initcall() device_initcall() --> add_cfi_flash_device() console_initcall() --> mxc_iomux_v3_setup_multiple_pads() core_initcall() So CFI/NOR detection happens before IOMUX setup, at least that's what I have gathered for my board copying from various other examples in barebox. What would the correct code execution path be from the architectural point of view? Best regards Roberto [-- Attachment #1.2: Type: text/html, Size: 2854 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-24 13:18 ` Roberto Nibali @ 2012-05-24 13:31 ` Eric Bénard 2012-05-25 9:04 ` Roberto Nibali 2012-05-24 17:17 ` Sascha Hauer 1 sibling, 1 reply; 24+ messages in thread From: Eric Bénard @ 2012-05-24 13:31 UTC (permalink / raw) To: Roberto Nibali; +Cc: barebox Hi, Le Thu, 24 May 2012 15:18:13 +0200, Roberto Nibali <rnibali@gmail.com> a écrit : > On Thu, May 24, 2012 at 2:58 PM, Eric Bénard <eric@eukrea.com> wrote: > > Le Thu, 24 May 2012 14:49:36 +0200, > > Roberto Nibali <rnibali@gmail.com> a écrit : > > > I haven't found a combination of root/rootfstype yet that permits me to > > > boot from barebox either from NFS, TFTP, MMC/SD or NOR yet. No matter > > what > > > I try, the kernel spits back at me. > > > > > well NAND boot + nand rootfs works fine here (cpuimx25) and I assume > > NAND boot + sd rootfs would work as sd is properly detected during boot. > > > > Yep, I believe it's more a question of me setting the parameters correctly > upon boot. But without a proper low level init (which I don't have because > I do not really understand all the details of the low level code), there > are other factors which could inhibit the proper boot, as you mention below. > if your sd's partitions are detected by the kernel you must be able to boot a rootfs on it it's just a bootargs problem (and kernel configuration to have the right FS included). > > > > Also I have the problem that my NOR is only detected when using barebox > > as > > > a second stage boot loader from uboot. If booting from SD into barebox, > > the > > > NOR is not detected. I have added the following changes to figure out > > > what's going on: > > > > > > .../... > > > What's going on here? > > > > > bad iomux and/or bad WEIM configuration > > > I support WEIM configuration is done in the low level part, isn't it? Where > would I find an appropriate example? I have been reading all the fsl > board's low_level codes, but have a hard time figuring out how to apply it > to my board. > > With regard to the IOMUX, I was under the impression that it does not > matter much, since after low level code run, the execution path is: > > late_initcall() > mem_initcall() > device_initcall() --> add_cfi_flash_device() > console_initcall() --> mxc_iomux_v3_setup_multiple_pads() > core_initcall() > > So CFI/NOR detection happens before IOMUX setup, at least that's what I > have gathered for my board copying from various other examples in barebox. > What would the correct code execution path be from the architectural point > of view? > nothing prevents you from moving mxc_iomux_v3_setup_multiple_pads to device_initcall as done in http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c;h=1b8f618138023b88893a024ddc0c078b7b9f2325;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a for the weim setting you may need to do something similar to what is done on line 187 of : http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c;h=63e87c9551c440edab572f5252a503ba4d533161;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a Eric _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-24 13:31 ` Eric Bénard @ 2012-05-25 9:04 ` Roberto Nibali 2012-05-25 10:08 ` Eric Bénard 0 siblings, 1 reply; 24+ messages in thread From: Roberto Nibali @ 2012-05-25 9:04 UTC (permalink / raw) To: Eric Bénard; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 5362 bytes --] Hi Eric > > well NAND boot + nand rootfs works fine here (cpuimx25) and I assume > > > NAND boot + sd rootfs would work as sd is properly detected during > boot. > > > > > > Yep, I believe it's more a question of me setting the parameters > correctly > > upon boot. But without a proper low level init (which I don't have > because > > I do not really understand all the details of the low level code), there > > are other factors which could inhibit the proper boot, as you mention > below. > > > if your sd's partitions are detected by the kernel you must be able to > boot a rootfs on it it's just a bootargs problem (and kernel > configuration to have the right FS included). > That's my understanding too, however it does not work at the moment. But what's really important is that I have NOR support when loading barebox as first stage boot loader from SD card. > > I suppose WEIM configuration is done in the low level part, isn't it? > Where > > would I find an appropriate example? I have been reading all the fsl > > board's low_level codes, but have a hard time figuring out how to apply > it > > to my board. > > > > With regard to the IOMUX, I was under the impression that it does not > > matter much, since after low level code run, the execution path is: > > > > late_initcall() > > mem_initcall() > > device_initcall() --> add_cfi_flash_device() > > console_initcall() --> mxc_iomux_v3_setup_multiple_pads() > > core_initcall() > > > > So CFI/NOR detection happens before IOMUX setup, at least that's what I > > have gathered for my board copying from various other examples in > barebox. > > What would the correct code execution path be from the architectural > point > > of view? > > > nothing prevents you from moving mxc_iomux_v3_setup_multiple_pads to > device_initcall as done in > > http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c;h=1b8f618138023b88893a024ddc0c078b7b9f2325;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a > > Thanks, I have done this now, looks much cleaner. Stil, I wonder about the order of things when powering and booting up the mx25 in general. lowlevel -> AIPS -> MAX (MPR, SGPCR, MGPCR) -> M3IF -> MPLL clock -> other clocks late_initcall -> fec_init mem_initcall -> imx25_mem_init device_initcall -> devices_init console_initcall -> console_init core_initcall -> core_setup > for the weim setting you may need to do something similar to what is > done on line 187 of : > > http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c;h=63e87c9551c440edab572f5252a503ba4d533161;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a > > Now that piece certainly was missing, but how the heck did you find out those register values? Where did you get the information about writing to chip select 0 and selecting: CSCR0U: 0x00008F03 CSCR0L: 0xA0330D01 CSCR0A: 0x002208C0 I have patched mx25-regs.h accordingly and added an equivalent call using the same register values: diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h index 73307c4..8225832 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -72,6 +72,7 @@ #define CCM_LTR1 0x44 #define CCM_LTR2 0x48 #define CCM_LTR3 0x4c +#define CCM_MCR 0x64 #define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) #define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) @@ -107,6 +108,22 @@ #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) +/* Chip Select Registers */ +#define IMX_WEIM_BASE WEIM_BASE +#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x Upper Register */ +#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x Lower Register */ +#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */ +#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */ + +#ifndef __ASSEMBLY__ +static inline void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional) +{ + CSxU(cs) = upper; + CSxL(cs) = lower; + CSxA(cs) = addional; +} +#endif /* __ASSEMBLY__ */ + /* * Definitions for the clocksource driver * But it still does not work. What could be missing? How can I find out more about which chip select I need? I'm practically married to the MX25-RM documentation, but still, it's one heck of a large piece of documentation. I found the following example (using cs2), but I am not sure this helps: @; config WEIM to Async access with EDC, OEA, RWA, RWN, EBC, 16 bit port and PSR WRITE WEIM_CSCR2U, 0x12020802 WRITE WEIM_CSCR2L, 0x80330d03 @ ; config Flash to WRAP 8 mode (by half word accesses) WRITE_H (CS2_BASE_ADDR+0x2384), 0x60 @ ; offset = 0x11c2 << 1 for 16 bit port WRITE_H (CS2_BASE_ADDR+0x2384), 0x03 WRITE_H (CS2_BASE_ADDR+0x0), 0xff @ ; Flash to read mode @ ; config to WEIM Sync access with WRAP8, 16 bit port WRITE WEIM_CSCR2U, 0x13510802 WRITE WEIM_CSCR2L, 0x80330d03 Could it be that I am missing an iomux setting? Clock missing? I am fairly certain that my NOR is at CS0, so the above example from the RM does not help much, I suppose. Best regards Roberto [-- Attachment #1.2: Type: text/html, Size: 7859 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-25 9:04 ` Roberto Nibali @ 2012-05-25 10:08 ` Eric Bénard 2012-05-29 9:06 ` Roberto Nibali 0 siblings, 1 reply; 24+ messages in thread From: Eric Bénard @ 2012-05-25 10:08 UTC (permalink / raw) To: Roberto Nibali; +Cc: barebox Hi Roberto, Le Fri, 25 May 2012 11:04:52 +0200, Roberto Nibali <rnibali@gmail.com> a écrit : > > for the weim setting you may need to do something similar to what is > > done on line 187 of : > > > > http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c;h=63e87c9551c440edab572f5252a503ba4d533161;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a > > > > > Now that piece certainly was missing, but how the heck did you find out > those register values? Where did you get the information about writing to > chip select 0 and selecting: > > CSCR0U: 0x00008F03 > CSCR0L: 0xA0330D01 > CSCR0A: 0x002208C0 > you need the reference manual of the i.MX25 to know the meaning of these registers and the datasheet of your flash to know it's timings then you can calculate the value to put in the registers. Eric _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-25 10:08 ` Eric Bénard @ 2012-05-29 9:06 ` Roberto Nibali 2012-05-29 9:29 ` Sascha Hauer 0 siblings, 1 reply; 24+ messages in thread From: Roberto Nibali @ 2012-05-29 9:06 UTC (permalink / raw) To: Eric Bénard; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 6697 bytes --] Hi Eric > > > http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c;h=63e87c9551c440edab572f5252a503ba4d533161;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a > > > > > > > > Now that piece certainly was missing, but how the heck did you find out > > those register values? Where did you get the information about writing to > > chip select 0 and selecting: > > > > CSCR0U: 0x00008F03 > > CSCR0L: 0xA0330D01 > > CSCR0A: 0x002208C0 > > > you need the reference manual of the i.MX25 to know the meaning of > these registers and the datasheet of your flash to know it's timings > then you can calculate the value to put in the registers. > > I have found them in an old uboot tree a previous person patched to have working support for NOR on boot. The values are: { .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, }, { .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, }, { .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, }, Still it does not work at all, it does not display anything upon boot. How could I debug this? I have adapted the DCD header (not needed in my case) according to what the old uboot patches did, I have also put this into my lowlevel_init (which I have studied extensively over the weekend and I start understanding much better): /* Check 24.3.3.1 and 24.5.4.1.1 */ static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl, uint32_t esdcfg) { uint32_t esdctlreg = ESDCTL0; uint32_t esdcfgreg = ESDCFG0; if (base == 0x90000000) { esdctlreg += 8; esdcfgreg += 8; } esdctl |= ESDCTL0_SDE; writel(esdcfg, esdcfgreg); writel(esdctl | ESDCTL0_SMODE_PRECHARGE, esdctlreg); writel(0, base + 1024); writel(esdctl | ESDCTL0_SMODE_AUTO_REFRESH, esdctlreg); readb(base); readb(base); writel(esdctl | ESDCTL0_SMODE_LOAD_MODE, esdctlreg); writeb(0, base + 0x33); writel(esdctl, esdctlreg); } void __bare_init __naked board_init_lowlevel(void) { uint32_t r; #ifdef CONFIG_NAND_IMX_BOOT unsigned int *trg, *src; #endif /* restart the MPLL and wait until it's stable */ writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27), IMX_CCM_BASE + CCM_CCTL); while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {}; /* Configure dividers and ARM clock source * ARM @ 400 MHz * AHB @ 133 MHz */ writel(0x20034000, IMX_CCM_BASE + CCM_CCTL); /* Set up 16bit NOR flash on WEIM CS0 */ writel(0xB8002000, 0x0000D003); writel(0xB8002004, 0x00330D01); writel(0xB8002008, 0x00220800); /* AIPS setup - Only setup MPROTx registers. The PACR default values are good. * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ writel(0x77777777, 0x43f00000); writel(0x77777777, 0x43f00004); writel(0x77777777, 0x53f00000); writel(0x77777777, 0x53f00004); /* MAX (Multi-Layer AHB Crossbar Switch) setup * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB */ writel(0x00043210, 0x43f04000); writel(0x00043210, 0x43f04100); writel(0x00043210, 0x43f04200); writel(0x00043210, 0x43f04300); writel(0x00043210, 0x43f04400); /* SGPCR - always park on last master */ writel(0x10, 0x43f04010); writel(0x10, 0x43f04110); writel(0x10, 0x43f04210); writel(0x10, 0x43f04310); writel(0x10, 0x43f04410); /* MGPCR - restore default values */ writel(0x0, 0x43f04800); writel(0x0, 0x43f04900); writel(0x0, 0x43f04a00); writel(0x0, 0x43f04b00); writel(0x0, 0x43f04c00); /* Configure M3IF registers * M3IF Control Register (M3IFCTL) for MX25 * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000 * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000 * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000 * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 * ---------- * 0x00000001 */ writel(0x1, 0xb8003000); /* enable all the clocks */ /* writel(0x1fffffff, IMX_CCM_BASE + CCM_CGCR0); writel(0xffffffff, IMX_CCM_BASE + CCM_CGCR1); writel(0x000fdfff, IMX_CCM_BASE + CCM_CGCR2); */ /* Set DDR2 and NFC group driver voltages */ writel(0x1000, IMX_IOMUXC_BASE + 0x454); writel(0x2000, IMX_IOMUXC_BASE + 0x448); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0x80000000 && r < 0x90000000) board_init_lowlevel_return(); writel(ESDMISC_RST, ESDMISC); while (!(readl(ESDMISC) & (1 << 31))); #define ESDCTLVAL (ESDCTL0_ROW13 | ESDCTL0_COL9 | ESDCTL0_DSIZ_15_0 | \ ESDCTL0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL) #define ESDCFGVAL (ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 | ESDCFGx_tRAS_6 | \ ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 | ESDCFGx_tRCD_3 | \ ESDCFGx_tRC_9) setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL); setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL); board_init_lowlevel_return(); } Why can't I printf() from low_level? I have also tried to what you did for your eukrea_cpuimx27.c: diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-reg index 73307c4..8225832 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -72,6 +72,7 @@ #define CCM_LTR1 0x44 #define CCM_LTR2 0x48 #define CCM_LTR3 0x4c +#define CCM_MCR 0x64 #define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) #define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) @@ -107,6 +108,22 @@ #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) +/* Chip Select Registers */ +#define IMX_WEIM_BASE WEIM_BASE +#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x Upper Register */ +#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x Lower Register */ +#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */ +#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */ + +#ifndef __ASSEMBLY__ +static inline void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional +{ + CSxU(cs) = upper; + CSxL(cs) = lower; + CSxA(cs) = addional; +} +#endif /* __ASSEMBLY__ */ + /* * Definitions for the clocksource driver * No matter what I do, it just does not work. Regards Roberto [-- Attachment #1.2: Type: text/html, Size: 14946 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-29 9:06 ` Roberto Nibali @ 2012-05-29 9:29 ` Sascha Hauer 2012-05-29 9:56 ` Roberto Nibali 0 siblings, 1 reply; 24+ messages in thread From: Sascha Hauer @ 2012-05-29 9:29 UTC (permalink / raw) To: Roberto Nibali; +Cc: barebox On Tue, May 29, 2012 at 11:06:00AM +0200, Roberto Nibali wrote: > Hi Eric > > > > > > http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c;h=63e87c9551c440edab572f5252a503ba4d533161;hb=c48de4beee21c3a5573cec084123c33ae08f6f7a > > > > > > > > > > > Now that piece certainly was missing, but how the heck did you find out > > > those register values? Where did you get the information about writing to > > > chip select 0 and selecting: > > > > > > CSCR0U: 0x00008F03 > > > CSCR0L: 0xA0330D01 > > > CSCR0A: 0x002208C0 > > > > > you need the reference manual of the i.MX25 to know the meaning of > > these registers and the datasheet of your flash to know it's timings > > then you can calculate the value to put in the registers. > > > > > I have found them in an old uboot tree a previous person patched to have > working support for NOR on boot. The values are: > > { .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, }, > { .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, }, > { .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, }, Do these values match the ones you read out of the registers using your U-Boot? > > /* Set up 16bit NOR flash on WEIM CS0 */ > writel(0xB8002000, 0x0000D003); > writel(0xB8002004, 0x00330D01); > writel(0xB8002008, 0x00220800); You mixed up the argument order. > > board_init_lowlevel_return(); > } > > Why can't I printf() from low_level? Because the console hasn't been setup yet. That's exactly the reason why I recommend doing only the absolutely necessary stuff in lowlevel_init. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-29 9:29 ` Sascha Hauer @ 2012-05-29 9:56 ` Roberto Nibali 2012-05-29 10:14 ` Roberto Nibali 0 siblings, 1 reply; 24+ messages in thread From: Roberto Nibali @ 2012-05-29 9:56 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 1695 bytes --] Hi Sascha > > you need the reference manual of the i.MX25 to know the meaning of > > > these registers and the datasheet of your flash to know it's timings > > > then you can calculate the value to put in the registers. > > > > > > > > I have found them in an old uboot tree a previous person patched to have > > working support for NOR on boot. The values are: > > > > { .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, }, > > { .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, }, > > { .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, }, > > Do these values match the ones you read out of the registers using your > U-Boot? > Yep, the corresponing dcdheader.S entries: DCDGEN( 1, 4, 0xB8002000, 0x0000D003) /* CS0_CSCRU */ DCDGEN( 2, 4, 0xB8002004, 0x00330d01) /* CS0_CSCRL */ DCDGEN( 3, 4, 0xB8002008, 0x00220800) /* CS0_CSCRA */ So I reckon at least I got this part working fine. > /* Set up 16bit NOR flash on WEIM CS0 */ > > writel(0xB8002000, 0x0000D003); > > writel(0xB8002004, 0x00330D01); > > writel(0xB8002008, 0x00220800); > > You mixed up the argument order. > > Yikes!!!! I hope I didn't fry something. I'll quickly try the reversed order and report back. > > > > board_init_lowlevel_return(); > > } > > > > Why can't I printf() from low_level? > > Because the console hasn't been setup yet. That's exactly the reason why > I recommend doing only the absolutely necessary stuff in lowlevel_init. > > Make perfect sense (*slapping forehead*). Thank you for your patience. I reckon those questions of mine could be compiled into some sort of FAQ for the newcomers into the barebox world to flatten the learning curve. Cheers Roberto [-- Attachment #1.2: Type: text/html, Size: 2634 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-29 9:56 ` Roberto Nibali @ 2012-05-29 10:14 ` Roberto Nibali 2012-05-30 5:47 ` Sascha Hauer 0 siblings, 1 reply; 24+ messages in thread From: Roberto Nibali @ 2012-05-29 10:14 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 42211 bytes --] ADDENDUM: > { .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, }, >> > { .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, }, >> > { .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, }, >> >> Do these values match the ones you read out of the registers using your >> U-Boot? >> > > Yep, the corresponing dcdheader.S entries: > > DCDGEN( 1, 4, 0xB8002000, 0x0000D003) /* CS0_CSCRU */ > DCDGEN( 2, 4, 0xB8002004, 0x00330d01) /* CS0_CSCRL */ > DCDGEN( 3, 4, 0xB8002008, 0x00220800) /* CS0_CSCRA */ > > So I reckon at least I got this part working fine. > > > /* Set up 16bit NOR flash on WEIM CS0 */ >> > writel(0xB8002000, 0x0000D003); >> > writel(0xB8002004, 0x00330D01); >> > writel(0xB8002008, 0x00220800); >> >> You mixed up the argument order. >> >> Yikes!!!! I hope I didn't fry something. I'll quickly try the reversed > order and report back. > It does not change the fact that it still does not recognize my NOR. I am at my wits' end here, so I go along posting my patch to support the mx25 based device for review: diff --git a/arch/arm/Makefile b/arch/arm/Makefile index d0bfd71..483b47e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -133,6 +133,7 @@ board-$(CONFIG_MACH_TX25) := karo-tx25 board-$(CONFIG_MACH_TQMA53) := tqma53 board-$(CONFIG_MACH_TX51) := karo-tx51 board-$(CONFIG_MACH_MX6Q_ARM2) := freescale-mx6-arm2 +board-$(CONFIG_MACH_MX25_NOAH) := fq-sid1-mx25-noah machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/boards/fq-sid1-mx25-noah/Makefile b/arch/arm/boards/fq-sid1-mx25-noah/Makefile new file mode 100644 index 0000000..1e9cd54 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/Makefile @@ -0,0 +1,26 @@ +# +# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +obj-y += lowlevel.o +obj-y += sid1_noah.o +obj-y += extra_commands.o +obj-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o diff --git a/arch/arm/boards/fq-sid1-mx25-noah/config.h b/arch/arm/boards/fq-sid1-mx25-noah/config.h new file mode 100644 index 0000000..f35e8a0 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/config.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Definitions related to passing arguments to kernel. + */ + +#define CONFIG_MX25_HCLK_FREQ 24000000 + +#endif + +/* nothing to do here yet */ diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/_update b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/_update new file mode 100644 index 0000000..014bce3 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/boot b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/boot new file mode 100644 index 0000000..d06fc16 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 != x ]; then + boot=$1 + kernel=$1 +fi + +if [ x$boot = xnor ]; then + bootargs="$bootargs root=$nor_rootpart rootfstype=jffs2" +elif [ x$boot = xmmc ]; then + bootargs="$bootargs root=$mmc_rootpart rootfstype=ext3" +elif [ x$boot = xnfs ]; then + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" + if [ x$getip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" + else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" + fi +fi + +# Generally add mtdparts to kernel cmdline +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts" + +if [ x$kernel = xtftp -o x$kernel = xnfs ]; then + if [ x$getip = xdhcp ]; then + echo "BOOT: Fetching IP address from $eth0.serverip" + dhcp + fi + tftp $tftp_uimage uImage || exit 1 + bootm uImage +elif [ x$kernel = xmmc ]; then + bootm $mmc_kernel +elif [ x$kernel = xnor ]; then + bootm /dev/nor0.kernel +fi + diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init new file mode 100644 index 0000000..070220d --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init @@ -0,0 +1,23 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nor [<imagename>] to update kernel into flash" + echo "type update_root nor [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_kernel b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_kernel new file mode 100644 index 0000000..49523aa --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_kernel @@ -0,0 +1,13 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_root b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_root new file mode 100644 index 0000000..0935bc1 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/config b/arch/arm/boards/fq-sid1-mx25-noah/env/config new file mode 100644 index 0000000..240056d --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/config @@ -0,0 +1,25 @@ +#!/bin/sh + +autoboot_timeout=5 + +# can be either 'nfs', 'tftp', 'nor', or 'mmc' +kernel=tftp +root=mmc + +version=/v2.1.8-rc +tftp_uimage=$version/uImage +tftp_jffs2=$version/console-image.jffs2 +bootargs="console=ttymxc0,115200" +nfsroot="/home/develop/SID1/nfsroot" +nor_parts="512k(barebox)ro,512k(bareboxenv),3072k(kernel),-(root)" +nor_rootpart="/dev/mtdblock3" +mmc_kernel="/dev/mmcblk0p1" +mmc_rootpart="/dev/mmcblk0p2" +getip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=192.168.1.80 +#eth0.netmask=255.255.255.0 +#eth0.gateway=a.b.c.d +eth0.serverip=192.168.1.23 +eth0.ethaddr=00:50:c2:8c:e6:0e diff --git a/arch/arm/boards/fq-sid1-mx25-noah/extra_commands.c b/arch/arm/boards/fq-sid1-mx25-noah/extra_commands.c new file mode 100644 index 0000000..e57c61f --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/extra_commands.c @@ -0,0 +1,66 @@ +/* + * (C) 2012 FQ Ingenieria, Roberto Nibali <rnibali@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <io.h> +#include <common.h> +#include <command.h> +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> + +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) + +static int do_cpufreq(int argc, char *argv[]) +{ + /* 15.3.3.1 Core PLL (MPLL) Control Register (MPCTL) */ + unsigned long freq; + + if (argc != 2) + return COMMAND_ERROR_USAGE; + + freq = simple_strtoul(argv[1], NULL, 0); + + switch (freq) { + case 399: + writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL); + break; + case 532: + writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); + break; + default: + return COMMAND_ERROR_USAGE; + } + + printf("Switched CPU frequency to %ldMHz\n", freq); + + return 0; +} + +static const __maybe_unused char cmd_cpufreq_help[] = +"Usage: cpufreq 399|532\n" +"\n" +"Set CPU frequency to <freq> MHz\n"; + +BAREBOX_CMD_START(cpufreq) + .cmd = do_cpufreq, + .usage = "adjust CPU frequency", + BAREBOX_CMD_HELP(cmd_cpufreq_help) +BAREBOX_CMD_END + diff --git a/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c b/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c new file mode 100644 index 0000000..982fc52 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c @@ -0,0 +1,88 @@ +#include <common.h> +#include <mach/imx-flash-header.h> +#include <mach/imx-regs.h> +#include <asm/barebox-arm-head.h> + +extern void exception_vectors(void); + +void __naked __flash_header_start go(void) +{ + barebox_arm_head(); +} + +/* + The Flash header is a data structure that the boot code reads from + Flash which provides information about the application. The Flash + header must be located at a known fixed address depending on the + type of external Flash device connected to i.MX25. The Flash header + is only required when an internal boot mode is selected from + BOOT_MODE[0:1]. The required offsets of the Flash header for each + device type are described in Table 7-10. + + NOR: 4 Kbyte = 0x1000 bytes + NAND: 1 Kbyte = 0x400 bytes + OneNAND: 256 bytes = 0x100 bytes + SD/eSD/MMC/eMMC: 1 kbyte = 0x400 bytes + I2C/CSPI EEPROM: 1 kbyte = 0x400 bytes + + The above flash header offsets are set accordingly in: + arch/arm/mach-imx/include/mach/imx-flash-header.h + + TEXT_BASE = 0x83F00000 + IMX_CS0_BASE = 0xA0000000 + #if INTERNAL_BOOT + DEST_BASE = IMX_CS0_BASE + #else + DEST_BASE = TEXT_BASE + #endif + FLASH_HEADER_BASE = (DEST_BASE + FLASH_HEADER_OFFSET) + */ + +struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { + /* NOR flash, CS0_CSCRU, CS0_CSCRL, CS0_CSCRA */ + { .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, }, + { .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, }, + { .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, }, + /* DDR2 init */ + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, }, /* initial value for ESDCFG0 */ + { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000204, }, /* ESD_MISC */ + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, /* CS0 precharge command */ + { .ptr_type = 4, .addr = 0x80000f00, .val = 0x12344321, }, /* precharge all dummy write */ + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, /* Load Mode Register command */ + { .ptr_type = 1, .addr = 0x82000000, .val = 0xda, }, /* dummy write Load EMR2 */ + { .ptr_type = 1, .addr = 0x83000000, .val = 0xda, }, /* dummy write Load EMR3 */ + { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, /* dummy write Load EMR1; enable DLL */ + { .ptr_type = 1, .addr = 0x80000333, .val = 0xda, }, /* dummy write Load MR; reset DLL */ + + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, /* CS0 precharge command */ + { .ptr_type = 4, .addr = 0x80000400, .val = 0x12345678, }, /* precharge all dummy write */ + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xA2210000, }, /* select manual refresh mode */ + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, /* manual refresh */ + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, /* manual refresh twice */ + + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, /* Load Mode Register command */ + { .ptr_type = 1, .addr = 0x80000233, .val = 0xda, }, /* Load MR; CL=3, BL=8, end DLL reset */ + { .ptr_type = 1, .addr = 0x81000780, .val = 0xda, }, /* Load EMR1; OCD default */ + { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, /* Load EMR1; OCD exit */ + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, /* normal mode */ + /* IOMUX_SW_PAD setup */ + { .ptr_type = 4, .addr = 0x43FAC454, .val = 0x00001000, }, /* IOMUXC_SW_PAD_CTL_GRP_DDRTYPE(1-5) */ + { .ptr_type = 4, .addr = 0x43FAC448, .val = 0x00002000, }, /* IOMUXC_SW_PAD NFC voltage 1.8 */ + + /* CLKCTL */ + { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, /* CLKCTL ARM=399 AHB=133 */ +}; + +struct imx_flash_header __flash_header_section flash_header = { + .app_code_jump_vector = DEST_BASE + ((unsigned int)&exception_vectors - TEXT_BASE), + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, /* non-secure boot (table 7-11) */ + .dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, /* non-secure boot (table 7-11) */ + .dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = DEST_BASE, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof(dcd_entry), +}; + +unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE; diff --git a/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c b/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c new file mode 100644 index 0000000..04ece36 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c @@ -0,0 +1,188 @@ +/* + * + * (c) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <init.h> +#include <mach/imx-regs.h> +#include <mach/esdctl.h> +#include <io.h> +#include <mach/imx-nand.h> +#include <asm/barebox-arm.h> +#include <asm/system.h> +#include <asm-generic/sections.h> +#include <asm-generic/memory_layout.h> + +#ifdef CONFIG_NAND_IMX_BOOT +static void __bare_init __naked insdram(void) +{ + uint32_t r; + + /* setup a stack to be able to call imx_nand_load_image() */ + r = STACK_BASE + STACK_SIZE - 12; + __asm__ __volatile__("mov sp, %0" : : "r"(r)); + + imx_nand_load_image((void *)TEXT_BASE, barebox_image_size); + + board_init_lowlevel_return(); +} +#endif + +/* Check 24.3.3.1 and 24.5.4.1.1 */ +static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl, + uint32_t esdcfg) +{ + uint32_t esdctlreg = ESDCTL0; + uint32_t esdcfgreg = ESDCFG0; + + if (base == 0x90000000) { + esdctlreg += 8; + esdcfgreg += 8; + } + + esdctl |= ESDCTL0_SDE; + + writel(esdcfg, esdcfgreg); + writel(esdctl | ESDCTL0_SMODE_PRECHARGE, esdctlreg); + writel(0, base + 1024); + writel(esdctl | ESDCTL0_SMODE_AUTO_REFRESH, esdctlreg); + readb(base); + readb(base); + writel(esdctl | ESDCTL0_SMODE_LOAD_MODE, esdctlreg); + writeb(0, base + 0x33); + writel(esdctl, esdctlreg); +} + +void __bare_init __naked board_init_lowlevel(void) +{ + uint32_t r; +#ifdef CONFIG_NAND_IMX_BOOT + unsigned int *trg, *src; +#endif + + /* restart the MPLL and wait until it's stable */ + writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27), + IMX_CCM_BASE + CCM_CCTL); + while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {}; + + /* Configure dividers and ARM clock source + * ARM @ 400 MHz + * AHB @ 133 MHz + */ + writel(0x20034000, IMX_CCM_BASE + CCM_CCTL); + + /* Set up 16bit NOR flash on WEIM CS0 */ + writel(0x0000D003, 0xB8002000); + writel(0x00330D01, 0xB8002004); + writel(0x00220800, 0xB8002008); + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good. + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, 0x43f00000); + writel(0x77777777, 0x43f00004); + writel(0x77777777, 0x53f00000); + writel(0x77777777, 0x53f00004); + + /* MAX (Multi-Layer AHB Crossbar Switch) setup + * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB + */ + writel(0x00043210, 0x43f04000); + writel(0x00043210, 0x43f04100); + writel(0x00043210, 0x43f04200); + writel(0x00043210, 0x43f04300); + writel(0x00043210, 0x43f04400); + /* SGPCR - always park on last master */ + writel(0x10, 0x43f04010); + writel(0x10, 0x43f04110); + writel(0x10, 0x43f04210); + writel(0x10, 0x43f04310); + writel(0x10, 0x43f04410); + /* MGPCR - restore default values */ + writel(0x0, 0x43f04800); + writel(0x0, 0x43f04900); + writel(0x0, 0x43f04a00); + writel(0x0, 0x43f04b00); + writel(0x0, 0x43f04c00); + + /* Configure M3IF registers + * M3IF Control Register (M3IFCTL) for MX25 + * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 + * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 + * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 + * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 + * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000 + * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000 + * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 + * ---------- + * 0x00000001 + */ + writel(0x1, 0xb8003000); + + /* enable all the clocks */ + writel(0x1fffffff, IMX_CCM_BASE + CCM_CGCR0); + writel(0xffffffff, IMX_CCM_BASE + CCM_CGCR1); + writel(0x000fdfff, IMX_CCM_BASE + CCM_CGCR2); + + /* Set DDR2 and NFC group driver voltages */ + writel(0x1000, IMX_IOMUXC_BASE + 0x454); + writel(0x2000, IMX_IOMUXC_BASE + 0x448); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0x80000000 && r < 0x90000000) + board_init_lowlevel_return(); + + writel(ESDMISC_RST, ESDMISC); + + while (!(readl(ESDMISC) & (1 << 31))); + +#define ESDCTLVAL (ESDCTL0_ROW13 | ESDCTL0_COL9 | ESDCTL0_DSIZ_15_0 | \ + ESDCTL0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL) +#define ESDCFGVAL (ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 | ESDCFGx_tRAS_6 | \ + ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 | ESDCFGx_tRCD_3 | \ + ESDCFGx_tRC_9) + + setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL); + setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL); + +#ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); + if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + board_init_lowlevel_return(); + + src = (unsigned int *)IMX_NFC_BASE; + trg = (unsigned int *)TEXT_BASE; + + /* Move ourselves out of NFC SRAM */ + for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ + r = (unsigned int)&insdram; + __asm__ __volatile__("mov pc, %0" : : "r"(r)); +#else + board_init_lowlevel_return(); +#endif +} diff --git a/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c new file mode 100644 index 0000000..239d72a --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c @@ -0,0 +1,377 @@ +/* + * (C) 2012 FQ Ingenieria, Roberto Nibali <rnibali@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <io.h> +#include <sizes.h> +#include <common.h> +#include <command.h> +#include <init.h> +#include <environment.h> +#include <partition.h> +#include <driver.h> +#include <fec.h> +#include <linux/err.h> +#include <i2c/i2c.h> +#include <generated/mach-types.h> +#include <asm/armlinux.h> +#include <asm/mmu.h> +#include <asm/barebox-arm-head.h> +#include <asm-generic/sections.h> +#include <mach/gpio.h> +#include <mach/iim.h> +#include <mach/usb.h> +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <mach/imx-flash-header.h> +#include <mach/iomux-mx25.h> +#include <mach/generic.h> +#include <mach/devices-imx25.h> + +/* The currently used MOSFET IRLMLL6402 needs + 3.3V driver voltage to function, however the + basic GPIO driver voltage is 1.8V, which is + not sufficient, unless the MOSFET switches + starting from VGS > 1.5V. + */ +#define MX25_PAD_CS1__GPIO_4_3_DVS IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL | PAD_CTL_DVS) + +static struct fec_platform_data fec_info = { + .xcv_type = RMII, + .phy_addr = 1, +}; + +#ifdef CONFIG_USB +static void imx25_usb_init(void) +{ + uint32_t reg; + + /* Host 1 */ + reg = readl(IMX_OTG_BASE + 0x600); + reg &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | + MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); + reg |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT; + reg |= MX35_H1_USBTE_BIT; + reg |= MX35_H1_IPPUE_DOWN_BIT; + writel(reg, IMX_OTG_BASE + 0x600); + + reg = readl(IMX_OTG_BASE + 0x584); + reg |= 3 << 30; + writel(reg, IMX_OTG_BASE + 0x584); + + /* Set to Host mode */ + reg = readl(IMX_OTG_BASE + 0x5a8); + writel(reg | 0x3, IMX_OTG_BASE + 0x5a8); +} +#endif + +/* +static struct at24_platform_data board_eeprom = { + .byte_len = 65536, + .page_size = 128, + .flags = AT24_FLAG_ADDR16, +}; +*/ + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("at24", 0x50), + //.platform_data = &board_eeprom, + }, +}; + +#if 0 +struct gpio_led noah_leds[] = { + { + .led = { .name = "GPIO-LED", }, + .gpio = IMX_GPIO_NR(4, 10), + .active_low = 1, + }, +}; + +static void noah_leds_init(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(noah_leds); i++) + led_gpio_register(&noah_leds[i]); +} +#endif + +#define MX25_NOAH_BOOT_UNKNOWN 0 +#define MX25_NOAH_BOOT_NOR 1 +#define MX25_NOAH_BOOT_MMC 2 +static int noah_read_ccm_regs(void) { + uint32_t reg; + + /* 15.3.3.12 CCM Reset and Debug Register (CRDR) + */ + reg = readl(IMX_CCM_BASE + CCM_CRDR); + printf("%s: CCM CRDR = %08X\n", __func__, reg); + + /* 15.3.3.11 CCM Status Register (RCSR) + if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14)) + nand_info.width = 2; + */ + reg = readl(IMX_CCM_BASE + CCM_RCSR); + printf("%s: CCM RCSR = %08X\n", __func__, reg); + if ((reg & (0x3 << 30)) == 0x3 << 30) { + printf("%s: Booting from expansion device: ", __func__); + if ((reg & (0x3 << 28)) == 0x0 << 28) { + printf("SD/MMC\n"); + return MX25_NOAH_BOOT_MMC; + } else { + printf("unknown\n"); + } + } else if ((reg & (0x3 << 30)) == 0x0 << 30) { + printf("%s: Booting from WEIM: ", __func__); + if ((reg & (0x3 << 28)) == 0x0 << 28) { + printf("NOR\n"); + return MX25_NOAH_BOOT_NOR; + } else { + printf("unknown\n"); + } + } + + return MX25_NOAH_BOOT_UNKNOWN; +} + +#ifdef CONFIG_DRIVER_VIDEO_IMX +static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "Chunghwa CLAA057VA01CT", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25600), + .left_margin = 46, + .right_margin = 114, + .upper_margin = 34, + .lower_margin = 11, + .hsync_len = 48, + .vsync_len = 3, + }, + .bpp = 16, + .pcr = 0xFA000080, /* 16bpp: Check 33.3.10 of the IMX25RM: LPCR */ +}; + +static struct imx_fb_platform_data noah_fb_data = { + .mode = &imxfb_mode, + .num_modes = 1, + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, +}; +#endif + +static iomux_v3_cfg_t imx25_pads[] = { + /* FEC RMII */ + MX25_PAD_FEC_MDC__FEC_MDC, /* Management data clock */ + MX25_PAD_FEC_MDIO__FEC_MDIO, /* Management data input/output */ + MX25_PAD_FEC_TX_EN__FEC_TX_EN, /* Transmit enable */ + MX25_PAD_FEC_RX_DV__FEC_RX_DV, /* Carrier sense / receive data valid */ + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, /* Synchronous clock reference (REF_CLK) */ + MX25_PAD_UART2_CTS__FEC_RX_ER, /* Receive error */ + MX25_PAD_FEC_RDATA0__FEC_RDATA0, /* Receive data */ + MX25_PAD_FEC_RDATA1__FEC_RDATA1, /* Receive data */ + MX25_PAD_FEC_TDATA0__FEC_TDATA0, /* Transmit data */ + MX25_PAD_FEC_TDATA1__FEC_TDATA1, /* Transmit data */ +#ifdef CONFIG_DRIVER_SERIAL_IMX + /* UART1 */ + MX25_PAD_UART1_RXD__UART1_RXD, + MX25_PAD_UART1_TXD__UART1_TXD, + MX25_PAD_UART1_RTS__UART1_RTS, + MX25_PAD_UART1_CTS__UART1_CTS, +#endif +#ifdef CONFIG_USB + /* USBH2 */ + MX25_PAD_D9__USBH2_PWR, + MX25_PAD_D8__USBH2_OC, + MX25_PAD_LD0__USBH2_CLK, + MX25_PAD_LD1__USBH2_DIR, + MX25_PAD_LD2__USBH2_STP, + MX25_PAD_LD3__USBH2_NXT, + MX25_PAD_LD4__USBH2_DATA0, + MX25_PAD_LD5__USBH2_DATA1, + MX25_PAD_LD6__USBH2_DATA2, + MX25_PAD_LD7__USBH2_DATA3, + MX25_PAD_HSYNC__USBH2_DATA4, + MX25_PAD_VSYNC__USBH2_DATA5, + MX25_PAD_LSCLK__USBH2_DATA6, + MX25_PAD_OE_ACD__USBH2_DATA7, +#endif + /* I2C1 */ + MX25_PAD_I2C1_CLK__I2C1_CLK, + MX25_PAD_I2C1_DAT__I2C1_DAT, + /* ESDHC */ + /* + MX25_PAD_SD1_CMD__SD1_CMD_NPU, + MX25_PAD_SD1_CLK__SD1_CLK_NPU, + MX25_PAD_SD1_DATA0__SD1_DATA0_NPU, + MX25_PAD_SD1_DATA1__SD1_DATA1_NPU, + MX25_PAD_SD1_DATA2__SD1_DATA2_NPU, + MX25_PAD_SD1_DATA3__SD1_DATA3_NPU, + */ +#ifdef CONFIG_DRIVER_VIDEO_IMX + /* LCD */ + MX25_PAD_LD0__LD0, /* TFT[19]: Blue[0] (LSB)*/ + MX25_PAD_LD1__LD1, /* TFT[18]: Blue[1] */ + MX25_PAD_LD2__LD2, /* TFT[17]: Blue[2] */ + MX25_PAD_LD3__LD3, /* TFT[15]: Blue[3] */ + MX25_PAD_LD4__LD4, /* TFT[14]: Blue[4] */ + MX25_PAD_LD5__LD5, /* TFT[13]: Blue[5] (MSB) */ + MX25_PAD_LD6__LD6, /* TFT[27]: Green[0] (LSB) */ + MX25_PAD_LD7__LD7, /* TFT[26]: Green[1] */ + MX25_PAD_LD8__LD8, /* TFT[25]: Green[2] */ + MX25_PAD_LD9__LD9, /* TFT[23]: Green[3] */ + MX25_PAD_LD10__LD10, /* TFT[22]: Green[4] */ + MX25_PAD_LD11__LD11, /* TFT[21]: Green[5] (MSB) */ + MX25_PAD_LD12__LD12, /* TFT[35]: Red[0] (LSB) */ + MX25_PAD_LD13__LD13, /* TFT[34]: Red[1] */ + MX25_PAD_LD14__LD14, /* TFT[33]: Red[2] */ + MX25_PAD_LD15__LD15, /* TFT[31]: Red[3] */ + MX25_PAD_GPIO_E__LD16, /* TFT[30]: Red[4] */ + MX25_PAD_GPIO_F__LD17, /* TFT[29]: Red[5] (MSB) */ + MX25_PAD_HSYNC__GPIO_1_22, /* TFT[ 3]: LCD_HSYNC */ + MX25_PAD_VSYNC__GPIO_1_23, /* TFT[ 8]: LCD_VSYNC */ + MX25_PAD_LSCLK__LSCLK, /* TFT[38]: LCD_LSCLK */ + MX25_PAD_OE_ACD__OE_ACD, /* TFT[ 9]: LCD_DRDY */ + MX25_PAD_CONTRAST__PWM4_PWMO, /* TFT[12]: LCD backlight (PWM): */ + MX25_PAD_CS1__GPIO_4_3_DVS, /* TFT[xx]: LCD_EN */ + MX25_PAD_EB1__GPIO_2_13, /* TFT[ 1]: LCD_UP_DOWN */ + MX25_PAD_BCLK__GPIO_4_4, /* TFT[40]: LCD_LEFT_RIGHT */ + MX25_PAD_CSI_D4__GPIO_1_29, /* TFT[ 2]: LCD_DMS */ +#endif +}; + +static int noah_fec_init(void) +{ + /* + * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. + * Assert FEC_RESET_B, then power up the PHY by asserting + * FEC_ENABLE, at the same time lifting FEC_RESET_B. + * + * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17 + * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12 + */ + writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */ + writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */ + +#define FEC_ENABLE_GPIO 35 +#define FEC_RESET_B_GPIO 104 + + /* make the pins output */ + gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */ + gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */ + udelay(2); + + /* turn on power & lift reset */ + gpio_set_value(FEC_ENABLE_GPIO, 1); + gpio_set_value(FEC_RESET_B_GPIO, 1); + + return 0; +} +late_initcall(noah_fec_init); + +static int imx25_mem_init(void) +{ + /* add memory bank to 0x80000000 (barebox_add_memory_bank()) */ + arm_add_mem_device("ram0", IMX_SDRAM_CS0, 64 * 1024 * 1024); + + return 0; +} +mem_initcall(imx25_mem_init); + +static int imx25_devices_init(void) +{ + int bootdev; + + bootdev = noah_read_ccm_regs(); + mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZE(imx25_pads)); + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + imx25_add_i2c0(NULL); + imx25_add_mmc0(NULL); + imx25_iim_register_fec_ethaddr(); + imx25_add_fec(&fec_info); + + printf("%s: Adding NOR flash device\n", __func__); + /* Configure 16 bit nor flash on WEIM cs0 */ + imx25_setup_weimcs(0, 0x0000D003, 0x00330D01, 0x00220800); + /* NOR flash starts at CS0 addr 0xA0000000, set to 64MB */ + add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, SZ_64M, 0); + printf("%s: Adding initial NOR flash partitions\n", __func__); + devfs_add_partition("nor0", 0x00000, SZ_512K, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", SZ_512K, SZ_512K, PARTITION_FIXED, "env0"); + //protect_file("/dev/env0", 1); +#ifdef CONFIG_USB + imx25_usb_init(); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); +#endif +#ifdef CONFIG_DRIVER_VIDEO_IMX + //imx25_add_fb(&noah_fb_data); +#endif + //noah_leds_init(); + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_MX25_3DS); + armlinux_set_serial(imx_uid()); + + return 0; +} +device_initcall(imx25_devices_init); + +static int imx25_console_init(void) +{ + //imx25_init_lowlevel(800) + imx25_core_setup(); + imx25_add_uart0(); + return 0; +} +console_initcall(imx25_console_init); + +/* Check arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c + for more information, especially with regard to low_level + setup inside the core_setup part. +*/ +static int imx25_core_setup(void) +{ + uint32_t reg; + /* Enable clocks: + UART1: 15 + FEC : 23 + SDHC1: 3/21 + USB : 28 + I2C : 6 + */ + reg = readl(IMX_CCM_BASE + CCM_CGCR0); + reg |= (1 << 6) | (1 << 23) | (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28); + reg = writel(reg, IMX_CCM_BASE + CCM_CGCR0); + + reg = readl(IMX_CCM_BASE + CCM_CGCR1); + reg |= (1 << 23) | (1 << 15) | (1 << 13); + reg = writel(reg, IMX_CCM_BASE + CCM_CGCR1); + + reg = readl(IMX_CCM_BASE + CCM_CGCR2); + reg |= (1 << 14); + reg = writel(reg, IMX_CCM_BASE + CCM_CGCR2); + /* CCM clocks: PER_12 -- PER_15 (15.3.3.10) */ + //writel(0x03010101, IMX_CCM_BASE + CCM_PCDR3); + /* CCM clocks: PER_8 -- PER_11 (15.3.3.9) */ + //writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2); + return 0; + +} +core_initcall(imx25_core_setup); diff --git a/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.dox b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.dox new file mode 100644 index 0000000..8b0e28a --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.dox @@ -0,0 +1,79 @@ +/** @page SID1 (FQ Ingeniería) + +This device is also known as "NOAH" (http://www.fqingenieria.es/) + +This CPU card is based on a Freescale i.MX25 CPU. The card is shipped with: + +- 64 MiB synchronous dynamic RAM (DDR type) +- 4 SIM/SAM sockets +- USB OTG +- ... + +Memory layout when @b barebox is running: + +- 0x80000000 start of SDRAM (IMX_SDRAM_CS0) +- 0x80000100 start of kernel's boot parameters + - below malloc area: stack area + - below barebox: malloc area +- 0x82000000 start of @b barebox + +@section get_sid1_noah_binary How to get the bootloader binary image: + +Using the default configuration: + +@verbatim +make ARCH=arm noah_defconfig +@endverbatim + +Build the bootloader binary image: + +@verbatim +make ARCH=arm CROSS_COMPILE=armv5compiler +@endverbatim + +@note replace the armv5compiler with your ARM v5 cross compiler. + +@section setup_falconwing How to prepare an MCI card to boot the "chumby one" with barebox + +- Create four primary partitions on the SD card + - the second one for the persistant environment (512 kiB, at least 256k) + - the third one for the kernel (3 MiB ... 4 MiB in size) + - the fourth one for the root filesystem which can fill the rest of the available space + +- Copy the default @b barebox environment into the second partition (no filesystem required). + +- Copy the kernel into the third partition (no filesystem required). + +- Create the root filesystem in the 4th partition. You may copy an image into this + partition or you can do it in the classic way: mkfs on it, mount it and copy + all required data and programs into it. + +@section gpio_falconwing Available GPIOs + +The SID1 NOAH uses some GPIOs to control various features. With the regular +GPIO commands these features can be controlled at @a barebox's runtime. + +<table width="100%" border="1" cellspacing="1" cellpadding="3"> + <tr> + <td>No</td> + <td>Direction</td> + <td>Function</td> + <td>Reset</td> + <td>Set</td> + </tr> + <tr> + <td>60</td> + <td>Output</td> + <td>Display Backlight</td> + <td>Backlight<br>Off</td> + <td>Backlight<br>On (100 %)</td> + </tr> + <tr> + <td>62</td> + <td>Input</td> + <td>Bend</td> + <td>Not pressed</td> + <td>Pressed</td> + </tr> +</table> +*/ diff --git a/arch/arm/configs/noah_defconfig b/arch/arm/configs/noah_defconfig new file mode 100644 index 0000000..152f0bf --- /dev/null +++ b/arch/arm/configs/noah_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX_EXTERNAL_BOOT=y +CONFIG_ARCH_IMX25=y +CONFIG_MACH_MX25_NOAH=y +CONFIG_IMX_CLKO=y +CONFIG_IMX_IIM=y +CONFIG_AEABI=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_BROKEN=y +CONFIG_EXPERIMENTAL=y +CONFIG_PROMPT="sid1-noah:" +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/fq-sid1-mx25-noah/env" +CONFIG_BAREBOXENV_TARGET=y +CONFIG_ENABLE_FLASH_NOISE=y +CONFIG_ENABLE_PARTITION_NOISE=y +CONFIG_ENABLE_DEVICE_NOISE=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_AUTOMOUNT=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_SAVES=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SHA256SUM=y +CONFIG_CMD_SHA224SUM=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_BMP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LED=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_TFTP=y +CONFIG_NET_TFTP_PUSH=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_DRIVER_SPI_IMX=y +CONFIG_I2C=y +CONFIG_I2C_IMX=y +CONFIG_DRIVER_CFI=y +# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set +# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set +CONFIG_MTD=y +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_USB_OHCI=y +CONFIG_USB_STORAGE=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_IMX=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_IMX_ESDHC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_EEPROM_AT25=y +CONFIG_FS_CRAMFS=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_BZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3236762..839de09 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -23,6 +23,7 @@ config ARCH_TEXT_BASE default 0x7ff00000 if MACH_MX53_SMD default 0x87f00000 if MACH_GUF_CUPID default 0x93d00000 if MACH_TX25 + default 0x83f00000 if MACH_MX25_NOAH default 0x7ff00000 if MACH_TQMA53 default 0x97f00000 if MACH_TX51 default 0x4fc00000 if MACH_MX6Q_ARM2 @@ -47,6 +48,7 @@ config BOARDINFO default "Freescale i.MX53 SMD" if MACH_FREESCALE_MX53_SMD default "Garz+Fricke Cupid" if MACH_GUF_CUPID default "Ka-Ro tx25" if MACH_TX25 + default "SID1 NOAH" if MACH_MX25_NOAH default "TQ tqma53" if MACH_TQMA53 default "Ka-Ro tx51" if MACH_TX51 default "Freescale i.MX6q armadillo2" if MACH_MX6Q_ARM2 @@ -251,6 +253,12 @@ config MACH_TX25 help Say Y here if you are using the Ka-Ro tx25 board +config MACH_MX25_NOAH + bool "SID1 NOAH" + select MACH_HAS_LOWLEVEL_INIT + help + Say Y here if you are using the SID1 NOAH board + endchoice endif diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h index 73307c4..8225832 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -72,6 +72,7 @@ #define CCM_LTR1 0x44 #define CCM_LTR2 0x48 #define CCM_LTR3 0x4c +#define CCM_MCR 0x64 #define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) #define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) @@ -107,6 +108,22 @@ #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) +/* Chip Select Registers */ +#define IMX_WEIM_BASE WEIM_BASE +#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x Upper Register */ +#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x Lower Register */ +#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */ +#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */ + +#ifndef __ASSEMBLY__ +static inline void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional) +{ + CSxU(cs) = upper; + CSxL(cs) = lower; + CSxA(cs) = addional; +} +#endif /* __ASSEMBLY__ */ + /* * Definitions for the clocksource driver * Thanks and best regards Roberto [-- Attachment #1.2: Type: text/html, Size: 87982 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-29 10:14 ` Roberto Nibali @ 2012-05-30 5:47 ` Sascha Hauer 2012-05-30 6:39 ` Juergen Beisert 2012-05-31 13:12 ` Roberto Nibali 0 siblings, 2 replies; 24+ messages in thread From: Sascha Hauer @ 2012-05-30 5:47 UTC (permalink / raw) To: Roberto Nibali; +Cc: barebox On Tue, May 29, 2012 at 12:14:52PM +0200, Roberto Nibali wrote: > ADDENDUM: > > > diff --git a/arch/arm/boards/fq-sid1-mx25-noah/Makefile > b/arch/arm/boards/fq-sid1-mx25-noah/Makefile > new file mode 100644 > index 0000000..1e9cd54 > --- /dev/null > +++ b/arch/arm/boards/fq-sid1-mx25-noah/Makefile > @@ -0,0 +1,26 @@ > +# > +# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> You should replace this with your own copyright. I think Jürgen can live with not having a copyright on trivial files ;) > diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/config Have you considered using one of the environment templates? You shouldn't duplicate them. > b/arch/arm/boards/fq-sid1-mx25-noah/env/config > new file mode 100644 > index 0000000..240056d > --- /dev/null > +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/config > @@ -0,0 +1,25 @@ > +#!/bin/sh > + > +autoboot_timeout=5 > + > +# can be either 'nfs', 'tftp', 'nor', or 'mmc' > +kernel=tftp > +root=mmc > + > +version=/v2.1.8-rc > +tftp_uimage=$version/uImage > +tftp_jffs2=$version/console-image.jffs2 > +bootargs="console=ttymxc0,115200" > +nfsroot="/home/develop/SID1/nfsroot" > +nor_parts="512k(barebox)ro,512k(bareboxenv),3072k(kernel),-(root)" > +nor_rootpart="/dev/mtdblock3" > +mmc_kernel="/dev/mmcblk0p1" > +mmc_rootpart="/dev/mmcblk0p2" > +getip=dhcp > + > +# or set your networking parameters here > +#eth0.ipaddr=192.168.1.80 > +#eth0.netmask=255.255.255.0 > +#eth0.gateway=a.b.c.d > +eth0.serverip=192.168.1.23 > +eth0.ethaddr=00:50:c2:8c:e6:0e *never* *ever* add MAC addresses to the default environment. > + > diff --git a/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c > b/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c > new file mode 100644 > index 0000000..982fc52 > --- /dev/null > +++ b/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c > @@ -0,0 +1,88 @@ > +#include <common.h> > +#include <mach/imx-flash-header.h> > +#include <mach/imx-regs.h> > +#include <asm/barebox-arm-head.h> > + > +extern void exception_vectors(void); > + > +void __naked __flash_header_start go(void) > +{ > + barebox_arm_head(); > +} > + > + DEST_BASE = IMX_CS0_BASE > + #else > + DEST_BASE = TEXT_BASE > + #endif > + FLASH_HEADER_BASE = (DEST_BASE + FLASH_HEADER_OFFSET) > + */ > + > +struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { > + /* NOR flash, CS0_CSCRU, CS0_CSCRL, CS0_CSCRA */ > + { .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, }, > + { .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, }, > + { .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, }, > + /* DDR2 init */ > + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, }, /* initial > value for ESDCFG0 */ Your mailer wraps lines. > +#endif > +#ifdef CONFIG_DRIVER_VIDEO_IMX > + //imx25_add_fb(&noah_fb_data); Please remove dead code before posting this for inclusion Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-30 5:47 ` Sascha Hauer @ 2012-05-30 6:39 ` Juergen Beisert 2012-05-31 13:12 ` Roberto Nibali 1 sibling, 0 replies; 24+ messages in thread From: Juergen Beisert @ 2012-05-30 6:39 UTC (permalink / raw) To: barebox Sascha Hauer wrote: > On Tue, May 29, 2012 at 12:14:52PM +0200, Roberto Nibali wrote: > > ADDENDUM: > > diff --git a/arch/arm/boards/fq-sid1-mx25-noah/Makefile > > b/arch/arm/boards/fq-sid1-mx25-noah/Makefile > > new file mode 100644 > > index 0000000..1e9cd54 > > --- /dev/null > > +++ b/arch/arm/boards/fq-sid1-mx25-noah/Makefile > > @@ -0,0 +1,26 @@ > > +# > > +# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> > > You should replace this with your own copyright. I think Jürgen can live > with not having a copyright on trivial files ;) Sure :) jbe -- Pengutronix e.K. | Juergen Beisert | Linux Solutions for Science and Industry | http://www.pengutronix.de/ | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-30 5:47 ` Sascha Hauer 2012-05-30 6:39 ` Juergen Beisert @ 2012-05-31 13:12 ` Roberto Nibali 2012-05-31 17:06 ` Sascha Hauer 1 sibling, 1 reply; 24+ messages in thread From: Roberto Nibali @ 2012-05-31 13:12 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 16094 bytes --] Hi > +# > > +# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> > > You should replace this with your own copyright. I think Jürgen can live > with not having a copyright on trivial files ;) > Ok, will do. > > diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/config > > Have you considered using one of the environment templates? You > shouldn't duplicate them. I haven't, I'll have look into them once I get NOR and SD card functionality inside barebox ... for which I have exactly one day left :). > > +# or set your networking parameters here > > +#eth0.ipaddr=192.168.1.80 > > +#eth0.netmask=255.255.255.0 > > +#eth0.gateway=a.b.c.d > > +eth0.serverip=192.168.1.23 > > +eth0.ethaddr=00:50:c2:8c:e6:0e > > *never* *ever* add MAC addresses to the default environment. Ok. In my case, the MAC address is actually stored inside a secured at24 EEPROM buffer. Unfortunately, at24 via I2C does not seem to be available in barebox. I reckon I have to port it from the kernel or uboot :). > > + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, }, /* initial > > value for ESDCFG0 */ > > Your mailer wraps lines. Yeah, sorry for that, gmail is all I have at the moment, however for serious inclusion or review of any patches, I'll definitely try to resort to ``git send-email'' > > +#endif > > +#ifdef CONFIG_DRIVER_VIDEO_IMX > > + //imx25_add_fb(&noah_fb_data); > > Please remove dead code before posting this for inclusion Will do, thanks. I have included some more debugging and also workarounds for the mx25. This is the current debug output, where it clearly indicates that for some reason the mx25 esdhc related registers never show a transfer complete for a multiblock write: Board: SID1 NOAH registered netconsole as cs1 noah_read_ccm_regs: CCM CRDR = 00000000 noah_read_ccm_regs: CCM RCSR = 01020820 noah_read_ccm_regs: Booting from WEIM: NOR imx-esdhc@mci0: registered as mci0 imx-esdhc@imx-esdhc0: set clock: wanted: 400000 got: 377840 imx-esdhc@imx-esdhc0: pre_div: 8 div: 10 imx-esdhc@imx-esdhc0: set clock: wanted: 200000 got: 188920 imx-esdhc@imx-esdhc0: pre_div: 16 div: 10 imx-esdhc@imx-esdhc0: set clock: wanted: 200000 got: 188920 imx-esdhc@imx-esdhc0: pre_div: 16 div: 10 mci@mci0: SD Card Rev. 2.00 or later detected mci@mci0: Put the Card in Identify Mode mci@mci0: Card's identification data is: 1B534D30-30303030-101ABB6A-9500AB00 mci@mci0: Get/Set relative address mci@mci0: Get card's specific data mci@mci0: Card's specific data is: 007FFF32-5B5A83BA-F6DBDFFF-0E800000 mci@mci0: Transfer speed: 25000000 mci@mci0: Max. block length are: Write=1024, Read=1024 Bytes mci@mci0: Capacity: 1910 MiB mci@mci0: Limiting max. read block size down to 512 mci@mci0: Limiting max. write block size down to 512 mci@mci0: Read block length: 512, Write block length: 512 mci@mci0: Select the card, and put it into Transfer Mode mci@mci0: Changing transfer frequency mci@mci0: Trying to read the SCR (try 1 of 3) esdhc_setup_data: Check if workaround ENGcm01112 is needed on i.MX25 (0x00000008) esdhc_setup_data: Enabling workaround for ENGcm01112 on i.MX25 esdhc_setup_data: Check if workaround ENGcm01112 is needed on i.MX25 (0x00000008) esdhc_setup_data: Enabling workaround for ENGcm01112 on i.MX25 esdhc_setup_data: Check if workaround ENGcm01112 is needed on i.MX25 (0x00000040) esdhc_setup_data: Enabling workaround for ENGcm01112 on i.MX25 mci@mci0: Prepare for bus width change mci@mci0: Set SD bus width to 4 bit imx-esdhc@imx-esdhc0: set clock: wanted: 200000 got: 188920 imx-esdhc@imx-esdhc0: pre_div: 16 div: 10 imx-esdhc@imx-esdhc0: set clock: wanted: 50000000 got: 33250000 imx-esdhc@imx-esdhc0: pre_div: 0 div: 1 mci@mci0: Card is up and running now, registering as a disk mci@mci0: registered disk0 mci@mci0: mci_sd_read: Read 1 block(s), starting at 0 mci@mci0: READ: Activating single block transfer esdhc_setup_data: Check if workaround ENGcm01112 is needed on i.MX25 (0x00000040) esdhc_setup_data: Enabling workaround for ENGcm01112 on i.MX25 mci@mci0: SD Card successfully added imx25_devices_init: Adding NOR flash device cfi_flash@cfi_flash0: cfi flash (id=01000000 vend=000002 manu=000001 devid=00007E extid=002301) at a0000000, size 64MB imx25_devices_init: Adding initial NOR flash partitions ehci@ehci0: USB EHCI 1.00 Malloc space: 0x83b00000 -> 0x83efffff (size 4 MB) Stack space : 0x83af8000 -> 0x83b00000 (size 32 kB) envfs: wrong magic on /dev/env0 no valid environment found on /dev/env0. Using default environment running /env/bin/init... Hit any key to stop autoboot: 4 type update_kernel nor [<imagename>] to update kernel into flash type update_root nor [<imagename>] to update rootfs into flash sid1-noah:/ mkdir /mnt sid1-noah:/ mount /dev/disk0.0 fat /mnt mci@mci0: mci_sd_read: Read 128 block(s), starting at 2048 mci@mci0: READ: Activating multiple block transfer block_cache: blk->ops->read returned 0 sid1-noah:/ cp /mnt/conmci@mci0: mci_sd_read: Read 128 block(s), starting at 2560 mci@mci0: READ: Activating multiple block transfer block_cache: blk->ops->read returned 0 sole_image.jffs2 /mnt/console_image.jffs2-backup mci@mci0: mci_sd_read: Read 128 block(s), starting at 3584 mci@mci0: READ: Activating multiple block transfer block_cache: blk->ops->read returned 0 mci@mci0: mci_sd_read: Read 128 block(s), starting at 2304 mci@mci0: READ: Activating multiple block transfer block_cache: blk->ops->read returned 0 mci@mci0: mci_sd_read: Read 128 block(s), starting at 53760 mci@mci0: READ: Activating multiple block transfer block_cache: blk->ops->read returned 0 mci@mci0: mci_sd_read: Read 128 block(s), starting at 3712 mci@mci0: READ: Activating multiple block transfer block_cache: blk->ops->read returned 0 mci@mci0: mci_sd_read: Read 128 block(s), starting at 53888 mci@mci0: READ: Activating multiple block transfer block_cache: blk->ops->read returned 0 mci@mci0: mci_sd_read: Read 128 block(s), starting at 3840 mci@mci0: READ: Activating multiple block transfer block_cache: blk->ops->read returned 0 mci@mci0: mci_sd_write: Write 128 block(s), starting at 2560 mci@mci0: WRITE: Activating multiple block transfer Data Write Failed in PIO Mode.imx-esdhc@imx-esdhc0: timeout 2 esdhc_send_cmd: busy loop 1 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 mci@mci0: Writing block 2560 failed with -110 mci@mci0: mci_sd_read: Read 128 block(s), starting at 54016 mci@mci0: READ: Activating multiple block transfer esdhc_send_cmd: busy loop 1 CMD=0x01a60000 (0x00000012) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x01a60000 (0x00000012) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x01a60000 (0x00000012) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 esdhc_send_cmd: busy loop 1 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 mci@mci0: Reading block 54016 failed with -110 block_cache: blk->ops->read returned -110 write: I/O error mci@mci0: mci_sd_write: Write 128 block(s), starting at 2048 mci@mci0: WRITE: Activating multiple block transfer esdhc_send_cmd: busy loop 1 CMD=0x00100000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x00100000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x00100000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 esdhc_send_cmd: busy loop 1 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 mci@mci0: Writing block 2048 failed with -110 mci@mci0: mci_sd_write: Write 128 block(s), starting at 2304 mci@mci0: WRITE: Activating multiple block transfer esdhc_send_cmd: busy loop 1 CMD=0x00120000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x00120000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x00120000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 esdhc_send_cmd: busy loop 1 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 mci@mci0: Writing block 2304 failed with -110 mci@mci0: mci_sd_write: Write 128 block(s), starting at 53888 mci@mci0: WRITE: Activating multiple block transfer esdhc_send_cmd: busy loop 1 CMD=0x01a50000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x01a50000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x01a50000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 esdhc_send_cmd: busy loop 1 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 mci@mci0: Writing block 53888 failed with -110 mci@mci0: mci_sd_write: Write 128 block(s), starting at 53760 mci@mci0: WRITE: Activating multiple block transfer esdhc_send_cmd: busy loop 1 CMD=0x01a40000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x01a40000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x01a40000 (0x00000019) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 esdhc_send_cmd: busy loop 1 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 mci@mci0: Writing block 53760 failed with -110 mci@mci0: mci_sd_read: Read 128 block(s), starting at 2560 mci@mci0: READ: Activating multiple block transfer esdhc_send_cmd: busy loop 1 CMD=0x00140000 (0x00000012) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x00140000 (0x00000012) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x00140000 (0x00000012) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 esdhc_send_cmd: busy loop 1 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 2 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 esdhc_send_cmd: busy loop 3 CMD=0x00000000 (0x0000000c) cap=0x07f30000 irqstat=0x00000000 proctl=0x00000022 prsstat=0xf7880587 xfertyp=0x0c3b0022 sysctl=0x000e0017 blkattr=0x00700200 imx-esdhc@imx-esdhc0: timeout 1 mci@mci0: Reading block 2560 failed with -110 block_cache: blk->ops->read returned -110 I'll start looking at the uboot drivers, since the kernel drivers are quite messy with regard to the software stack a SD cmd has to travel. In any case, you before dropping a new barebox release, you might want to consider this cosmetic change: diff --git a/drivers/mci/imx-esdhc.h b/drivers/mci/imx-esdhc.h index 19fed5a..d9be69e 100644 --- a/drivers/mci/imx-esdhc.h +++ b/drivers/mci/imx-esdhc.h @@ -39,7 +39,6 @@ #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 -#define SYSCTL_RSTA 0x01000000 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) Best regards Roberto [-- Attachment #1.2: Type: text/html, Size: 20016 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-31 13:12 ` Roberto Nibali @ 2012-05-31 17:06 ` Sascha Hauer 2012-06-01 10:25 ` Roberto Nibali 0 siblings, 1 reply; 24+ messages in thread From: Sascha Hauer @ 2012-05-31 17:06 UTC (permalink / raw) To: Roberto Nibali; +Cc: barebox On Thu, May 31, 2012 at 03:12:08PM +0200, Roberto Nibali wrote: > Hi > > > > > > +# or set your networking parameters here > > > +#eth0.ipaddr=192.168.1.80 > > > +#eth0.netmask=255.255.255.0 > > > +#eth0.gateway=a.b.c.d > > > +eth0.serverip=192.168.1.23 > > > +eth0.ethaddr=00:50:c2:8c:e6:0e > > > > *never* *ever* add MAC addresses to the default environment. > > > Ok. In my case, the MAC address is actually stored inside a secured at24 > EEPROM buffer. Unfortunately, at24 via I2C does not seem to be available in > barebox. I reckon I have to port it from the kernel or uboot :). Or just leave the field blank. In this case a random (local-) MAC address is generated. > > I have included some more debugging and also workarounds for the mx25. This > is the current debug output, where it clearly indicates that for some > reason the mx25 esdhc related registers never show a transfer complete for > a multiblock write: The kernel has this: if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK | SDHCI_QUIRK_BROKEN_ADMA; Which means that the kernel won't do multiblock on i.MX25 and i.MX35. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-31 17:06 ` Sascha Hauer @ 2012-06-01 10:25 ` Roberto Nibali 2012-06-05 7:09 ` Sascha Hauer 0 siblings, 1 reply; 24+ messages in thread From: Roberto Nibali @ 2012-06-01 10:25 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 4394 bytes --] G'day > > > +# or set your networking parameters here > > > > +#eth0.ipaddr=192.168.1.80 > > > > +#eth0.netmask=255.255.255.0 > > > > +#eth0.gateway=a.b.c.d > > > > +eth0.serverip=192.168.1.23 > > > > +eth0.ethaddr=00:50:c2:8c:e6:0e > > > > > > *never* *ever* add MAC addresses to the default environment. > > > > > > Ok. In my case, the MAC address is actually stored inside a secured at24 > > EEPROM buffer. Unfortunately, at24 via I2C does not seem to be available > in > > barebox. I reckon I have to port it from the kernel or uboot :). > > Or just leave the field blank. In this case a random (local-) MAC > address is generated. Oh, I didn't know that, brilliant. > I have included some more debugging and also workarounds for the mx25. > This > > is the current debug output, where it clearly indicates that for some > > reason the mx25 esdhc related registers never show a transfer complete > for > > a multiblock write: > > The kernel has this: > > if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) > /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ > host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK > | SDHCI_QUIRK_BROKEN_ADMA; > :) Yes, the kernel has lots of quirks for the mx25 based esdhc implementation, and I have stumbled across these lines a dozen times already over the past few weeks trying to figure out why SD write transfer is doooooog slow on my device. I have been sending a lot of in-depth analysis and traces, including timing charts showing completely impossible CMD timeouts, and no one seems to be able to figure out what causes this. Hardware failure is almost not possible, and that's why I focused on the Software part. Since the eSDHC stack in the kernel is composed of a lot of intermediary drivers down to block layer, I opted for the simplest possible test case where I didn't have to write an SD driver from scratch: barebox! That's how we ended up here. I am well aware that for others this problem does not seem to exist, but I simply don't know where to look for anymore. With regard to ENGcm07207, IMHO the introduced quirk does not really fix this specific erratum. The problem description in the READ case is as follows: "If a CMD12 command is sent during a WRITE MULTIPLE BLOCK transfer, the AHB bus keeps writing to the internal buffers. This is undesirable behavior. During this situation, the AHB bus does not stop until all the blocks are written to the internal buffer, and an AutoCMD12 command is sent. A typical scenario is as follows: After Sending a non-ending block, the card replies with a CRC error. The software detects the CRC error and manually sends a CMD12 command to the card to stop the transmission. Internally, the AHB bus keeps writing to the internal buffer even though the software stopped the transfer." So the solution is as follows: To abort data transfers on the AHB, software can reset the eSDHC by writing 1 to SYSCTL[24] (RSTA). I haven't tried this, but I can assure you that setting block count to 1 does not resolve the issue at all, or the other way around: having multiple block write/read support for the i.MX25 does not seem to be the cause of any reproducible problem. So, unless someone proves me otherwise, I believe the kernel driver implementation is wrong. On top of that, there is erratum ENGcm01112 which then directly comes into action, something I also didn't see addressed in the kernel sources. I'll keep looking for other answers, however you might want to consider the minimally invasive WML changes I did in the patch sent before, which at the same time introduce a similar quirk "framework" to the esdhc driver in barebox like the kernel has. I will also compare to the uboot driver. I understand that there is very little concern for this in the barebox driver, since most of what the users need is to copy from the SD card, and so far nobody has complained. I happily stand corrected ;). Best regards Roberto > Which means that the kernel won't do multiblock on i.MX25 and i.MX35. > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > [-- Attachment #1.2: Type: text/html, Size: 5669 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-06-01 10:25 ` Roberto Nibali @ 2012-06-05 7:09 ` Sascha Hauer 0 siblings, 0 replies; 24+ messages in thread From: Sascha Hauer @ 2012-06-05 7:09 UTC (permalink / raw) To: Roberto Nibali; +Cc: barebox On Fri, Jun 01, 2012 at 12:25:04PM +0200, Roberto Nibali wrote: > > I have included some more debugging and also workarounds for the mx25. > > This > > > is the current debug output, where it clearly indicates that for some > > > reason the mx25 esdhc related registers never show a transfer complete > > for > > > a multiblock write: > > > > The kernel has this: > > > > if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) > > /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ > > host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK > > | SDHCI_QUIRK_BROKEN_ADMA; > > > > :) Yes, the kernel has lots of quirks for the mx25 based esdhc > implementation, and I have stumbled across these lines a dozen times > already over the past few weeks trying to figure out why SD write transfer > is doooooog slow on my device. I have been sending a lot of in-depth > analysis and traces, including timing charts showing completely impossible > CMD timeouts, and no one seems to be able to figure out what causes this. > Hardware failure is almost not possible, and that's why I focused on the > Software part. Since the eSDHC stack in the kernel is composed of a lot of > intermediary drivers down to block layer, I opted for the simplest possible > test case where I didn't have to write an SD driver from scratch: barebox! > > That's how we ended up here. I am well aware that for others this problem > does not seem to exist, but I simply don't know where to look for anymore. > With regard to ENGcm07207, IMHO the introduced quirk does not really fix > this specific erratum. The problem description in the READ case is as > follows: > > "If a CMD12 command is sent during a WRITE MULTIPLE BLOCK transfer, the AHB > bus keeps writing to the internal buffers. This is undesirable behavior. > During this situation, the AHB bus does not stop until all the blocks are > written to the internal buffer, and an AutoCMD12 command is sent. > > A typical scenario is as follows: After Sending a non-ending block, the > card replies with a CRC error. The software detects the CRC error and > manually sends a CMD12 command to the card to stop the transmission. > Internally, the AHB bus keeps writing to the internal buffer even though > the software stopped the transfer." > > So the solution is as follows: > > To abort data transfers on the AHB, software can reset the eSDHC by writing > 1 to SYSCTL[24] (RSTA). > > I haven't tried this, but I can assure you that setting block count to 1 > does not resolve the issue at all, or the other way around: having multiple > block write/read support for the i.MX25 does not seem to be the cause of > any reproducible problem. So, unless someone proves me otherwise, I believe > the kernel driver implementation is wrong. On top of that, there is > erratum ENGcm01112 which then directly comes into action, something I also > didn't see addressed in the kernel sources. I don't know much about this topic. If you find something, please let us know, also if you find something that helps the kernel. > > I'll keep looking for other answers, however you might want to consider the > minimally invasive WML changes I did in the patch sent before, which at the > same time introduce a similar quirk "framework" to the esdhc driver in > barebox like the kernel has. Can you send this patch again? The thread has gotten quite long and I can't find this anymore. Please start a new thread next time for different topics. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-24 13:18 ` Roberto Nibali 2012-05-24 13:31 ` Eric Bénard @ 2012-05-24 17:17 ` Sascha Hauer 2012-05-25 9:19 ` Roberto Nibali 1 sibling, 1 reply; 24+ messages in thread From: Sascha Hauer @ 2012-05-24 17:17 UTC (permalink / raw) To: Roberto Nibali; +Cc: barebox On Thu, May 24, 2012 at 03:18:13PM +0200, Roberto Nibali wrote: > Hi Eric > > On Thu, May 24, 2012 at 2:58 PM, Eric Bénard <eric@eukrea.com> wrote: > > > > I support WEIM configuration is done in the low level part, isn't it? You don't need to do it in lowlevel init, just before registering the cfi device is enough. Usually it's good habit to do only the absolutely necessary things in lowlevel init. Doing things later increases the chance that you get useful debug output when something goes wrong Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-24 17:17 ` Sascha Hauer @ 2012-05-25 9:19 ` Roberto Nibali 2012-05-25 10:01 ` Sascha Hauer 0 siblings, 1 reply; 24+ messages in thread From: Roberto Nibali @ 2012-05-25 9:19 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 1323 bytes --] Hi On Thu, May 24, 2012 at 7:17 PM, Sascha Hauer <s.hauer@pengutronix.de>wrote: > On Thu, May 24, 2012 at 03:18:13PM +0200, Roberto Nibali wrote: > > Hi Eric > > > > On Thu, May 24, 2012 at 2:58 PM, Eric Bénard <eric@eukrea.com> wrote: > > > > > > > > I support WEIM configuration is done in the low level part, isn't it? > > You don't need to do it in lowlevel init, just before registering the > cfi device is enough. Usually it's good habit to do only the absolutely > necessary things in lowlevel init. Doing things later increases the > chance that you get useful debug output when something goes wrong > > I read the different board initialization routines over and over again, but can't find a common pattern. From what I see the lowlevel_init (which has been converted nicely into a C file), only AIPS, MAX, MPLL core clock, all clocks, SDRAM are initialized, but I have seen AIPS and MAX setups in core_init functions (eukrea_cpuimx35.c), as well as clock setups in console_init and other places. So, what's the bare minimum in lowlevel to set up? SDRAM/MDDR? What's the order of things? I am merely asking because I have come a long way trying to debug an issue with weird I/O and clock behaviour on the ESDHC and other parts of my mx25 device. Thanks and best regards Roberto [-- Attachment #1.2: Type: text/html, Size: 1838 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-25 9:19 ` Roberto Nibali @ 2012-05-25 10:01 ` Sascha Hauer 2012-05-29 9:26 ` Roberto Nibali 0 siblings, 1 reply; 24+ messages in thread From: Sascha Hauer @ 2012-05-25 10:01 UTC (permalink / raw) To: Roberto Nibali; +Cc: barebox On Fri, May 25, 2012 at 11:19:38AM +0200, Roberto Nibali wrote: > Hi > > On Thu, May 24, 2012 at 7:17 PM, Sascha Hauer <s.hauer@pengutronix.de>wrote: > > > On Thu, May 24, 2012 at 03:18:13PM +0200, Roberto Nibali wrote: > > > Hi Eric > > > > > > On Thu, May 24, 2012 at 2:58 PM, Eric Bénard <eric@eukrea.com> wrote: > > > > > > > > > > > > I support WEIM configuration is done in the low level part, isn't it? > > > > You don't need to do it in lowlevel init, just before registering the > > cfi device is enough. Usually it's good habit to do only the absolutely > > necessary things in lowlevel init. Doing things later increases the > > chance that you get useful debug output when something goes wrong > > > > I read the different board initialization routines over and over again, > but can't find a common pattern. From what I see the lowlevel_init (which > has been converted nicely into a C file), only AIPS, MAX, MPLL core clock, > all clocks, SDRAM are initialized, but I have seen AIPS and MAX setups in > core_init functions (eukrea_cpuimx35.c), as well as clock setups in > console_init and other places. So, what's the bare minimum in lowlevel to > set up? SDRAM/MDDR? What's the order of things? > > I am merely asking because I have come a long way trying to debug an issue > with weird I/O and clock behaviour on the ESDHC and other parts of my mx25 > device. - MAX setup is not needed for barebox - AIPS can most probably be done later aswell - I'm unsure with the MPLL, that depends on whether the SDRAM clock depends on it. You should only setup all dependencies for SDRAM and the SDRAM itself. Everything else can be done later. What that is for the i.MX25 you can see in the dcd, here from the Eukrea mx25: struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, }, { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, }, { .ptr_type = 1, .addr = 0x80000400, .val = 0x12344321, }, { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, }, { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, }, { .ptr_type = 1, .addr = 0x80000033, .val = 0xda, }, { .ptr_type = 1, .addr = 0x81000000, .val = 0xff, }, { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, { .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, }, { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, }; So basically this means that the SDRAM does not seem to have any dependencies. All the things in lowlevel_init are then done when running from SDRAM anyway (at least when doing a dcd based boot), so they can safely be done later. The next thing is that the clocks are correctly initialized before the corresponding devices are registered. So let's analyze Eukreas lowlevel init: > void __bare_init __naked board_init_lowlevel(void) > { > uint32_t r; > #ifdef CONFIG_NAND_IMX_BOOT > unsigned int *trg, *src; > int i; > #endif > register uint32_t loops = 0x20000; > > /* restart the MPLL and wait until it's stable */ > writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27), > IMX_CCM_BASE + CCM_CCTL); > while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {}; > > /* Configure dividers and ARM clock source > * ARM @ 400 MHz > * AHB @ 133 MHz > */ > writel(0x20034000, IMX_CCM_BASE + CCM_CCTL); This may influence the timer clock, so it can be here. > > /* Enable UART1 / FEC / */ > /* writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0); > writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1); > writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2);*/ This brings the Clock gate registers to reset default. This may be a good idea, but can be done later. > > /* AIPS setup - Only setup MPROTx registers. The PACR default values are good. > * Set all MPROTx to be non-bufferable, trusted for R/W, > * not forced to user-mode. > */ > writel(0x77777777, 0x43f00000); > writel(0x77777777, 0x43f00004); > writel(0x77777777, 0x53f00000); > writel(0x77777777, 0x53f00004); This can be done later. This is duplicated in many boards and is always the same. Look for example at the i.MX53 code, there we have imx53_init_lowlevel() which sets up the AIPS. This is common for all i.MX53 and is called from an initcall. Similar could be done for i.MX25 aswell, if somebody is willing to implement it. > > /* MAX (Multi-Layer AHB Crossbar Switch) setup > * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB > */ > writel(0x00002143, 0x43f04000); > writel(0x00002143, 0x43f04100); > writel(0x00002143, 0x43f04200); > writel(0x00002143, 0x43f04300); > writel(0x00002143, 0x43f04400); > /* SGPCR - always park on last master */ > writel(0x10, 0x43f04010); > writel(0x10, 0x43f04110); > writel(0x10, 0x43f04210); > writel(0x10, 0x43f04310); > writel(0x10, 0x43f04410); > /* MGPCR - restore default values */ > writel(0x0, 0x43f04800); > writel(0x0, 0x43f04900); > writel(0x0, 0x43f04a00); > writel(0x0, 0x43f04b00); > writel(0x0, 0x43f04c00); > > /* Configure M3IF registers > * M3IF Control Register (M3IFCTL) for MX25 > * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 > * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 > * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 > * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000 > * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 > * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000 > * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000 > * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 > * ---------- > * 0x00000001 > */ > writel(0x1, 0xb8003000); Same as above. > > /* Speed up NAND controller by adjusting the NFC divider */ > r = readl(IMX_CCM_BASE + CCM_PCDR2); > r &= ~0xf; > r |= 0x1; > writel(r, IMX_CCM_BASE + CCM_PCDR2); This is necessary for external NAND boot. The NAND controller comes up with a low speed which makes the copying of the image (CONFIG_NAND_IMX_BOOT below) slow. This is optional but has to be done here to get a faster boot. > > /* Skip SDRAM initialization if we run from RAM */ > r = get_pc(); > if (r > 0x80000000 && r < 0x90000000) > board_init_lowlevel_return(); Here we bail out for second stage boots (and also internal bootmode where we are already running from SDRAM > > /* Init Mobile DDR */ > writel(0x0000000E, ESDMISC); > writel(0x00000004, ESDMISC); > __asm__ volatile ("1:\n" > "subs %0, %1, #1\n" > "bne 1b":"=r" (loops):"0" (loops)); > > writel(0x0029572B, ESDCFG0); > writel(0x92210000, ESDCTL0); > writeb(0xda, IMX_SDRAM_CS0 + 0x400); > writel(0xA2210000, ESDCTL0); > writeb(0xda, IMX_SDRAM_CS0); > writeb(0xda, IMX_SDRAM_CS0); > writel(0xB2210000, ESDCTL0); > writeb(0xda, IMX_SDRAM_CS0 + 0x33); > writeb(0xda, IMX_SDRAM_CS0 + 0x1000000); > writel(0x82216080, ESDCTL0); RAM init for external bootmode, has to be done here. > > #ifdef CONFIG_NAND_IMX_BOOT > /* skip NAND boot if not running from NFC space */ > r = get_pc(); > if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) > board_init_lowlevel_return(); > > src = (unsigned int *)IMX_NFC_BASE; > trg = (unsigned int *)TEXT_BASE; > > /* Move ourselves out of NFC SRAM */ > for (i = 0; i < 0x800 / sizeof(int); i++) > *trg++ = *src++; > > /* Jump to SDRAM */ > r = (unsigned int)&insdram; > __asm__ __volatile__("mov pc, %0" : : "r"(r)); > #else > board_init_lowlevel_return(); > #endif Finally copy the image from NAND SRAM to SDRAM, only needed for external NAND boot. Often the whole lowlevel stuff is setup in early assembly code. This has mostly historical reasons and 'hey, this is hardcore stuff we configure here, we must do it early and we must do it in assembly'. Much of the lowlevel stuff we have in barebox is just copied from a working U-Boot or redboot setup and never touched again, hence the slightly chaotic situation. Hope I could help you a bit. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: Booting mx25 based device from SD and NOR 2012-05-25 10:01 ` Sascha Hauer @ 2012-05-29 9:26 ` Roberto Nibali 0 siblings, 0 replies; 24+ messages in thread From: Roberto Nibali @ 2012-05-29 9:26 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox [-- Attachment #1.1: Type: text/plain, Size: 22249 bytes --] Hi Sascha Thank you so much for taking your time explaining things the way you did. It certainly cleared things up a lot, albeit it still does not work; comment below. > > I read the different board initialization routines over and over again, > > but can't find a common pattern. From what I see the lowlevel_init (which > > has been converted nicely into a C file), only AIPS, MAX, MPLL core > clock, > > all clocks, SDRAM are initialized, but I have seen AIPS and MAX setups in > > core_init functions (eukrea_cpuimx35.c), as well as clock setups in > > console_init and other places. So, what's the bare minimum in lowlevel to > > set up? SDRAM/MDDR? What's the order of things? > > > > I am merely asking because I have come a long way trying to debug an > issue > > with weird I/O and clock behaviour on the ESDHC and other parts of my > mx25 > > device. > > - MAX setup is not needed for barebox > - AIPS can most probably be done later aswell > - I'm unsure with the MPLL, that depends on whether the SDRAM clock > depends on it. > In my case I am fairly certain that SDRAM clock does not depend on MPLL. I will be moving MAX and AIPS setup out of lowlevel init, so as to keep it tiny. > You should only setup all dependencies for SDRAM and the SDRAM itself. > Everything else can be done later. What that is for the i.MX25 you > can see in the dcd, here from the Eukrea mx25: > > struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { > { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, }, > { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, }, > { .ptr_type = 1, .addr = 0x80000400, .val = 0x12344321, }, > { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, }, > { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, > { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, > { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, }, > { .ptr_type = 1, .addr = 0x80000033, .val = 0xda, }, > { .ptr_type = 1, .addr = 0x81000000, .val = 0xff, }, > { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, > { .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, }, > { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, > }; > > So basically this means that the SDRAM does not seem to have any > dependencies. > This is the first time I have realized that the DCD actually represents more or less what should be done in the lowlevel init. After carefully reading what you explained and cross-checking with the old uboot, I have come up with the following DCD: struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { /* NOR flash, CS0_CSCRU, CS0_CSCRL, CS0_CSCRA */ { .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, }, { .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, }, { .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, }, /* DDR2 init */ { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, }, /* initial value for ESDCFG0 */ { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000204, }, /* ESD_MISC */ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, /* CS0 precharge command */ { .ptr_type = 4, .addr = 0x80000f00, .val = 0x12344321, }, /* precharge all dummy write */ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, /* Load Mode Register command */ { .ptr_type = 1, .addr = 0x82000000, .val = 0xda, }, /* dummy write Load EMR2 */ { .ptr_type = 1, .addr = 0x83000000, .val = 0xda, }, /* dummy write Load EMR3 */ { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, /* dummy write Load EMR1; enable DLL */ { .ptr_type = 1, .addr = 0x80000333, .val = 0xda, }, /* dummy write Load MR; reset DLL */ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, /* CS0 precharge command */ { .ptr_type = 4, .addr = 0x80000400, .val = 0x12345678, }, /* precharge all dummy write */ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xA2210000, }, /* select manual refresh mode */ { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, /* manual refresh */ { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, /* manual refresh twice */ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, /* Load Mode Register command */ { .ptr_type = 1, .addr = 0x80000233, .val = 0xda, }, /* Load MR; CL=3, BL=8, end DLL reset */ { .ptr_type = 1, .addr = 0x81000780, .val = 0xda, }, /* Load EMR1; OCD default */ { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, /* Load EMR1; OCD exit */ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, /* normal mode */ /* IOMUX_SW_PAD setup */ { .ptr_type = 4, .addr = 0x43FAC454, .val = 0x00001000, }, /* IOMUXC_SW_PAD_CTL_GRP_DDRTYPE(1-5) */ { .ptr_type = 4, .addr = 0x43FAC448, .val = 0x00002000, }, /* IOMUXC_SW_PAD NFC voltage 1.8 */ /* CLKCTL */ { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, /* CLKCTL ARM=399 AHB=133 */ }; > All the things in lowlevel_init are then done when running from SDRAM > anyway (at least when doing a dcd based boot), so they can safely be > done later. > > The next thing is that the clocks are correctly initialized before the > corresponding devices are registered. > I have seen that some devices simply enable all clocks in lowlevel and some enable the necessary ones at a later stage. To be sure, I have included both versions in my setup, so I can assure that all the necessary clocks are running on boot init. > So let's analyze Eukreas lowlevel init: > > > > void __bare_init __naked board_init_lowlevel(void) > > { > > uint32_t r; > > #ifdef CONFIG_NAND_IMX_BOOT > > unsigned int *trg, *src; > > int i; > > #endif > > register uint32_t loops = 0x20000; > > > > /* restart the MPLL and wait until it's stable */ > > writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27), > > IMX_CCM_BASE + CCM_CCTL); > > while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {}; > > > > /* Configure dividers and ARM clock source > > * ARM @ 400 MHz > > * AHB @ 133 MHz > > */ > > writel(0x20034000, IMX_CCM_BASE + CCM_CCTL); > > This may influence the timer clock, so it can be here. > I have copied this, since it was also done in the old uboot version that works. > > > > /* Enable UART1 / FEC / */ > > /* writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0); > > writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1); > > writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2);*/ > > This brings the Clock gate registers to reset default. This may be a > good idea, but can be done later. > Ok, I have copied this. > > > > > /* AIPS setup - Only setup MPROTx registers. The PACR default > values are good. > > * Set all MPROTx to be non-bufferable, trusted for R/W, > > * not forced to user-mode. > > */ > > writel(0x77777777, 0x43f00000); > > writel(0x77777777, 0x43f00004); > > writel(0x77777777, 0x53f00000); > > writel(0x77777777, 0x53f00004); > > This can be done later. This is duplicated in many boards and is always > the same. Look for example at the i.MX53 code, there we have > imx53_init_lowlevel() which sets up the AIPS. This is common for all > i.MX53 and is called from an initcall. Similar could be done for i.MX25 > aswell, if somebody is willing to implement it. > I like the imx53_init_lowlevel() approach a lot, it's very clean and helps avoiding redundancy and maintenance costs. If I get my device to boot from NOR, I might be inclined to give it a shot. > > > > /* MAX (Multi-Layer AHB Crossbar Switch) setup > > * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB > > */ > > writel(0x00002143, 0x43f04000); > > writel(0x00002143, 0x43f04100); > > writel(0x00002143, 0x43f04200); > > writel(0x00002143, 0x43f04300); > > writel(0x00002143, 0x43f04400); > > /* SGPCR - always park on last master */ > > writel(0x10, 0x43f04010); > > writel(0x10, 0x43f04110); > > writel(0x10, 0x43f04210); > > writel(0x10, 0x43f04310); > > writel(0x10, 0x43f04410); > > /* MGPCR - restore default values */ > > writel(0x0, 0x43f04800); > > writel(0x0, 0x43f04900); > > writel(0x0, 0x43f04a00); > > writel(0x0, 0x43f04b00); > > writel(0x0, 0x43f04c00); > > > > /* Configure M3IF registers > > * M3IF Control Register (M3IFCTL) for MX25 > > * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 > > * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 > > * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 > > * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000 > > * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 > > * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000 > > * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000 > > * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 > > * ---------- > > * 0x00000001 > > */ > > writel(0x1, 0xb8003000); > > Same as above. > > > > > /* Speed up NAND controller by adjusting the NFC divider */ > > r = readl(IMX_CCM_BASE + CCM_PCDR2); > > r &= ~0xf; > > r |= 0x1; > > writel(r, IMX_CCM_BASE + CCM_PCDR2); > > This is necessary for external NAND boot. The NAND controller comes up > with a low speed which makes the copying of the image > (CONFIG_NAND_IMX_BOOT below) slow. This is optional but has to be done > here to get a faster boot. > > Ok, I reckon there is nothing comparable which should be done in the NOR case. > > > > /* Skip SDRAM initialization if we run from RAM */ > > r = get_pc(); > > if (r > 0x80000000 && r < 0x90000000) > > board_init_lowlevel_return(); > > Here we bail out for second stage boots (and also internal bootmode > where we are already running from SDRAM > It's this place where I wanted to put a printf() to see where the code is actually branching and if my setting of the corresponding WEIM CS0 registers upset the processor already. However, it seems as if printf()'s here is a no-go. > > > > /* Init Mobile DDR */ > > writel(0x0000000E, ESDMISC); > > writel(0x00000004, ESDMISC); > > __asm__ volatile ("1:\n" > > "subs %0, %1, #1\n" > > "bne 1b":"=r" (loops):"0" (loops)); > > > > writel(0x0029572B, ESDCFG0); > > writel(0x92210000, ESDCTL0); > > writeb(0xda, IMX_SDRAM_CS0 + 0x400); > > writel(0xA2210000, ESDCTL0); > > writeb(0xda, IMX_SDRAM_CS0); > > writeb(0xda, IMX_SDRAM_CS0); > > writel(0xB2210000, ESDCTL0); > > writeb(0xda, IMX_SDRAM_CS0 + 0x33); > > writeb(0xda, IMX_SDRAM_CS0 + 0x1000000); > > writel(0x82216080, ESDCTL0); > > RAM init for external bootmode, has to be done here. > I left it there. > > > > > #ifdef CONFIG_NAND_IMX_BOOT > > /* skip NAND boot if not running from NFC space */ > > r = get_pc(); > > if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) > > board_init_lowlevel_return(); > > > > src = (unsigned int *)IMX_NFC_BASE; > > trg = (unsigned int *)TEXT_BASE; > > > > /* Move ourselves out of NFC SRAM */ > > for (i = 0; i < 0x800 / sizeof(int); i++) > > *trg++ = *src++; > > > > /* Jump to SDRAM */ > > r = (unsigned int)&insdram; > > __asm__ __volatile__("mov pc, %0" : : "r"(r)); > > #else > > board_init_lowlevel_return(); > > #endif > > Finally copy the image from NAND SRAM to SDRAM, only needed for external > NAND boot. > > And since I am trying to perform an internal MMC or NOR boot, this does not affect me at all. > Often the whole lowlevel stuff is setup in early assembly code. This has > mostly historical reasons and 'hey, this is hardcore stuff we configure > here, we must do it early and we must do it in assembly'. Much of the > lowlevel stuff we have in barebox is just copied from a working U-Boot > or redboot setup and never touched again, hence the slightly chaotic > situation. > This is what I have slowly come to understand while reading more source code over the weekend. I have also found the old uboot init part for this device from 2009.08 and have adapted my lowlevel and device part code accordingly. I wonder if someone could write a quick and dirty perl/shell script to auto-port devices from uboot to barebox, at least the basic booting facility. In my case, there is one peculiarity in the u-boot sources, which I haven't been able to map to barebox yet and it's best described by the corresponding code: #include <common.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/mx25.h> #include <asm/arch/mx25-regs.h> #include <asm/arch/mx25_pins.h> #include <asm/arch/iomux.h> #include <asm/arch/gpio.h> #include <imx_spi.h> #ifdef CONFIG_CMD_MMC #include <mmc.h> #include <fsl_esdhc.h> #endif DECLARE_GLOBAL_DATA_PTR; static u32 system_rev; u32 get_board_rev(void) { return system_rev; } static inline void setup_soc_rev(void) { int reg; reg = __REG(IIM_BASE + IIM_SREV); if (!reg) { reg = __REG(ROMPATCH_REV); reg <<= 4; } else reg += CHIP_REV_1_0; system_rev = 0x25000 + (reg & 0xFF); } inline int is_soc_rev(int rev) { return (system_rev & 0xFF) - rev; } int dram_init(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } #ifdef CONFIG_CMD_MMC u32 *imx_esdhc_base_addr; int esdhc_gpio_init(void) { u32 interface_esdhc = 0, val = 0; interface_esdhc = (readl(CCM_RCSR) & (0x00300000)) >> 20; switch (interface_esdhc) { case 0: imx_esdhc_base_addr = (u32 *)MMC_SDHC1_BASE; /* Pins */ writel(0x10, IOMUXC_BASE + 0x190); /* SD1_CMD */ writel(0x10, IOMUXC_BASE + 0x194); /* SD1_CLK */ writel(0x00, IOMUXC_BASE + 0x198); /* SD1_DATA0 */ writel(0x00, IOMUXC_BASE + 0x19c); /* SD1_DATA1 */ writel(0x00, IOMUXC_BASE + 0x1a0); /* SD1_DATA2 */ writel(0x00, IOMUXC_BASE + 0x1a4); /* SD1_DATA3 */ /*ENABLE NOR writel(0x06, IOMUXC_BASE + 0x094); // D12 (SD1_DATA4) writel(0x06, IOMUXC_BASE + 0x090); // D13 (SD1_DATA5) writel(0x06, IOMUXC_BASE + 0x08c); // D14 (SD1_DATA6) writel(0x06, IOMUXC_BASE + 0x088); // D15 (SD1_DATA7) writel(0x05, IOMUXC_BASE + 0x010); // A14 (SD1_WP) writel(0x05, IOMUXC_BASE + 0x014); // A15 (SD1_DET) */ /* Pads */ writel(0xD1, IOMUXC_BASE + 0x388); /* SD1_CMD */ writel(0xD1, IOMUXC_BASE + 0x38c); /* SD1_CLK */ writel(0xD1, IOMUXC_BASE + 0x390); /* SD1_DATA0 */ writel(0xD1, IOMUXC_BASE + 0x394); /* SD1_DATA1 */ writel(0xD1, IOMUXC_BASE + 0x398); /* SD1_DATA2 */ writel(0xD1, IOMUXC_BASE + 0x39c); /* SD1_DATA3 */ /* ENABLE NOR writel(0xD1, IOMUXC_BASE + 0x28c); // D12 (SD1_DATA4) writel(0xD1, IOMUXC_BASE + 0x288); // D13 (SD1_DATA5) writel(0xD1, IOMUXC_BASE + 0x284); // D14 (SD1_DATA6) writel(0xD1, IOMUXC_BASE + 0x280); // D15 (SD1_DATA7) writel(0xD1, IOMUXC_BASE + 0x230); // A14 (SD1_WP) writel(0xD1, IOMUXC_BASE + 0x234); // A15 (SD1_DET) */ /* * Set write protect and card detect gpio as inputs * A14 (SD1_WP) and A15 (SD1_DET) */ val = ~(3 << 0) & readl(GPIO1_BASE + GPIO_GDIR); writel(val, GPIO1_BASE + GPIO_GDIR); break; case 1: imx_esdhc_base_addr = (u32 *)MMC_SDHC2_BASE; /* Pins */ writel(0x16, IOMUXC_BASE + 0x0e8); /* LD8 (SD1_CMD) */ writel(0x16, IOMUXC_BASE + 0x0ec); /* LD9 (SD1_CLK) */ writel(0x06, IOMUXC_BASE + 0x0f0); /* LD10 (SD1_DATA0) */ writel(0x06, IOMUXC_BASE + 0x0f4); /* LD11 (SD1_DATA1) */ writel(0x06, IOMUXC_BASE + 0x0f8); /* LD12 (SD1_DATA2) */ writel(0x06, IOMUXC_BASE + 0x0fc); /* LD13 (SD1_DATA3) */ writel(0x02, IOMUXC_BASE + 0x120); /* CSI_D2 (SD1_DATA4) */ writel(0x02, IOMUXC_BASE + 0x124); /* CSI_D3 (SD1_DATA5) */ writel(0x02, IOMUXC_BASE + 0x128); /* CSI_D4 (SD1_DATA6) */ writel(0x02, IOMUXC_BASE + 0x12c); /* CSI_D5 (SD1_DATA7) */ /* Pads */ writel(0xD1, IOMUXC_BASE + 0x2e0); /* LD8 (SD1_CMD) */ writel(0xD1, IOMUXC_BASE + 0x2e4); /* LD9 (SD1_CLK) */ writel(0xD1, IOMUXC_BASE + 0x2e8); /* LD10 (SD1_DATA0) */ writel(0xD1, IOMUXC_BASE + 0x2ec); /* LD11 (SD1_DATA1) */ writel(0xD1, IOMUXC_BASE + 0x2f0); /* LD12 (SD1_DATA2) */ writel(0xD1, IOMUXC_BASE + 0x2f4); /* LD13 (SD1_DATA3) */ writel(0xD1, IOMUXC_BASE + 0x318); /* CSI_D2 (SD1_DATA4) */ writel(0xD1, IOMUXC_BASE + 0x31c); /* CSI_D3 (SD1_DATA5) */ writel(0xD1, IOMUXC_BASE + 0x320); /* CSI_D4 (SD1_DATA6) */ writel(0xD1, IOMUXC_BASE + 0x324); /* CSI_D5 (SD1_DATA7) */ break; default: break; } return 0; } int board_mmc_init(void) { if (!esdhc_gpio_init()) return fsl_esdhc_mmc_init(gd->bd); else return -1; } #endif void spi_io_init(struct imx_spi_dev_t *dev) { switch (dev->base) { case CSPI1_BASE: writel(0, IOMUXC_BASE + 0x180); /* CSPI1 SCLK */ writel(0x1C0, IOMUXC_BASE + 0x5c4); writel(0, IOMUXC_BASE + 0x184); /* SPI_RDY */ writel(0x1E0, IOMUXC_BASE + 0x5c8); writel(0, IOMUXC_BASE + 0x170); /* MOSI */ writel(0x1C0, IOMUXC_BASE + 0x5b4); writel(0, IOMUXC_BASE + 0x174); /* MISO */ writel(0x1C0, IOMUXC_BASE + 0x5b8); writel(0, IOMUXC_BASE + 0x17C); /* SS1 */ writel(0x1E0, IOMUXC_BASE + 0x5C0); break; default: break; } } int board_init(void) { setup_soc_rev(); /* setup pins for UART1 */ /* UART 1 IOMUX Configs */ mxc_request_iomux(MX25_PIN_UART1_RXD, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_UART1_TXD, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_UART1_CTS, MUX_CONFIG_FUNC); mxc_iomux_set_pad(MX25_PIN_UART1_RXD, PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX25_PIN_UART1_TXD, PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); mxc_iomux_set_pad(MX25_PIN_UART1_RTS, PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX25_PIN_UART1_CTS, PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); /* setup pins for FEC */ mxc_request_iomux(MX25_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_FEC_MDC, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_FEC_MDIO, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); mxc_request_iomux(MX25_PIN_POWER_FAIL, MUX_CONFIG_FUNC); /* PHY INT */ #define FEC_PAD_CTL1 (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PUE_PUD | \ PAD_CTL_PKE_ENABLE) #define FEC_PAD_CTL2 (PAD_CTL_PUE_PUD) mxc_iomux_set_pad(MX25_PIN_FEC_TX_CLK, FEC_PAD_CTL1); mxc_iomux_set_pad(MX25_PIN_FEC_RX_DV, FEC_PAD_CTL1); mxc_iomux_set_pad(MX25_PIN_FEC_RDATA0, FEC_PAD_CTL1); mxc_iomux_set_pad(MX25_PIN_FEC_TDATA0, FEC_PAD_CTL2); mxc_iomux_set_pad(MX25_PIN_FEC_TX_EN, FEC_PAD_CTL2); mxc_iomux_set_pad(MX25_PIN_FEC_MDC, FEC_PAD_CTL2); mxc_iomux_set_pad(MX25_PIN_FEC_MDIO, FEC_PAD_CTL1 | PAD_CTL_22K_PU); mxc_iomux_set_pad(MX25_PIN_FEC_RDATA1, FEC_PAD_CTL1); mxc_iomux_set_pad(MX25_PIN_FEC_TDATA1, FEC_PAD_CTL2); mxc_iomux_set_pad(MX25_PIN_POWER_FAIL, FEC_PAD_CTL1); /* * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. * Assert FEC_RESET_B, then power up the PHY by asserting * FEC_ENABLE, at the same time lifting FEC_RESET_B. * * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin D12 * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin A17 */ /*FQ FOR ENABLE NOR mxc_request_iomux(MX25_PIN_A17, MUX_CONFIG_ALT5); // FEC_EN mxc_request_iomux(MX25_PIN_D12, MUX_CONFIG_ALT5); // FEC_RESET_B mxc_iomux_set_pad(MX25_PIN_A17, PAD_CTL_ODE_OpenDrain); mxc_iomux_set_pad(MX25_PIN_D12, 0); mxc_set_gpio_direction(MX25_PIN_A17, 0); // FEC_EN mxc_set_gpio_direction(MX25_PIN_D12, 0); // FEC_RESET_B /* drop PHY power mxc_set_gpio_dataout(MX25_PIN_A17, 0); // FEC_EN // assert reset mxc_set_gpio_dataout(MX25_PIN_D12, 0); // FEC_RESET_B udelay(2); // spec says 1us min // turn on PHY power and lift reset mxc_set_gpio_dataout(MX25_PIN_A17, 1); // FEC_EN mxc_set_gpio_dataout(MX25_PIN_D12, 1); // FEC_RESET_B */ #define I2C_PAD_CTL (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \ PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain) mxc_request_iomux(MX25_PIN_I2C1_CLK, MUX_CONFIG_SION); mxc_request_iomux(MX25_PIN_I2C1_DAT, MUX_CONFIG_SION); mxc_iomux_set_pad(MX25_PIN_I2C1_CLK, 0x1E8); mxc_iomux_set_pad(MX25_PIN_I2C1_DAT, 0x1E8); gd->bd->bi_arch_number = MACH_TYPE_MX25_3DS; /* board id for linux */ gd->bd->bi_boot_params = 0x80000100; /* address of boot parameters */ return 0; #undef FEC_PAD_CTL1 #undef FEC_PAD_CTL2 #undef I2C_PAD_CTL } #ifdef BOARD_LATE_INIT int board_late_init(void) { u8 reg[4]; /* Turn PMIC On*/ reg[0] = 0x09; i2c_write(0x54, 0x02, 1, reg, 1); #ifdef CONFIG_IMX_SPI_CPLD mxc_cpld_spi_init(); #endif return 0; } #endif int checkboard(void) { printf("Boot Device: SD Card \n"); printf("Board: SID1 i.MX25 \n"); return 0; } int board_eth_init(bd_t *bis) { int rc = -ENODEV; #if defined(CONFIG_SMC911X) rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); #endif return rc; } It seems as if in order to support NOR upon boot, the following PADs and PINs have to be disabled: writel(0x06, IOMUXC_BASE + 0x094); // D12 (SD1_DATA4) writel(0x06, IOMUXC_BASE + 0x090); // D13 (SD1_DATA5) writel(0x06, IOMUXC_BASE + 0x08c); // D14 (SD1_DATA6) writel(0x06, IOMUXC_BASE + 0x088); // D15 (SD1_DATA7) writel(0x05, IOMUXC_BASE + 0x010); // A14 (SD1_WP) writel(0x05, IOMUXC_BASE + 0x014); // A15 (SD1_DET) Why, and how could I find the corresponding barebox mappings? I recall that last week someone wanted to synchronize the IOMUX settings with the kernel ones. But still, why this change and could this affect my issue I am seeing with barebox? I still cannot initialize the NOR upon MMC internal boot on my device. Hope I could help you a bit. > > A lot, let me know where I can send the beers or any beverage to as soon as I get the bloody thing booting from NOR and showing up my NOR :). Take care Roberto [-- Attachment #1.2: Type: text/html, Size: 47260 bytes --] [-- Attachment #2: Type: text/plain, Size: 149 bytes --] _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2012-06-05 7:10 UTC | newest] Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-05-22 12:11 Booting mx25 based device from SD and NOR Roberto Nibali 2012-05-22 18:42 ` Sascha Hauer 2012-05-23 10:43 ` Roberto Nibali 2012-05-23 11:47 ` Eric Bénard 2012-05-24 12:49 ` Roberto Nibali 2012-05-24 12:58 ` Eric Bénard 2012-05-24 13:18 ` Roberto Nibali 2012-05-24 13:31 ` Eric Bénard 2012-05-25 9:04 ` Roberto Nibali 2012-05-25 10:08 ` Eric Bénard 2012-05-29 9:06 ` Roberto Nibali 2012-05-29 9:29 ` Sascha Hauer 2012-05-29 9:56 ` Roberto Nibali 2012-05-29 10:14 ` Roberto Nibali 2012-05-30 5:47 ` Sascha Hauer 2012-05-30 6:39 ` Juergen Beisert 2012-05-31 13:12 ` Roberto Nibali 2012-05-31 17:06 ` Sascha Hauer 2012-06-01 10:25 ` Roberto Nibali 2012-06-05 7:09 ` Sascha Hauer 2012-05-24 17:17 ` Sascha Hauer 2012-05-25 9:19 ` Roberto Nibali 2012-05-25 10:01 ` Sascha Hauer 2012-05-29 9:26 ` Roberto Nibali
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