Re: Booting mx25 based device from SD and NOR

[Roberto Nibali <rnibali@gmail.com>]

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ADDENDUM:

>         { .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, },
>> >         { .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, },
>> >         { .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, },
>>
>> Do these values match the ones you read out of the registers using your
>> U-Boot?
>>
>
> Yep, the corresponing dcdheader.S entries:
>
> DCDGEN( 1, 4, 0xB8002000, 0x0000D003) /* CS0_CSCRU */
> DCDGEN( 2, 4, 0xB8002004, 0x00330d01) /* CS0_CSCRL */
> DCDGEN( 3, 4, 0xB8002008, 0x00220800) /* CS0_CSCRA */
>
> So I reckon at least I got this part working fine.
>
>  > /* Set up 16bit NOR flash on WEIM CS0 */
>> > writel(0xB8002000, 0x0000D003);
>> >  writel(0xB8002004, 0x00330D01);
>> > writel(0xB8002008, 0x00220800);
>>
>> You mixed up the argument order.
>>
>> Yikes!!!! I hope I didn't fry something. I'll quickly try the reversed
> order and report back.
>

It does not change the fact that it still does not recognize my NOR. I am
at my wits' end here, so I go along posting my patch to support the mx25
based device for review:

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d0bfd71..483b47e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -133,6 +133,7 @@ board-$(CONFIG_MACH_TX25) := karo-tx25
 board-$(CONFIG_MACH_TQMA53) := tqma53
 board-$(CONFIG_MACH_TX51) := karo-tx51
 board-$(CONFIG_MACH_MX6Q_ARM2) := freescale-mx6-arm2
+board-$(CONFIG_MACH_MX25_NOAH) := fq-sid1-mx25-noah

 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))

diff --git a/arch/arm/boards/fq-sid1-mx25-noah/Makefile
b/arch/arm/boards/fq-sid1-mx25-noah/Makefile
new file mode 100644
index 0000000..1e9cd54
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/Makefile
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+obj-y += lowlevel.o
+obj-y += sid1_noah.o
+obj-y += extra_commands.o
+obj-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/config.h
b/arch/arm/boards/fq-sid1-mx25-noah/config.h
new file mode 100644
index 0000000..f35e8a0
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/config.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+
+#define CONFIG_MX25_HCLK_FREQ 24000000
+
+#endif
+
+/* nothing to do here yet */
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/_update
b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/_update
new file mode 100644
index 0000000..014bce3
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/_update
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+if [ -z "$part" -o -z "$image" ]; then
+ echo "define \$part and \$image"
+ exit 1
+fi
+
+if [ ! -e "$part" ]; then
+ echo "Partition $part does not exist"
+ exit 1
+fi
+
+if [ $# = 1 ]; then
+ image=$1
+fi
+
+if [ x$ip = xdhcp ]; then
+ dhcp
+fi
+
+ping $eth0.serverip
+if [ $? -ne 0 ] ; then
+ echo "update aborted"
+ exit 1
+fi
+
+unprotect $part
+
+echo
+echo "erasing partition $part"
+erase $part
+
+echo
+echo "flashing $image to $part"
+echo
+tftp $image $part
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/boot
b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/boot
new file mode 100644
index 0000000..d06fc16
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/boot
@@ -0,0 +1,38 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 != x ]; then
+ boot=$1
+ kernel=$1
+fi
+
+if [ x$boot = xnor ]; then
+ bootargs="$bootargs root=$nor_rootpart rootfstype=jffs2"
+elif [ x$boot = xmmc ]; then
+ bootargs="$bootargs root=$mmc_rootpart rootfstype=ext3"
+elif [ x$boot = xnfs ]; then
+ bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
+ if [ x$getip = xdhcp ]; then
+ bootargs="$bootargs ip=dhcp"
+ else
+ bootargs="$bootargs
ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
+ fi
+fi
+
+# Generally add mtdparts to kernel cmdline
+bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts"
+
+if [ x$kernel = xtftp -o x$kernel = xnfs ]; then
+ if [ x$getip = xdhcp ]; then
+ echo "BOOT: Fetching IP address from $eth0.serverip"
+ dhcp
+ fi
+ tftp $tftp_uimage uImage || exit 1
+ bootm uImage
+elif [ x$kernel = xmmc ]; then
+ bootm $mmc_kernel
+elif [ x$kernel = xnor ]; then
+ bootm /dev/nor0.kernel
+fi
+
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init
b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init
new file mode 100644
index 0000000..070220d
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init
@@ -0,0 +1,23 @@
+#!/bin/sh
+
+PATH=/env/bin
+export PATH
+
+. /env/config
+
+if [ -e /dev/nor0 ]; then
+ addpart /dev/nor0 $nor_parts
+fi
+
+echo
+echo -n "Hit any key to stop autoboot: "
+timeout -a $autoboot_timeout
+if [ $? != 0 ]; then
+ echo
+ echo "type update_kernel nor [<imagename>] to update kernel into flash"
+ echo "type update_root nor [<imagename>] to update rootfs into flash"
+ echo
+ exit
+fi
+
+boot
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_kernel
b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_kernel
new file mode 100644
index 0000000..49523aa
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_kernel
@@ -0,0 +1,13 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+if [ x$1 = xnor ]; then
+ part=/dev/nor0.kernel
+else
+ echo "usage: $0 nor [imagename]"
+ exit 1
+fi
+
+. /env/bin/_update $2
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_root
b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_root
new file mode 100644
index 0000000..0935bc1
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_root
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+if [ x$1 = xnand ]; then
+ part=/dev/nand0.root.bb
+elif [ x$1 = xnor ]; then
+ part=/dev/nor0.root
+else
+ echo "usage: $0 nor [imagename]"
+ exit 1
+fi
+
+. /env/bin/_update $2
+
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/config
b/arch/arm/boards/fq-sid1-mx25-noah/env/config
new file mode 100644
index 0000000..240056d
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/env/config
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+autoboot_timeout=5
+
+# can be either 'nfs', 'tftp', 'nor', or 'mmc'
+kernel=tftp
+root=mmc
+
+version=/v2.1.8-rc
+tftp_uimage=$version/uImage
+tftp_jffs2=$version/console-image.jffs2
+bootargs="console=ttymxc0,115200"
+nfsroot="/home/develop/SID1/nfsroot"
+nor_parts="512k(barebox)ro,512k(bareboxenv),3072k(kernel),-(root)"
+nor_rootpart="/dev/mtdblock3"
+mmc_kernel="/dev/mmcblk0p1"
+mmc_rootpart="/dev/mmcblk0p2"
+getip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=192.168.1.80
+#eth0.netmask=255.255.255.0
+#eth0.gateway=a.b.c.d
+eth0.serverip=192.168.1.23
+eth0.ethaddr=00:50:c2:8c:e6:0e
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/extra_commands.c
b/arch/arm/boards/fq-sid1-mx25-noah/extra_commands.c
new file mode 100644
index 0000000..e57c61f
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/extra_commands.c
@@ -0,0 +1,66 @@
+/*
+ * (C) 2012 FQ Ingenieria, Roberto Nibali <rnibali@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <io.h>
+#include <common.h>
+#include <command.h>
+#include <mach/imx-regs.h>
+#include <mach/imx-pll.h>
+
+#define MPCTL_PARAM_399     (IMX_PLL_PD(0) | IMX_PLL_MFD(15) |
IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
+#define MPCTL_PARAM_532     ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) |
IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
+
+static int do_cpufreq(int argc, char *argv[])
+{
+ /* 15.3.3.1 Core PLL (MPLL) Control Register (MPCTL) */
+        unsigned long freq;
+
+        if (argc != 2)
+                return COMMAND_ERROR_USAGE;
+
+        freq = simple_strtoul(argv[1], NULL, 0);
+
+        switch (freq) {
+        case 399:
+                writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
+                break;
+        case 532:
+                writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+                break;
+        default:
+                return COMMAND_ERROR_USAGE;
+        }
+
+        printf("Switched CPU frequency to %ldMHz\n", freq);
+
+        return 0;
+}
+
+static const __maybe_unused char cmd_cpufreq_help[] =
+"Usage: cpufreq 399|532\n"
+"\n"
+"Set CPU frequency to <freq> MHz\n";
+
+BAREBOX_CMD_START(cpufreq)
+ .cmd            = do_cpufreq,
+ .usage          = "adjust CPU frequency",
+ BAREBOX_CMD_HELP(cmd_cpufreq_help)
+BAREBOX_CMD_END
+
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c
b/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c
new file mode 100644
index 0000000..982fc52
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c
@@ -0,0 +1,88 @@
+#include <common.h>
+#include <mach/imx-flash-header.h>
+#include <mach/imx-regs.h>
+#include <asm/barebox-arm-head.h>
+
+extern void exception_vectors(void);
+
+void __naked __flash_header_start go(void)
+{
+ barebox_arm_head();
+}
+
+/*
+   The Flash header is a data structure that the boot code reads from
+   Flash which provides information about the application. The Flash
+   header must be located at a known fixed address depending on the
+   type of external Flash device connected to i.MX25. The Flash header
+   is only required when an internal boot mode is selected from
+   BOOT_MODE[0:1]. The required offsets of the Flash header for each
+   device type are described in Table 7-10.
+
+   NOR:   4 Kbyte = 0x1000 bytes
+   NAND:  1 Kbyte = 0x400 bytes
+   OneNAND: 256 bytes = 0x100 bytes
+   SD/eSD/MMC/eMMC:   1 kbyte = 0x400 bytes
+   I2C/CSPI EEPROM:   1 kbyte = 0x400 bytes
+
+   The above flash header offsets are set accordingly in:
+ arch/arm/mach-imx/include/mach/imx-flash-header.h
+
+   TEXT_BASE = 0x83F00000
+   IMX_CS0_BASE = 0xA0000000
+   #if INTERNAL_BOOT
+ DEST_BASE = IMX_CS0_BASE
+   #else
+ DEST_BASE = TEXT_BASE
+   #endif
+   FLASH_HEADER_BASE = (DEST_BASE + FLASH_HEADER_OFFSET)
+ */
+
+struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
+ /* NOR flash, CS0_CSCRU, CS0_CSCRL, CS0_CSCRA */
+ { .ptr_type = 4, .addr = 0xB8002000, .val = 0x0000D003, },
+ { .ptr_type = 4, .addr = 0xB8002004, .val = 0x00330D01, },
+ { .ptr_type = 4, .addr = 0xB8002008, .val = 0x00220800, },
+ /* DDR2 init */
+ { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, }, /* initial
value for ESDCFG0 */
+ { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000204, }, /* ESD_MISC */
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, /* CS0
precharge command */
+ { .ptr_type = 4, .addr = 0x80000f00, .val = 0x12344321, }, /* precharge
all dummy write */
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, /* Load Mode
Register command */
+ { .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },   /* dummy write
Load EMR2 */
+ { .ptr_type = 1, .addr = 0x83000000, .val = 0xda, },   /* dummy write
Load EMR3 */
+ { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, },   /* dummy write
Load EMR1; enable DLL */
+ { .ptr_type = 1, .addr = 0x80000333, .val = 0xda, },   /* dummy write
Load MR; reset DLL */
+
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, /* CS0
precharge command */
+ { .ptr_type = 4, .addr = 0x80000400, .val = 0x12345678, }, /* precharge
all dummy write */
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xA2210000, }, /* select
manual refresh mode */
+ { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, /* manual
refresh */
+ { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, /* manual
refresh twice */
+
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, /* Load Mode
Register command */
+ { .ptr_type = 1, .addr = 0x80000233, .val = 0xda, },   /* Load MR; CL=3,
BL=8, end DLL reset */
+ { .ptr_type = 1, .addr = 0x81000780, .val = 0xda, },   /* Load EMR1; OCD
default */
+ { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, },   /* Load EMR1; OCD
exit */
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, /* normal mode
*/
+ /* IOMUX_SW_PAD setup */
+ { .ptr_type = 4, .addr = 0x43FAC454, .val = 0x00001000, }, /*
IOMUXC_SW_PAD_CTL_GRP_DDRTYPE(1-5) */
+ { .ptr_type = 4, .addr = 0x43FAC448, .val = 0x00002000, }, /*
IOMUXC_SW_PAD NFC voltage 1.8 */
+
+ /* CLKCTL */
+ { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, /* CLKCTL
ARM=399 AHB=133 */
+};
+
+struct imx_flash_header __flash_header_section flash_header = {
+ .app_code_jump_vector = DEST_BASE + ((unsigned int)&exception_vectors -
TEXT_BASE),
+ .app_code_barker = APP_CODE_BARKER,
+ .app_code_csf = 0, /* non-secure boot (table 7-11) */
+ .dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
+ .super_root_key = 0, /* non-secure boot (table 7-11) */
+ .dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker),
+ .app_dest = DEST_BASE,
+ .dcd_barker = DCD_BARKER,
+ .dcd_block_len = sizeof(dcd_entry),
+};
+
+unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c
b/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c
new file mode 100644
index 0000000..04ece36
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c
@@ -0,0 +1,188 @@
+/*
+ *
+ * (c) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <init.h>
+#include <mach/imx-regs.h>
+#include <mach/esdctl.h>
+#include <io.h>
+#include <mach/imx-nand.h>
+#include <asm/barebox-arm.h>
+#include <asm/system.h>
+#include <asm-generic/sections.h>
+#include <asm-generic/memory_layout.h>
+
+#ifdef CONFIG_NAND_IMX_BOOT
+static void __bare_init __naked insdram(void)
+{
+ uint32_t r;
+
+ /* setup a stack to be able to call imx_nand_load_image() */
+ r = STACK_BASE + STACK_SIZE - 12;
+ __asm__ __volatile__("mov sp, %0" : : "r"(r));
+
+ imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
+
+ board_init_lowlevel_return();
+}
+#endif
+
+/* Check 24.3.3.1 and 24.5.4.1.1 */
+static inline void __bare_init  setup_sdram(uint32_t base, uint32_t esdctl,
+ uint32_t esdcfg)
+{
+ uint32_t esdctlreg = ESDCTL0;
+ uint32_t esdcfgreg = ESDCFG0;
+
+ if (base == 0x90000000) {
+ esdctlreg += 8;
+ esdcfgreg += 8;
+ }
+
+ esdctl |= ESDCTL0_SDE;
+
+ writel(esdcfg, esdcfgreg);
+ writel(esdctl | ESDCTL0_SMODE_PRECHARGE, esdctlreg);
+ writel(0, base + 1024);
+ writel(esdctl | ESDCTL0_SMODE_AUTO_REFRESH, esdctlreg);
+ readb(base);
+ readb(base);
+ writel(esdctl | ESDCTL0_SMODE_LOAD_MODE, esdctlreg);
+ writeb(0, base + 0x33);
+ writel(esdctl, esdctlreg);
+}
+
+void __bare_init __naked board_init_lowlevel(void)
+{
+ uint32_t r;
+#ifdef CONFIG_NAND_IMX_BOOT
+ unsigned int *trg, *src;
+#endif
+
+        /* restart the MPLL and wait until it's stable */
+        writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27),
+                                                IMX_CCM_BASE + CCM_CCTL);
+        while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {};
+
+        /* Configure dividers and ARM clock source
+         *      ARM @ 400 MHz
+         *      AHB @ 133 MHz
+         */
+ writel(0x20034000, IMX_CCM_BASE + CCM_CCTL);
+
+ /* Set up 16bit NOR flash on WEIM CS0 */
+ writel(0x0000D003, 0xB8002000);
+ writel(0x00330D01, 0xB8002004);
+ writel(0x00220800, 0xB8002008);
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are
good.
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, 0x43f00000);
+ writel(0x77777777, 0x43f00004);
+ writel(0x77777777, 0x53f00000);
+ writel(0x77777777, 0x53f00004);
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup
+ * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
+ */
+ writel(0x00043210, 0x43f04000);
+ writel(0x00043210, 0x43f04100);
+ writel(0x00043210, 0x43f04200);
+ writel(0x00043210, 0x43f04300);
+ writel(0x00043210, 0x43f04400);
+ /* SGPCR - always park on last master */
+ writel(0x10, 0x43f04010);
+ writel(0x10, 0x43f04110);
+ writel(0x10, 0x43f04210);
+ writel(0x10, 0x43f04310);
+ writel(0x10, 0x43f04410);
+ /* MGPCR - restore default values */
+ writel(0x0, 0x43f04800);
+ writel(0x0, 0x43f04900);
+ writel(0x0, 0x43f04a00);
+ writel(0x0, 0x43f04b00);
+ writel(0x0, 0x43f04c00);
+
+ /* Configure M3IF registers
+ * M3IF Control Register (M3IFCTL) for MX25
+ * MRRP[0] = LCDC           on priority list (1 << 0)  = 0x00000001
+ * MRRP[1] = MAX1       not on priority list (0 << 1)  = 0x00000000
+ * MRRP[2] = MAX0       not on priority list (0 << 2)  = 0x00000000
+ * MRRP[3] = USB HOST   not on priority list (0 << 3)  = 0x00000000
+ * MRRP[4] = SDMA       not on priority list (0 << 4)  = 0x00000000
+ * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5)  = 0x00000000
+ * MRRP[6] = SCMFBC     not on priority list (0 << 6)  = 0x00000000
+ * MRRP[7] = CSI        not on priority list (0 << 7)  = 0x00000000
+ *                                                       ----------
+ *                                                       0x00000001
+ */
+ writel(0x1, 0xb8003000);
+
+ /* enable all the clocks */
+ writel(0x1fffffff, IMX_CCM_BASE + CCM_CGCR0);
+ writel(0xffffffff, IMX_CCM_BASE + CCM_CGCR1);
+ writel(0x000fdfff, IMX_CCM_BASE + CCM_CGCR2);
+
+ /* Set DDR2 and NFC group driver voltages */
+ writel(0x1000, IMX_IOMUXC_BASE + 0x454);
+ writel(0x2000, IMX_IOMUXC_BASE + 0x448);
+
+ /* Skip SDRAM initialization if we run from RAM */
+ r = get_pc();
+ if (r > 0x80000000 && r < 0x90000000)
+ board_init_lowlevel_return();
+
+ writel(ESDMISC_RST, ESDMISC);
+
+ while (!(readl(ESDMISC) & (1 << 31)));
+
+#define ESDCTLVAL (ESDCTL0_ROW13 | ESDCTL0_COL9 | ESDCTL0_DSIZ_15_0 | \
+ ESDCTL0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL)
+#define ESDCFGVAL (ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 | ESDCFGx_tRAS_6 | \
+ ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 | ESDCFGx_tRCD_3 | \
+ ESDCFGx_tRC_9)
+
+ setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL);
+ setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL);
+
+#ifdef CONFIG_NAND_IMX_BOOT
+ /* skip NAND boot if not running from NFC space */
+ r = get_pc();
+ if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+ board_init_lowlevel_return();
+
+ src = (unsigned int *)IMX_NFC_BASE;
+ trg = (unsigned int *)TEXT_BASE;
+
+ /* Move ourselves out of NFC SRAM */
+ for (i = 0; i < 0x800 / sizeof(int); i++)
+ *trg++ = *src++;
+
+ /* Jump to SDRAM */
+ r = (unsigned int)&insdram;
+ __asm__ __volatile__("mov pc, %0" : : "r"(r));
+#else
+ board_init_lowlevel_return();
+#endif
+}
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c
b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c
new file mode 100644
index 0000000..239d72a
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c
@@ -0,0 +1,377 @@
+/*
+ * (C) 2012 FQ Ingenieria, Roberto Nibali <rnibali@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <io.h>
+#include <sizes.h>
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <environment.h>
+#include <partition.h>
+#include <driver.h>
+#include <fec.h>
+#include <linux/err.h>
+#include <i2c/i2c.h>
+#include <generated/mach-types.h>
+#include <asm/armlinux.h>
+#include <asm/mmu.h>
+#include <asm/barebox-arm-head.h>
+#include <asm-generic/sections.h>
+#include <mach/gpio.h>
+#include <mach/iim.h>
+#include <mach/usb.h>
+#include <mach/imx-regs.h>
+#include <mach/imx-pll.h>
+#include <mach/imx-flash-header.h>
+#include <mach/iomux-mx25.h>
+#include <mach/generic.h>
+#include <mach/devices-imx25.h>
+
+/* The currently used MOSFET IRLMLL6402 needs
+   3.3V driver voltage to function, however the
+   basic GPIO driver voltage is 1.8V, which is
+   not sufficient, unless the MOSFET switches
+   starting from VGS > 1.5V.
+ */
+#define MX25_PAD_CS1__GPIO_4_3_DVS      IOMUX_PAD(0x000, 0x050, 0x05, 0,
0, NO_PAD_CTRL | PAD_CTL_DVS)
+
+static struct fec_platform_data fec_info = {
+ .xcv_type = RMII,
+ .phy_addr = 1,
+};
+
+#ifdef CONFIG_USB
+static void imx25_usb_init(void)
+{
+ uint32_t reg;
+
+        /* Host 1 */
+        reg = readl(IMX_OTG_BASE + 0x600);
+        reg &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+                MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
MX35_H1_IPPUE_UP_BIT);
+        reg |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT;
+        reg |= MX35_H1_USBTE_BIT;
+        reg |= MX35_H1_IPPUE_DOWN_BIT;
+ writel(reg, IMX_OTG_BASE + 0x600);
+
+ reg = readl(IMX_OTG_BASE + 0x584);
+ reg |= 3 << 30;
+ writel(reg, IMX_OTG_BASE + 0x584);
+
+ /* Set to Host mode */
+ reg = readl(IMX_OTG_BASE + 0x5a8);
+ writel(reg | 0x3, IMX_OTG_BASE + 0x5a8);
+}
+#endif
+
+/*
+static struct at24_platform_data board_eeprom = {
+ .byte_len = 65536,
+ .page_size = 128,
+ .flags = AT24_FLAG_ADDR16,
+};
+*/
+
+static struct i2c_board_info i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("at24", 0x50),
+ //.platform_data = &board_eeprom,
+ },
+};
+
+#if 0
+struct gpio_led noah_leds[] = {
+ {
+ .led = { .name = "GPIO-LED", },
+ .gpio = IMX_GPIO_NR(4, 10),
+ .active_low = 1,
+ },
+};
+
+static void noah_leds_init(void)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(noah_leds); i++)
+ led_gpio_register(&noah_leds[i]);
+}
+#endif
+
+#define MX25_NOAH_BOOT_UNKNOWN 0
+#define MX25_NOAH_BOOT_NOR 1
+#define MX25_NOAH_BOOT_MMC 2
+static int noah_read_ccm_regs(void) {
+ uint32_t reg;
+
+ /*  15.3.3.12 CCM Reset and Debug Register (CRDR)
+ */
+ reg = readl(IMX_CCM_BASE + CCM_CRDR);
+ printf("%s: CCM CRDR = %08X\n", __func__, reg);
+
+ /* 15.3.3.11 CCM Status Register (RCSR)
+ if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
+ nand_info.width = 2;
+ */
+ reg = readl(IMX_CCM_BASE + CCM_RCSR);
+ printf("%s: CCM RCSR = %08X\n", __func__, reg);
+ if ((reg & (0x3 << 30)) == 0x3 << 30) {
+ printf("%s: Booting from expansion device: ", __func__);
+ if ((reg & (0x3 << 28)) == 0x0 << 28) {
+ printf("SD/MMC\n");
+ return MX25_NOAH_BOOT_MMC;
+ } else {
+ printf("unknown\n");
+ }
+ } else if ((reg & (0x3 << 30)) == 0x0 << 30) {
+ printf("%s: Booting from WEIM: ", __func__);
+ if ((reg & (0x3 << 28)) == 0x0 << 28) {
+ printf("NOR\n");
+ return MX25_NOAH_BOOT_NOR;
+ } else {
+ printf("unknown\n");
+ }
+ }
+
+ return MX25_NOAH_BOOT_UNKNOWN;
+}
+
+#ifdef CONFIG_DRIVER_VIDEO_IMX
+static struct imx_fb_videomode imxfb_mode = {
+ .mode   = {
+ .name = "Chunghwa CLAA057VA01CT",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25600),
+ .left_margin = 46,
+ .right_margin = 114,
+ .upper_margin = 34,
+ .lower_margin = 11,
+ .hsync_len = 48,
+ .vsync_len = 3,
+ },
+ .bpp = 16,
+ .pcr = 0xFA000080, /* 16bpp: Check 33.3.10 of the IMX25RM: LPCR */
+};
+
+static struct imx_fb_platform_data noah_fb_data = {
+ .mode   = &imxfb_mode,
+ .num_modes = 1,
+ .pwmr   = 0x00A903FF,
+ .lscr1  = 0x00120300,
+ .dmacr  = 0x00020010,
+};
+#endif
+
+static iomux_v3_cfg_t imx25_pads[] = {
+ /* FEC RMII */
+ MX25_PAD_FEC_MDC__FEC_MDC,              /* Management data clock */
+ MX25_PAD_FEC_MDIO__FEC_MDIO,            /* Management data input/output */
+ MX25_PAD_FEC_TX_EN__FEC_TX_EN,          /* Transmit enable */
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV,          /* Carrier sense / receive data
valid */
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,        /* Synchronous clock reference
(REF_CLK) */
+ MX25_PAD_UART2_CTS__FEC_RX_ER,          /* Receive error */
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0,        /* Receive data */
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1,        /* Receive data */
+ MX25_PAD_FEC_TDATA0__FEC_TDATA0,        /* Transmit data */
+ MX25_PAD_FEC_TDATA1__FEC_TDATA1,        /* Transmit data */
+#ifdef CONFIG_DRIVER_SERIAL_IMX
+ /* UART1 */
+ MX25_PAD_UART1_RXD__UART1_RXD,
+ MX25_PAD_UART1_TXD__UART1_TXD,
+ MX25_PAD_UART1_RTS__UART1_RTS,
+ MX25_PAD_UART1_CTS__UART1_CTS,
+#endif
+#ifdef CONFIG_USB
+ /* USBH2 */
+ MX25_PAD_D9__USBH2_PWR,
+ MX25_PAD_D8__USBH2_OC,
+ MX25_PAD_LD0__USBH2_CLK,
+ MX25_PAD_LD1__USBH2_DIR,
+ MX25_PAD_LD2__USBH2_STP,
+ MX25_PAD_LD3__USBH2_NXT,
+ MX25_PAD_LD4__USBH2_DATA0,
+ MX25_PAD_LD5__USBH2_DATA1,
+ MX25_PAD_LD6__USBH2_DATA2,
+ MX25_PAD_LD7__USBH2_DATA3,
+ MX25_PAD_HSYNC__USBH2_DATA4,
+ MX25_PAD_VSYNC__USBH2_DATA5,
+ MX25_PAD_LSCLK__USBH2_DATA6,
+ MX25_PAD_OE_ACD__USBH2_DATA7,
+#endif
+ /* I2C1 */
+ MX25_PAD_I2C1_CLK__I2C1_CLK,
+ MX25_PAD_I2C1_DAT__I2C1_DAT,
+ /* ESDHC */
+ /*
+ MX25_PAD_SD1_CMD__SD1_CMD_NPU,
+ MX25_PAD_SD1_CLK__SD1_CLK_NPU,
+ MX25_PAD_SD1_DATA0__SD1_DATA0_NPU,
+ MX25_PAD_SD1_DATA1__SD1_DATA1_NPU,
+ MX25_PAD_SD1_DATA2__SD1_DATA2_NPU,
+ MX25_PAD_SD1_DATA3__SD1_DATA3_NPU,
+ */
+#ifdef CONFIG_DRIVER_VIDEO_IMX
+ /* LCD */
+ MX25_PAD_LD0__LD0,                      /* TFT[19]: Blue[0] (LSB)*/
+ MX25_PAD_LD1__LD1,                      /* TFT[18]: Blue[1] */
+ MX25_PAD_LD2__LD2,                      /* TFT[17]: Blue[2] */
+ MX25_PAD_LD3__LD3,                      /* TFT[15]: Blue[3] */
+ MX25_PAD_LD4__LD4,                      /* TFT[14]: Blue[4] */
+ MX25_PAD_LD5__LD5,                      /* TFT[13]: Blue[5] (MSB) */
+ MX25_PAD_LD6__LD6,                      /* TFT[27]: Green[0] (LSB) */
+ MX25_PAD_LD7__LD7,                      /* TFT[26]: Green[1] */
+ MX25_PAD_LD8__LD8,                      /* TFT[25]: Green[2] */
+ MX25_PAD_LD9__LD9,                      /* TFT[23]: Green[3] */
+ MX25_PAD_LD10__LD10,                    /* TFT[22]: Green[4] */
+ MX25_PAD_LD11__LD11,                    /* TFT[21]: Green[5] (MSB) */
+ MX25_PAD_LD12__LD12,                    /* TFT[35]: Red[0] (LSB) */
+ MX25_PAD_LD13__LD13,                    /* TFT[34]: Red[1] */
+ MX25_PAD_LD14__LD14,                    /* TFT[33]: Red[2] */
+ MX25_PAD_LD15__LD15,                    /* TFT[31]: Red[3] */
+ MX25_PAD_GPIO_E__LD16,                  /* TFT[30]: Red[4] */
+ MX25_PAD_GPIO_F__LD17,                  /* TFT[29]: Red[5] (MSB) */
+ MX25_PAD_HSYNC__GPIO_1_22,              /* TFT[ 3]: LCD_HSYNC */
+ MX25_PAD_VSYNC__GPIO_1_23,              /* TFT[ 8]: LCD_VSYNC */
+ MX25_PAD_LSCLK__LSCLK,                  /* TFT[38]: LCD_LSCLK */
+ MX25_PAD_OE_ACD__OE_ACD,                /* TFT[ 9]: LCD_DRDY */
+ MX25_PAD_CONTRAST__PWM4_PWMO,           /* TFT[12]: LCD backlight (PWM):
*/
+ MX25_PAD_CS1__GPIO_4_3_DVS,             /* TFT[xx]: LCD_EN */
+ MX25_PAD_EB1__GPIO_2_13,                /* TFT[ 1]: LCD_UP_DOWN */
+ MX25_PAD_BCLK__GPIO_4_4,                /* TFT[40]: LCD_LEFT_RIGHT */
+ MX25_PAD_CSI_D4__GPIO_1_29,             /* TFT[ 2]: LCD_DMS */
+#endif
+};
+
+static int noah_fec_init(void)
+{
+ /*
+ * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
+ * Assert FEC_RESET_B, then power up the PHY by asserting
+ * FEC_ENABLE, at the same time lifting FEC_RESET_B.
+ *
+ * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17
+ * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12
+ */
+ writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */
+ writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */
+
+#define FEC_ENABLE_GPIO 35
+#define FEC_RESET_B_GPIO 104
+
+ /* make the pins output */
+ gpio_direction_output(FEC_ENABLE_GPIO, 0);  /* drop PHY power */
+ gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
+ udelay(2);
+
+ /* turn on power & lift reset */
+ gpio_set_value(FEC_ENABLE_GPIO, 1);
+ gpio_set_value(FEC_RESET_B_GPIO, 1);
+
+ return 0;
+}
+late_initcall(noah_fec_init);
+
+static int imx25_mem_init(void)
+{
+ /* add memory bank to 0x80000000 (barebox_add_memory_bank()) */
+ arm_add_mem_device("ram0", IMX_SDRAM_CS0, 64 * 1024 * 1024);
+
+ return 0;
+}
+mem_initcall(imx25_mem_init);
+
+static int imx25_devices_init(void)
+{
+ int bootdev;
+
+ bootdev = noah_read_ccm_regs();
+ mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZE(imx25_pads));
+ i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
+ imx25_add_i2c0(NULL);
+ imx25_add_mmc0(NULL);
+ imx25_iim_register_fec_ethaddr();
+ imx25_add_fec(&fec_info);
+
+ printf("%s: Adding NOR flash device\n", __func__);
+ /* Configure 16 bit nor flash on WEIM cs0 */
+ imx25_setup_weimcs(0, 0x0000D003, 0x00330D01, 0x00220800);
+ /* NOR flash starts at CS0 addr 0xA0000000, set to 64MB */
+ add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, SZ_64M, 0);
+ printf("%s: Adding initial NOR flash partitions\n", __func__);
+ devfs_add_partition("nor0", 0x00000, SZ_512K, PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", SZ_512K, SZ_512K, PARTITION_FIXED, "env0");
+ //protect_file("/dev/env0", 1);
+#ifdef CONFIG_USB
+ imx25_usb_init();
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400,
NULL);
+#endif
+#ifdef CONFIG_DRIVER_VIDEO_IMX
+ //imx25_add_fb(&noah_fb_data);
+#endif
+ //noah_leds_init();
+ armlinux_set_bootparams((void *)0x80000100);
+ armlinux_set_architecture(MACH_TYPE_MX25_3DS);
+ armlinux_set_serial(imx_uid());
+
+ return 0;
+}
+device_initcall(imx25_devices_init);
+
+static int imx25_console_init(void)
+{
+ //imx25_init_lowlevel(800) + imx25_core_setup();
+ imx25_add_uart0();
+ return 0;
+}
+console_initcall(imx25_console_init);
+
+/* Check arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+   for more information, especially with regard to low_level
+   setup inside the core_setup part.
+*/
+static int imx25_core_setup(void)
+{
+ uint32_t reg;
+ /* Enable clocks:
+   UART1: 15
+   FEC : 23
+   SDHC1: 3/21
+   USB : 28
+   I2C : 6
+ */
+ reg = readl(IMX_CCM_BASE + CCM_CGCR0);
+ reg |= (1 << 6) | (1 << 23) | (1 << 15) | (1 << 21) | (1 << 3) | (1 <<
28);
+ reg = writel(reg, IMX_CCM_BASE + CCM_CGCR0);
+
+ reg = readl(IMX_CCM_BASE + CCM_CGCR1);
+ reg |= (1 << 23) | (1 << 15) | (1 << 13);
+ reg = writel(reg, IMX_CCM_BASE + CCM_CGCR1);
+
+ reg = readl(IMX_CCM_BASE + CCM_CGCR2);
+ reg |= (1 << 14);
+ reg = writel(reg, IMX_CCM_BASE + CCM_CGCR2);
+ /* CCM clocks: PER_12 -- PER_15 (15.3.3.10) */
+ //writel(0x03010101, IMX_CCM_BASE + CCM_PCDR3);
+ /* CCM clocks: PER_8 -- PER_11 (15.3.3.9) */
+ //writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2);
+ return 0;
+
+}
+core_initcall(imx25_core_setup);
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.dox
b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.dox
new file mode 100644
index 0000000..8b0e28a
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.dox
@@ -0,0 +1,79 @@
+/** @page SID1 (FQ Ingeniería)
+
+This device is also known as "NOAH" (http://www.fqingenieria.es/)
+
+This CPU card is based on a Freescale i.MX25 CPU. The card is shipped with:
+
+- 64 MiB synchronous dynamic RAM (DDR type)
+- 4 SIM/SAM sockets
+- USB OTG
+- ...
+
+Memory layout when @b barebox is running:
+
+- 0x80000000 start of SDRAM (IMX_SDRAM_CS0)
+- 0x80000100 start of kernel's boot parameters
+  - below malloc area: stack area
+  - below barebox: malloc area
+- 0x82000000 start of @b barebox
+
+@section get_sid1_noah_binary How to get the bootloader binary image:
+
+Using the default configuration:
+
+@verbatim
+make ARCH=arm noah_defconfig
+@endverbatim
+
+Build the bootloader binary image:
+
+@verbatim
+make ARCH=arm CROSS_COMPILE=armv5compiler
+@endverbatim
+
+@note replace the armv5compiler with your ARM v5 cross compiler.
+
+@section setup_falconwing How to prepare an MCI card to boot the "chumby
one" with barebox
+
+- Create four primary partitions on the SD card
+ - the second one for the persistant environment (512 kiB, at least 256k)
+ - the third one for the kernel (3 MiB ... 4 MiB in size)
+ - the fourth one for the root filesystem which can fill the rest of the
available space
+
+- Copy the default @b barebox environment into the second partition (no
filesystem required).
+
+- Copy the kernel into the third partition (no filesystem required).
+
+- Create the root filesystem in the 4th partition. You may copy an image
into this
+  partition or you can do it in the classic way: mkfs on it, mount it and
copy
+  all required data and programs into it.
+
+@section gpio_falconwing Available GPIOs
+
+The SID1 NOAH uses some GPIOs to control various features. With the
regular
+GPIO commands these features can be controlled at @a barebox's runtime.
+
+<table width="100%" border="1" cellspacing="1" cellpadding="3">
+        <tr>
+                <td>No</td>
+                <td>Direction</td>
+                <td>Function</td>
+                <td>Reset</td>
+                <td>Set</td>
+        </tr>
+        <tr>
+                <td>60</td>
+                <td>Output</td>
+                <td>Display Backlight</td>
+                <td>Backlight<br>Off</td>
+                <td>Backlight<br>On (100 %)</td>
+        </tr>
+        <tr>
+                <td>62</td>
+                <td>Input</td>
+                <td>Bend</td>
+                <td>Not pressed</td>
+                <td>Pressed</td>
+        </tr>
+</table>
+*/
diff --git a/arch/arm/configs/noah_defconfig
b/arch/arm/configs/noah_defconfig
new file mode 100644
index 0000000..152f0bf
--- /dev/null
+++ b/arch/arm/configs/noah_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARCH_IMX=y
+CONFIG_ARCH_IMX_EXTERNAL_BOOT=y
+CONFIG_ARCH_IMX25=y
+CONFIG_MACH_MX25_NOAH=y
+CONFIG_IMX_CLKO=y
+CONFIG_IMX_IIM=y
+CONFIG_AEABI=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_BROKEN=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_PROMPT="sid1-noah:"
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/fq-sid1-mx25-noah/env"
+CONFIG_BAREBOXENV_TARGET=y
+CONFIG_ENABLE_FLASH_NOISE=y
+CONFIG_ENABLE_PARTITION_NOISE=y
+CONFIG_ENABLE_DEVICE_NOISE=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_AUTOMOUNT=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_SAVES=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_SHA224SUM=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_MTEST_ALTERNATIVE=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_DRIVER_SPI_IMX=y
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
+CONFIG_DRIVER_CFI=y
+# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
+# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set
+CONFIG_MTD=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_OHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
+CONFIG_DRIVER_VIDEO_IMX=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_EEPROM_AT25=y
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_BZLIB=y
+CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3236762..839de09 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -23,6 +23,7 @@ config ARCH_TEXT_BASE
  default 0x7ff00000 if MACH_MX53_SMD
  default 0x87f00000 if MACH_GUF_CUPID
  default 0x93d00000 if MACH_TX25
+ default 0x83f00000 if MACH_MX25_NOAH
  default 0x7ff00000 if MACH_TQMA53
  default 0x97f00000 if MACH_TX51
  default 0x4fc00000 if MACH_MX6Q_ARM2
@@ -47,6 +48,7 @@ config BOARDINFO
  default "Freescale i.MX53 SMD" if MACH_FREESCALE_MX53_SMD
  default "Garz+Fricke Cupid" if MACH_GUF_CUPID
  default "Ka-Ro tx25" if MACH_TX25
+ default "SID1 NOAH" if MACH_MX25_NOAH
  default "TQ tqma53" if MACH_TQMA53
  default "Ka-Ro tx51" if MACH_TX51
  default "Freescale i.MX6q armadillo2" if MACH_MX6Q_ARM2
@@ -251,6 +253,12 @@ config MACH_TX25
  help
   Say Y here if you are using the Ka-Ro tx25 board

+config MACH_MX25_NOAH
+ bool "SID1 NOAH"
+ select MACH_HAS_LOWLEVEL_INIT
+ help
+  Say Y here if you are using the SID1 NOAH board
+
 endchoice

 endif
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h
b/arch/arm/mach-imx/include/mach/imx25-regs.h
index 73307c4..8225832 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -72,6 +72,7 @@
 #define CCM_LTR1 0x44
 #define CCM_LTR2 0x48
 #define CCM_LTR3 0x4c
+#define CCM_MCR 0x64

 #define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
 #define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
@@ -107,6 +108,22 @@
 #define CSCR_L(x)     (WEIM_BASE + 4 + (x) * 0x10)
 #define CSCR_A(x)     (WEIM_BASE + 8 + (x) * 0x10)

+/* Chip Select Registers */
+#define IMX_WEIM_BASE WEIM_BASE
+#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x
Upper Register    */
+#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x
Lower Register    */
+#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x
Addition Register */
+#define EIM  __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register
  */
+
+#ifndef __ASSEMBLY__
+static inline void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned
lower, unsigned addional)
+{
+        CSxU(cs) = upper;
+        CSxL(cs) = lower;
+        CSxA(cs) = addional;
+}
+#endif /* __ASSEMBLY__ */
+
 /*
  * Definitions for the clocksource driver
  *

Thanks and best regards
Roberto

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