From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-gh0-f177.google.com ([209.85.160.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SZJSM-0003FS-D0 for barebox@lists.infradead.org; Tue, 29 May 2012 10:15:19 +0000 Received: by ghbf11 with SMTP id f11so1841236ghb.36 for ; Tue, 29 May 2012 03:15:13 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <20120522184240.GM30400@pengutronix.de> <20120523134733.6164c4fb@eb-e6520> <20120524145837.42085b83@eb-e6520> <20120524153119.6d724afc@eb-e6520> <20120525120858.77dd6e7a@eb-e6520> <20120529092958.GP30400@pengutronix.de> From: Roberto Nibali Date: Tue, 29 May 2012 12:14:52 +0200 Message-ID: List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============8784144281687461080==" Sender: barebox-bounces@lists.infradead.org Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: Re: Booting mx25 based device from SD and NOR To: Sascha Hauer Cc: barebox@lists.infradead.org --===============8784144281687461080== Content-Type: multipart/alternative; boundary=e89a8f3ba4b92fb4b004c12a1c34 --e89a8f3ba4b92fb4b004c12a1c34 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable ADDENDUM: > { .ptr_type =3D 4, .addr =3D 0xB8002000, .val =3D 0x0000D003, }, >> > { .ptr_type =3D 4, .addr =3D 0xB8002004, .val =3D 0x00330D01, = }, >> > { .ptr_type =3D 4, .addr =3D 0xB8002008, .val =3D 0x00220800, = }, >> >> Do these values match the ones you read out of the registers using your >> U-Boot? >> > > Yep, the corresponing dcdheader.S entries: > > DCDGEN( 1, 4, 0xB8002000, 0x0000D003) /* CS0_CSCRU */ > DCDGEN( 2, 4, 0xB8002004, 0x00330d01) /* CS0_CSCRL */ > DCDGEN( 3, 4, 0xB8002008, 0x00220800) /* CS0_CSCRA */ > > So I reckon at least I got this part working fine. > > > /* Set up 16bit NOR flash on WEIM CS0 */ >> > writel(0xB8002000, 0x0000D003); >> > writel(0xB8002004, 0x00330D01); >> > writel(0xB8002008, 0x00220800); >> >> You mixed up the argument order. >> >> Yikes!!!! I hope I didn't fry something. I'll quickly try the reversed > order and report back. > It does not change the fact that it still does not recognize my NOR. I am at my wits' end here, so I go along posting my patch to support the mx25 based device for review: diff --git a/arch/arm/Makefile b/arch/arm/Makefile index d0bfd71..483b47e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -133,6 +133,7 @@ board-$(CONFIG_MACH_TX25) :=3D karo-tx25 board-$(CONFIG_MACH_TQMA53) :=3D tqma53 board-$(CONFIG_MACH_TX51) :=3D karo-tx51 board-$(CONFIG_MACH_MX6Q_ARM2) :=3D freescale-mx6-arm2 +board-$(CONFIG_MACH_MX25_NOAH) :=3D fq-sid1-mx25-noah machdirs :=3D $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/boards/fq-sid1-mx25-noah/Makefile b/arch/arm/boards/fq-sid1-mx25-noah/Makefile new file mode 100644 index 0000000..1e9cd54 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/Makefile @@ -0,0 +1,26 @@ +# +# (C) Copyright 2007 Juergen Beisert +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +obj-y +=3D lowlevel.o +obj-y +=3D sid1_noah.o +obj-y +=3D extra_commands.o +obj-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) +=3D flash_header.o diff --git a/arch/arm/boards/fq-sid1-mx25-noah/config.h b/arch/arm/boards/fq-sid1-mx25-noah/config.h new file mode 100644 index 0000000..f35e8a0 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/config.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 Juergen Beisert + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Definitions related to passing arguments to kernel. + */ + +#define CONFIG_MX25_HCLK_FREQ 24000000 + +#endif + +/* nothing to do here yet */ diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/_update b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/_update new file mode 100644 index 0000000..014bce3 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# =3D 1 ]; then + image=3D$1 +fi + +if [ x$ip =3D xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/boot b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/boot new file mode 100644 index 0000000..d06fc16 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 !=3D x ]; then + boot=3D$1 + kernel=3D$1 +fi + +if [ x$boot =3D xnor ]; then + bootargs=3D"$bootargs root=3D$nor_rootpart rootfstype=3Djffs2" +elif [ x$boot =3D xmmc ]; then + bootargs=3D"$bootargs root=3D$mmc_rootpart rootfstype=3Dext3" +elif [ x$boot =3D xnfs ]; then + bootargs=3D"$bootargs root=3D/dev/nfs nfsroot=3D$eth0.serverip:$nfsroot,v= 3,tcp" + if [ x$getip =3D xdhcp ]; then + bootargs=3D"$bootargs ip=3Ddhcp" + else + bootargs=3D"$bootargs ip=3D$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" + fi +fi + +# Generally add mtdparts to kernel cmdline +bootargs=3D"$bootargs mtdparts=3Dphysmap-flash.0:$nor_parts" + +if [ x$kernel =3D xtftp -o x$kernel =3D xnfs ]; then + if [ x$getip =3D xdhcp ]; then + echo "BOOT: Fetching IP address from $eth0.serverip" + dhcp + fi + tftp $tftp_uimage uImage || exit 1 + bootm uImage +elif [ x$kernel =3D xmmc ]; then + bootm $mmc_kernel +elif [ x$kernel =3D xnor ]; then + bootm /dev/nor0.kernel +fi + diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init new file mode 100644 index 0000000..070220d --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init @@ -0,0 +1,23 @@ +#!/bin/sh + +PATH=3D/env/bin +export PATH + +. /env/config + +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? !=3D 0 ]; then + echo + echo "type update_kernel nor [] to update kernel into flash" + echo "type update_root nor [] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_kernel b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_kernel new file mode 100644 index 0000000..49523aa --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_kernel @@ -0,0 +1,13 @@ +#!/bin/sh + +. /env/config + +image=3D$uimage +if [ x$1 =3D xnor ]; then + part=3D/dev/nor0.kernel +else + echo "usage: $0 nor [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_root b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_root new file mode 100644 index 0000000..0935bc1 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=3D$uimage +if [ x$1 =3D xnand ]; then + part=3D/dev/nand0.root.bb +elif [ x$1 =3D xnor ]; then + part=3D/dev/nor0.root +else + echo "usage: $0 nor [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/config b/arch/arm/boards/fq-sid1-mx25-noah/env/config new file mode 100644 index 0000000..240056d --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/env/config @@ -0,0 +1,25 @@ +#!/bin/sh + +autoboot_timeout=3D5 + +# can be either 'nfs', 'tftp', 'nor', or 'mmc' +kernel=3Dtftp +root=3Dmmc + +version=3D/v2.1.8-rc +tftp_uimage=3D$version/uImage +tftp_jffs2=3D$version/console-image.jffs2 +bootargs=3D"console=3Dttymxc0,115200" +nfsroot=3D"/home/develop/SID1/nfsroot" +nor_parts=3D"512k(barebox)ro,512k(bareboxenv),3072k(kernel),-(root)" +nor_rootpart=3D"/dev/mtdblock3" +mmc_kernel=3D"/dev/mmcblk0p1" +mmc_rootpart=3D"/dev/mmcblk0p2" +getip=3Ddhcp + +# or set your networking parameters here +#eth0.ipaddr=3D192.168.1.80 +#eth0.netmask=3D255.255.255.0 +#eth0.gateway=3Da.b.c.d +eth0.serverip=3D192.168.1.23 +eth0.ethaddr=3D00:50:c2:8c:e6:0e diff --git a/arch/arm/boards/fq-sid1-mx25-noah/extra_commands.c b/arch/arm/boards/fq-sid1-mx25-noah/extra_commands.c new file mode 100644 index 0000000..e57c61f --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/extra_commands.c @@ -0,0 +1,66 @@ +/* + * (C) 2012 FQ Ingenieria, Roberto Nibali + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include + +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) + +static int do_cpufreq(int argc, char *argv[]) +{ + /* 15.3.3.1 Core PLL (MPLL) Control Register (MPCTL) */ + unsigned long freq; + + if (argc !=3D 2) + return COMMAND_ERROR_USAGE; + + freq =3D simple_strtoul(argv[1], NULL, 0); + + switch (freq) { + case 399: + writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL); + break; + case 532: + writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); + break; + default: + return COMMAND_ERROR_USAGE; + } + + printf("Switched CPU frequency to %ldMHz\n", freq); + + return 0; +} + +static const __maybe_unused char cmd_cpufreq_help[] =3D +"Usage: cpufreq 399|532\n" +"\n" +"Set CPU frequency to MHz\n"; + +BAREBOX_CMD_START(cpufreq) + .cmd =3D do_cpufreq, + .usage =3D "adjust CPU frequency", + BAREBOX_CMD_HELP(cmd_cpufreq_help) +BAREBOX_CMD_END + diff --git a/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c b/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c new file mode 100644 index 0000000..982fc52 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c @@ -0,0 +1,88 @@ +#include +#include +#include +#include + +extern void exception_vectors(void); + +void __naked __flash_header_start go(void) +{ + barebox_arm_head(); +} + +/* + The Flash header is a data structure that the boot code reads from + Flash which provides information about the application. The Flash + header must be located at a known fixed address depending on the + type of external Flash device connected to i.MX25. The Flash header + is only required when an internal boot mode is selected from + BOOT_MODE[0:1]. The required offsets of the Flash header for each + device type are described in Table 7-10. + + NOR: 4 Kbyte =3D 0x1000 bytes + NAND: 1 Kbyte =3D 0x400 bytes + OneNAND: 256 bytes =3D 0x100 bytes + SD/eSD/MMC/eMMC: 1 kbyte =3D 0x400 bytes + I2C/CSPI EEPROM: 1 kbyte =3D 0x400 bytes + + The above flash header offsets are set accordingly in: + arch/arm/mach-imx/include/mach/imx-flash-header.h + + TEXT_BASE =3D 0x83F00000 + IMX_CS0_BASE =3D 0xA0000000 + #if INTERNAL_BOOT + DEST_BASE =3D IMX_CS0_BASE + #else + DEST_BASE =3D TEXT_BASE + #endif + FLASH_HEADER_BASE =3D (DEST_BASE + FLASH_HEADER_OFFSET) + */ + +struct imx_dcd_entry __dcd_entry_section dcd_entry[] =3D { + /* NOR flash, CS0_CSCRU, CS0_CSCRL, CS0_CSCRA */ + { .ptr_type =3D 4, .addr =3D 0xB8002000, .val =3D 0x0000D003, }, + { .ptr_type =3D 4, .addr =3D 0xB8002004, .val =3D 0x00330D01, }, + { .ptr_type =3D 4, .addr =3D 0xB8002008, .val =3D 0x00220800, }, + /* DDR2 init */ + { .ptr_type =3D 4, .addr =3D 0xb8001004, .val =3D 0x0076e83a, }, /* initi= al value for ESDCFG0 */ + { .ptr_type =3D 4, .addr =3D 0xb8001010, .val =3D 0x00000204, }, /* ESD_M= ISC */ + { .ptr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0x92210000, }, /* CS0 precharge command */ + { .ptr_type =3D 4, .addr =3D 0x80000f00, .val =3D 0x12344321, }, /* prech= arge all dummy write */ + { .ptr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0xb2210000, }, /* Load = Mode Register command */ + { .ptr_type =3D 1, .addr =3D 0x82000000, .val =3D 0xda, }, /* dummy wri= te Load EMR2 */ + { .ptr_type =3D 1, .addr =3D 0x83000000, .val =3D 0xda, }, /* dummy wri= te Load EMR3 */ + { .ptr_type =3D 1, .addr =3D 0x81000400, .val =3D 0xda, }, /* dummy wri= te Load EMR1; enable DLL */ + { .ptr_type =3D 1, .addr =3D 0x80000333, .val =3D 0xda, }, /* dummy wri= te Load MR; reset DLL */ + + { .ptr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0x92210000, }, /* CS0 precharge command */ + { .ptr_type =3D 4, .addr =3D 0x80000400, .val =3D 0x12345678, }, /* prech= arge all dummy write */ + { .ptr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0xA2210000, }, /* selec= t manual refresh mode */ + { .ptr_type =3D 4, .addr =3D 0x80000000, .val =3D 0x87654321, }, /* manua= l refresh */ + { .ptr_type =3D 4, .addr =3D 0x80000000, .val =3D 0x87654321, }, /* manua= l refresh twice */ + + { .ptr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0xb2210000, }, /* Load = Mode Register command */ + { .ptr_type =3D 1, .addr =3D 0x80000233, .val =3D 0xda, }, /* Load MR; = CL=3D3, BL=3D8, end DLL reset */ + { .ptr_type =3D 1, .addr =3D 0x81000780, .val =3D 0xda, }, /* Load EMR1= ; OCD default */ + { .ptr_type =3D 1, .addr =3D 0x81000400, .val =3D 0xda, }, /* Load EMR1= ; OCD exit */ + { .ptr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0x82216080, }, /* norma= l mode */ + /* IOMUX_SW_PAD setup */ + { .ptr_type =3D 4, .addr =3D 0x43FAC454, .val =3D 0x00001000, }, /* IOMUXC_SW_PAD_CTL_GRP_DDRTYPE(1-5) */ + { .ptr_type =3D 4, .addr =3D 0x43FAC448, .val =3D 0x00002000, }, /* IOMUXC_SW_PAD NFC voltage 1.8 */ + + /* CLKCTL */ + { .ptr_type =3D 4, .addr =3D 0x53f80008, .val =3D 0x20034000, }, /* CLKCT= L ARM=3D399 AHB=3D133 */ +}; + +struct imx_flash_header __flash_header_section flash_header =3D { + .app_code_jump_vector =3D DEST_BASE + ((unsigned int)&exception_vectors - TEXT_BASE), + .app_code_barker =3D APP_CODE_BARKER, + .app_code_csf =3D 0, /* non-secure boot (table 7-11) */ + .dcd_ptr_ptr =3D FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dc= d), + .super_root_key =3D 0, /* non-secure boot (table 7-11) */ + .dcd =3D FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker= ), + .app_dest =3D DEST_BASE, + .dcd_barker =3D DCD_BARKER, + .dcd_block_len =3D sizeof(dcd_entry), +}; + +unsigned long __image_len_section barebox_len =3D DCD_BAREBOX_SIZE; diff --git a/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c b/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c new file mode 100644 index 0000000..04ece36 --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c @@ -0,0 +1,188 @@ +/* + * + * (c) 2011 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_NAND_IMX_BOOT +static void __bare_init __naked insdram(void) +{ + uint32_t r; + + /* setup a stack to be able to call imx_nand_load_image() */ + r =3D STACK_BASE + STACK_SIZE - 12; + __asm__ __volatile__("mov sp, %0" : : "r"(r)); + + imx_nand_load_image((void *)TEXT_BASE, barebox_image_size); + + board_init_lowlevel_return(); +} +#endif + +/* Check 24.3.3.1 and 24.5.4.1.1 */ +static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl= , + uint32_t esdcfg) +{ + uint32_t esdctlreg =3D ESDCTL0; + uint32_t esdcfgreg =3D ESDCFG0; + + if (base =3D=3D 0x90000000) { + esdctlreg +=3D 8; + esdcfgreg +=3D 8; + } + + esdctl |=3D ESDCTL0_SDE; + + writel(esdcfg, esdcfgreg); + writel(esdctl | ESDCTL0_SMODE_PRECHARGE, esdctlreg); + writel(0, base + 1024); + writel(esdctl | ESDCTL0_SMODE_AUTO_REFRESH, esdctlreg); + readb(base); + readb(base); + writel(esdctl | ESDCTL0_SMODE_LOAD_MODE, esdctlreg); + writeb(0, base + 0x33); + writel(esdctl, esdctlreg); +} + +void __bare_init __naked board_init_lowlevel(void) +{ + uint32_t r; +#ifdef CONFIG_NAND_IMX_BOOT + unsigned int *trg, *src; +#endif + + /* restart the MPLL and wait until it's stable */ + writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27), + IMX_CCM_BASE + CCM_CCTL); + while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {}; + + /* Configure dividers and ARM clock source + * ARM @ 400 MHz + * AHB @ 133 MHz + */ + writel(0x20034000, IMX_CCM_BASE + CCM_CCTL); + + /* Set up 16bit NOR flash on WEIM CS0 */ + writel(0x0000D003, 0xB8002000); + writel(0x00330D01, 0xB8002004); + writel(0x00220800, 0xB8002008); + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good. + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, 0x43f00000); + writel(0x77777777, 0x43f00004); + writel(0x77777777, 0x53f00000); + writel(0x77777777, 0x53f00004); + + /* MAX (Multi-Layer AHB Crossbar Switch) setup + * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB + */ + writel(0x00043210, 0x43f04000); + writel(0x00043210, 0x43f04100); + writel(0x00043210, 0x43f04200); + writel(0x00043210, 0x43f04300); + writel(0x00043210, 0x43f04400); + /* SGPCR - always park on last master */ + writel(0x10, 0x43f04010); + writel(0x10, 0x43f04110); + writel(0x10, 0x43f04210); + writel(0x10, 0x43f04310); + writel(0x10, 0x43f04410); + /* MGPCR - restore default values */ + writel(0x0, 0x43f04800); + writel(0x0, 0x43f04900); + writel(0x0, 0x43f04a00); + writel(0x0, 0x43f04b00); + writel(0x0, 0x43f04c00); + + /* Configure M3IF registers + * M3IF Control Register (M3IFCTL) for MX25 + * MRRP[0] =3D LCDC on priority list (1 << 0) =3D 0x00000001 + * MRRP[1] =3D MAX1 not on priority list (0 << 1) =3D 0x00000000 + * MRRP[2] =3D MAX0 not on priority list (0 << 2) =3D 0x00000000 + * MRRP[3] =3D USB HOST not on priority list (0 << 3) =3D 0x00000000 + * MRRP[4] =3D SDMA not on priority list (0 << 4) =3D 0x00000000 + * MRRP[5] =3D SD/ATA/FEC not on priority list (0 << 5) =3D 0x00000000 + * MRRP[6] =3D SCMFBC not on priority list (0 << 6) =3D 0x00000000 + * MRRP[7] =3D CSI not on priority list (0 << 7) =3D 0x00000000 + * ---------- + * 0x00000001 + */ + writel(0x1, 0xb8003000); + + /* enable all the clocks */ + writel(0x1fffffff, IMX_CCM_BASE + CCM_CGCR0); + writel(0xffffffff, IMX_CCM_BASE + CCM_CGCR1); + writel(0x000fdfff, IMX_CCM_BASE + CCM_CGCR2); + + /* Set DDR2 and NFC group driver voltages */ + writel(0x1000, IMX_IOMUXC_BASE + 0x454); + writel(0x2000, IMX_IOMUXC_BASE + 0x448); + + /* Skip SDRAM initialization if we run from RAM */ + r =3D get_pc(); + if (r > 0x80000000 && r < 0x90000000) + board_init_lowlevel_return(); + + writel(ESDMISC_RST, ESDMISC); + + while (!(readl(ESDMISC) & (1 << 31))); + +#define ESDCTLVAL (ESDCTL0_ROW13 | ESDCTL0_COL9 | ESDCTL0_DSIZ_15_0 | \ + ESDCTL0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL) +#define ESDCFGVAL (ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 | ESDCFGx_tRAS_6 | \ + ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 | ESDCFGx_tRCD_3 | \ + ESDCFGx_tRC_9) + + setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL); + setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL); + +#ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r =3D get_pc(); + if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + board_init_lowlevel_return(); + + src =3D (unsigned int *)IMX_NFC_BASE; + trg =3D (unsigned int *)TEXT_BASE; + + /* Move ourselves out of NFC SRAM */ + for (i =3D 0; i < 0x800 / sizeof(int); i++) + *trg++ =3D *src++; + + /* Jump to SDRAM */ + r =3D (unsigned int)&insdram; + __asm__ __volatile__("mov pc, %0" : : "r"(r)); +#else + board_init_lowlevel_return(); +#endif +} diff --git a/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c new file mode 100644 index 0000000..239d72a --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c @@ -0,0 +1,377 @@ +/* + * (C) 2012 FQ Ingenieria, Roberto Nibali + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The currently used MOSFET IRLMLL6402 needs + 3.3V driver voltage to function, however the + basic GPIO driver voltage is 1.8V, which is + not sufficient, unless the MOSFET switches + starting from VGS > 1.5V. + */ +#define MX25_PAD_CS1__GPIO_4_3_DVS IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL | PAD_CTL_DVS) + +static struct fec_platform_data fec_info =3D { + .xcv_type =3D RMII, + .phy_addr =3D 1, +}; + +#ifdef CONFIG_USB +static void imx25_usb_init(void) +{ + uint32_t reg; + + /* Host 1 */ + reg =3D readl(IMX_OTG_BASE + 0x600); + reg &=3D ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | + MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); + reg |=3D (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT; + reg |=3D MX35_H1_USBTE_BIT; + reg |=3D MX35_H1_IPPUE_DOWN_BIT; + writel(reg, IMX_OTG_BASE + 0x600); + + reg =3D readl(IMX_OTG_BASE + 0x584); + reg |=3D 3 << 30; + writel(reg, IMX_OTG_BASE + 0x584); + + /* Set to Host mode */ + reg =3D readl(IMX_OTG_BASE + 0x5a8); + writel(reg | 0x3, IMX_OTG_BASE + 0x5a8); +} +#endif + +/* +static struct at24_platform_data board_eeprom =3D { + .byte_len =3D 65536, + .page_size =3D 128, + .flags =3D AT24_FLAG_ADDR16, +}; +*/ + +static struct i2c_board_info i2c_devices[] =3D { + { + I2C_BOARD_INFO("at24", 0x50), + //.platform_data =3D &board_eeprom, + }, +}; + +#if 0 +struct gpio_led noah_leds[] =3D { + { + .led =3D { .name =3D "GPIO-LED", }, + .gpio =3D IMX_GPIO_NR(4, 10), + .active_low =3D 1, + }, +}; + +static void noah_leds_init(void) +{ + int i; + for (i =3D 0; i < ARRAY_SIZE(noah_leds); i++) + led_gpio_register(&noah_leds[i]); +} +#endif + +#define MX25_NOAH_BOOT_UNKNOWN 0 +#define MX25_NOAH_BOOT_NOR 1 +#define MX25_NOAH_BOOT_MMC 2 +static int noah_read_ccm_regs(void) { + uint32_t reg; + + /* 15.3.3.12 CCM Reset and Debug Register (CRDR) + */ + reg =3D readl(IMX_CCM_BASE + CCM_CRDR); + printf("%s: CCM CRDR =3D %08X\n", __func__, reg); + + /* 15.3.3.11 CCM Status Register (RCSR) + if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14)) + nand_info.width =3D 2; + */ + reg =3D readl(IMX_CCM_BASE + CCM_RCSR); + printf("%s: CCM RCSR =3D %08X\n", __func__, reg); + if ((reg & (0x3 << 30)) =3D=3D 0x3 << 30) { + printf("%s: Booting from expansion device: ", __func__); + if ((reg & (0x3 << 28)) =3D=3D 0x0 << 28) { + printf("SD/MMC\n"); + return MX25_NOAH_BOOT_MMC; + } else { + printf("unknown\n"); + } + } else if ((reg & (0x3 << 30)) =3D=3D 0x0 << 30) { + printf("%s: Booting from WEIM: ", __func__); + if ((reg & (0x3 << 28)) =3D=3D 0x0 << 28) { + printf("NOR\n"); + return MX25_NOAH_BOOT_NOR; + } else { + printf("unknown\n"); + } + } + + return MX25_NOAH_BOOT_UNKNOWN; +} + +#ifdef CONFIG_DRIVER_VIDEO_IMX +static struct imx_fb_videomode imxfb_mode =3D { + .mode =3D { + .name =3D "Chunghwa CLAA057VA01CT", + .refresh =3D 60, + .xres =3D 640, + .yres =3D 480, + .pixclock =3D KHZ2PICOS(25600), + .left_margin =3D 46, + .right_margin =3D 114, + .upper_margin =3D 34, + .lower_margin =3D 11, + .hsync_len =3D 48, + .vsync_len =3D 3, + }, + .bpp =3D 16, + .pcr =3D 0xFA000080, /* 16bpp: Check 33.3.10 of the IMX25RM: LPCR */ +}; + +static struct imx_fb_platform_data noah_fb_data =3D { + .mode =3D &imxfb_mode, + .num_modes =3D 1, + .pwmr =3D 0x00A903FF, + .lscr1 =3D 0x00120300, + .dmacr =3D 0x00020010, +}; +#endif + +static iomux_v3_cfg_t imx25_pads[] =3D { + /* FEC RMII */ + MX25_PAD_FEC_MDC__FEC_MDC, /* Management data clock */ + MX25_PAD_FEC_MDIO__FEC_MDIO, /* Management data input/output *= / + MX25_PAD_FEC_TX_EN__FEC_TX_EN, /* Transmit enable */ + MX25_PAD_FEC_RX_DV__FEC_RX_DV, /* Carrier sense / receive data valid */ + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, /* Synchronous clock reference (REF_CLK) */ + MX25_PAD_UART2_CTS__FEC_RX_ER, /* Receive error */ + MX25_PAD_FEC_RDATA0__FEC_RDATA0, /* Receive data */ + MX25_PAD_FEC_RDATA1__FEC_RDATA1, /* Receive data */ + MX25_PAD_FEC_TDATA0__FEC_TDATA0, /* Transmit data */ + MX25_PAD_FEC_TDATA1__FEC_TDATA1, /* Transmit data */ +#ifdef CONFIG_DRIVER_SERIAL_IMX + /* UART1 */ + MX25_PAD_UART1_RXD__UART1_RXD, + MX25_PAD_UART1_TXD__UART1_TXD, + MX25_PAD_UART1_RTS__UART1_RTS, + MX25_PAD_UART1_CTS__UART1_CTS, +#endif +#ifdef CONFIG_USB + /* USBH2 */ + MX25_PAD_D9__USBH2_PWR, + MX25_PAD_D8__USBH2_OC, + MX25_PAD_LD0__USBH2_CLK, + MX25_PAD_LD1__USBH2_DIR, + MX25_PAD_LD2__USBH2_STP, + MX25_PAD_LD3__USBH2_NXT, + MX25_PAD_LD4__USBH2_DATA0, + MX25_PAD_LD5__USBH2_DATA1, + MX25_PAD_LD6__USBH2_DATA2, + MX25_PAD_LD7__USBH2_DATA3, + MX25_PAD_HSYNC__USBH2_DATA4, + MX25_PAD_VSYNC__USBH2_DATA5, + MX25_PAD_LSCLK__USBH2_DATA6, + MX25_PAD_OE_ACD__USBH2_DATA7, +#endif + /* I2C1 */ + MX25_PAD_I2C1_CLK__I2C1_CLK, + MX25_PAD_I2C1_DAT__I2C1_DAT, + /* ESDHC */ + /* + MX25_PAD_SD1_CMD__SD1_CMD_NPU, + MX25_PAD_SD1_CLK__SD1_CLK_NPU, + MX25_PAD_SD1_DATA0__SD1_DATA0_NPU, + MX25_PAD_SD1_DATA1__SD1_DATA1_NPU, + MX25_PAD_SD1_DATA2__SD1_DATA2_NPU, + MX25_PAD_SD1_DATA3__SD1_DATA3_NPU, + */ +#ifdef CONFIG_DRIVER_VIDEO_IMX + /* LCD */ + MX25_PAD_LD0__LD0, /* TFT[19]: Blue[0] (LSB)*/ + MX25_PAD_LD1__LD1, /* TFT[18]: Blue[1] */ + MX25_PAD_LD2__LD2, /* TFT[17]: Blue[2] */ + MX25_PAD_LD3__LD3, /* TFT[15]: Blue[3] */ + MX25_PAD_LD4__LD4, /* TFT[14]: Blue[4] */ + MX25_PAD_LD5__LD5, /* TFT[13]: Blue[5] (MSB) */ + MX25_PAD_LD6__LD6, /* TFT[27]: Green[0] (LSB) */ + MX25_PAD_LD7__LD7, /* TFT[26]: Green[1] */ + MX25_PAD_LD8__LD8, /* TFT[25]: Green[2] */ + MX25_PAD_LD9__LD9, /* TFT[23]: Green[3] */ + MX25_PAD_LD10__LD10, /* TFT[22]: Green[4] */ + MX25_PAD_LD11__LD11, /* TFT[21]: Green[5] (MSB) */ + MX25_PAD_LD12__LD12, /* TFT[35]: Red[0] (LSB) */ + MX25_PAD_LD13__LD13, /* TFT[34]: Red[1] */ + MX25_PAD_LD14__LD14, /* TFT[33]: Red[2] */ + MX25_PAD_LD15__LD15, /* TFT[31]: Red[3] */ + MX25_PAD_GPIO_E__LD16, /* TFT[30]: Red[4] */ + MX25_PAD_GPIO_F__LD17, /* TFT[29]: Red[5] (MSB) */ + MX25_PAD_HSYNC__GPIO_1_22, /* TFT[ 3]: LCD_HSYNC */ + MX25_PAD_VSYNC__GPIO_1_23, /* TFT[ 8]: LCD_VSYNC */ + MX25_PAD_LSCLK__LSCLK, /* TFT[38]: LCD_LSCLK */ + MX25_PAD_OE_ACD__OE_ACD, /* TFT[ 9]: LCD_DRDY */ + MX25_PAD_CONTRAST__PWM4_PWMO, /* TFT[12]: LCD backlight (PWM): */ + MX25_PAD_CS1__GPIO_4_3_DVS, /* TFT[xx]: LCD_EN */ + MX25_PAD_EB1__GPIO_2_13, /* TFT[ 1]: LCD_UP_DOWN */ + MX25_PAD_BCLK__GPIO_4_4, /* TFT[40]: LCD_LEFT_RIGHT */ + MX25_PAD_CSI_D4__GPIO_1_29, /* TFT[ 2]: LCD_DMS */ +#endif +}; + +static int noah_fec_init(void) +{ + /* + * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. + * Assert FEC_RESET_B, then power up the PHY by asserting + * FEC_ENABLE, at the same time lifting FEC_RESET_B. + * + * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17 + * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12 + */ + writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */ + writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */ + +#define FEC_ENABLE_GPIO 35 +#define FEC_RESET_B_GPIO 104 + + /* make the pins output */ + gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */ + gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */ + udelay(2); + + /* turn on power & lift reset */ + gpio_set_value(FEC_ENABLE_GPIO, 1); + gpio_set_value(FEC_RESET_B_GPIO, 1); + + return 0; +} +late_initcall(noah_fec_init); + +static int imx25_mem_init(void) +{ + /* add memory bank to 0x80000000 (barebox_add_memory_bank()) */ + arm_add_mem_device("ram0", IMX_SDRAM_CS0, 64 * 1024 * 1024); + + return 0; +} +mem_initcall(imx25_mem_init); + +static int imx25_devices_init(void) +{ + int bootdev; + + bootdev =3D noah_read_ccm_regs(); + mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZE(imx25_pads)); + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + imx25_add_i2c0(NULL); + imx25_add_mmc0(NULL); + imx25_iim_register_fec_ethaddr(); + imx25_add_fec(&fec_info); + + printf("%s: Adding NOR flash device\n", __func__); + /* Configure 16 bit nor flash on WEIM cs0 */ + imx25_setup_weimcs(0, 0x0000D003, 0x00330D01, 0x00220800); + /* NOR flash starts at CS0 addr 0xA0000000, set to 64MB */ + add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, SZ_64M, 0); + printf("%s: Adding initial NOR flash partitions\n", __func__); + devfs_add_partition("nor0", 0x00000, SZ_512K, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", SZ_512K, SZ_512K, PARTITION_FIXED, "env0"); + //protect_file("/dev/env0", 1); +#ifdef CONFIG_USB + imx25_usb_init(); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); +#endif +#ifdef CONFIG_DRIVER_VIDEO_IMX + //imx25_add_fb(&noah_fb_data); +#endif + //noah_leds_init(); + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_MX25_3DS); + armlinux_set_serial(imx_uid()); + + return 0; +} +device_initcall(imx25_devices_init); + +static int imx25_console_init(void) +{ + //imx25_init_lowlevel(800) + imx25_core_setup(); + imx25_add_uart0(); + return 0; +} +console_initcall(imx25_console_init); + +/*=C2=AC=E2=80=A0Check arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c + for more information, especially with regard to low_level + setup inside the core_setup part. +*/ +static int imx25_core_setup(void) +{ + uint32_t reg; + /* Enable clocks: + UART1: 15 + FEC : 23 + SDHC1: 3/21 + USB : 28 + I2C : 6 + */ + reg =3D readl(IMX_CCM_BASE + CCM_CGCR0); + reg |=3D (1 << 6) | (1 << 23) | (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28); + reg =3D writel(reg, IMX_CCM_BASE + CCM_CGCR0); + + reg =3D readl(IMX_CCM_BASE + CCM_CGCR1); + reg |=3D (1 << 23) | (1 << 15) | (1 << 13); + reg =3D writel(reg, IMX_CCM_BASE + CCM_CGCR1); + + reg =3D readl(IMX_CCM_BASE + CCM_CGCR2); + reg |=3D (1 << 14); + reg =3D writel(reg, IMX_CCM_BASE + CCM_CGCR2); + /* CCM clocks: PER_12 -- PER_15 (15.3.3.10) */ + //writel(0x03010101, IMX_CCM_BASE + CCM_PCDR3); + /* CCM clocks: PER_8 -- PER_11 (15.3.3.9) */ + //writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2); + return 0; + +} +core_initcall(imx25_core_setup); diff --git a/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.dox b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.dox new file mode 100644 index 0000000..8b0e28a --- /dev/null +++ b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.dox @@ -0,0 +1,79 @@ +/** @page SID1 (FQ=C2=AC=E2=80=A0Ingenier=E2=88=9A=E2=89=A0a) + +This device is also known as "NOAH" (http://www.fqingenieria.es/) + +This CPU card is based on a Freescale i.MX25 CPU. The card is shipped with= : + +- 64 MiB synchronous dynamic RAM (DDR type) +- 4=C2=AC=E2=80=A0SIM/SAM=C2=AC=E2=80=A0sockets +- USB OTG +- ... + +Memory layout when @b barebox is running: + +- 0x80000000 start of SDRAM (IMX_SDRAM_CS0) +- 0x80000100 start of kernel's boot parameters + - below malloc area: stack area + - below barebox: malloc area +- 0x82000000 start of @b barebox + +@section get_sid1_noah_binary How to get the bootloader binary image: + +Using the default configuration: + +@verbatim +make ARCH=3Darm noah_defconfig +@endverbatim + +Build the bootloader binary image: + +@verbatim +make ARCH=3Darm CROSS_COMPILE=3Darmv5compiler +@endverbatim + +@note replace the armv5compiler with your ARM v5 cross compiler. + +@section setup_falconwing How to prepare an MCI card to boot the "chumby one" with barebox + +- Create four primary partitions on the SD=C2=AC=E2=80=A0card + - the second one for the persistant environment (512 kiB, at least 256k) + - the third one for the kernel (3 MiB ... 4 MiB in size) + - the fourth one for the root filesystem which can fill the rest of the available space + +- Copy the default @b barebox environment into the second partition (no filesystem required). + +- Copy the kernel into the third partition (no filesystem required). + +- Create the root filesystem in the 4th partition. You may copy an image into this + partition or you can do it in the classic way: mkfs on it, mount it and copy + all required data and programs into it. + +@section gpio_falconwing Available GPIOs + +The SID1 NOAH=C2=AC=E2=80=A0uses some GPIOs to control various features. W= ith the regular +GPIO commands these features can be controlled at @a barebox's runtime. + + + + + + + + + + + + + + + + + + + + + + + +
NoDirectionFunctionResetSet
60OutputDisplay BacklightBacklight
Off		Backlight
On (100 %)
62InputBendNot pressedPressed
+*/ diff --git a/arch/arm/configs/noah_defconfig b/arch/arm/configs/noah_defconfig new file mode 100644 index 0000000..152f0bf --- /dev/null +++ b/arch/arm/configs/noah_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARCH_IMX=3Dy +CONFIG_ARCH_IMX_EXTERNAL_BOOT=3Dy +CONFIG_ARCH_IMX25=3Dy +CONFIG_MACH_MX25_NOAH=3Dy +CONFIG_IMX_CLKO=3Dy +CONFIG_IMX_IIM=3Dy +CONFIG_AEABI=3Dy +CONFIG_ARM_UNWIND=3Dy +CONFIG_MMU=3Dy +CONFIG_BROKEN=3Dy +CONFIG_EXPERIMENTAL=3Dy +CONFIG_PROMPT=3D"sid1-noah:" +CONFIG_LONGHELP=3Dy +CONFIG_GLOB=3Dy +CONFIG_CMDLINE_EDITING=3Dy +CONFIG_AUTO_COMPLETE=3Dy +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=3Dy +CONFIG_DEFAULT_ENVIRONMENT_PATH=3D"arch/arm/boards/fq-sid1-mx25-noah/env" +CONFIG_BAREBOXENV_TARGET=3Dy +CONFIG_ENABLE_FLASH_NOISE=3Dy +CONFIG_ENABLE_PARTITION_NOISE=3Dy +CONFIG_ENABLE_DEVICE_NOISE=3Dy +CONFIG_CMD_EDIT=3Dy +CONFIG_CMD_SLEEP=3Dy +CONFIG_CMD_SAVEENV=3Dy +CONFIG_CMD_EXPORT=3Dy +CONFIG_CMD_PRINTENV=3Dy +CONFIG_CMD_READLINE=3Dy +CONFIG_CMD_TIME=3Dy +CONFIG_CMD_AUTOMOUNT=3Dy +CONFIG_CMD_ECHO_E=3Dy +CONFIG_CMD_LOADB=3Dy +CONFIG_CMD_LOADY=3Dy +CONFIG_CMD_LOADS=3Dy +CONFIG_CMD_SAVES=3Dy +CONFIG_CMD_MEMINFO=3Dy +CONFIG_CMD_IOMEM=3Dy +CONFIG_CMD_MD5SUM=3Dy +CONFIG_CMD_SHA1SUM=3Dy +CONFIG_CMD_SHA256SUM=3Dy +CONFIG_CMD_SHA224SUM=3Dy +CONFIG_CMD_MTEST=3Dy +CONFIG_CMD_MTEST_ALTERNATIVE=3Dy +CONFIG_CMD_FLASH=3Dy +CONFIG_CMD_BOOTM_SHOW_TYPE=3Dy +CONFIG_CMD_BOOTM_VERBOSE=3Dy +CONFIG_CMD_BOOTM_INITRD=3Dy +CONFIG_CMD_BOOTM_OFTREE=3Dy +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=3Dy +CONFIG_CMD_UIMAGE=3Dy +CONFIG_CMD_RESET=3Dy +CONFIG_CMD_GO=3Dy +CONFIG_CMD_OFTREE=3Dy +CONFIG_CMD_TIMEOUT=3Dy +CONFIG_CMD_PARTITION=3Dy +CONFIG_CMD_MAGICVAR=3Dy +CONFIG_CMD_MAGICVAR_HELP=3Dy +CONFIG_CMD_BMP=3Dy +CONFIG_CMD_GPIO=3Dy +CONFIG_CMD_UNCOMPRESS=3Dy +CONFIG_CMD_I2C=3Dy +CONFIG_CMD_LED=3Dy +CONFIG_NET=3Dy +CONFIG_NET_DHCP=3Dy +CONFIG_NET_NFS=3Dy +CONFIG_NET_PING=3Dy +CONFIG_NET_TFTP=3Dy +CONFIG_NET_TFTP_PUSH=3Dy +CONFIG_NET_NETCONSOLE=3Dy +CONFIG_NET_RESOLV=3Dy +CONFIG_DRIVER_NET_FEC_IMX=3Dy +CONFIG_DRIVER_SPI_IMX=3Dy +CONFIG_I2C=3Dy +CONFIG_I2C_IMX=3Dy +CONFIG_DRIVER_CFI=3Dy +# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set +# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set +CONFIG_MTD=3Dy +CONFIG_USB=3Dy +CONFIG_USB_EHCI=3Dy +CONFIG_USB_OHCI=3Dy +CONFIG_USB_STORAGE=3Dy +CONFIG_VIDEO=3Dy +CONFIG_DRIVER_VIDEO_IMX=3Dy +CONFIG_MCI=3Dy +CONFIG_MCI_STARTUP=3Dy +CONFIG_MCI_IMX_ESDHC=3Dy +CONFIG_LED=3Dy +CONFIG_LED_GPIO=3Dy +CONFIG_EEPROM_AT25=3Dy +CONFIG_FS_CRAMFS=3Dy +CONFIG_FS_TFTP=3Dy +CONFIG_FS_FAT=3Dy +CONFIG_FS_FAT_WRITE=3Dy +CONFIG_FS_FAT_LFN=3Dy +CONFIG_BZLIB=3Dy +CONFIG_LZO_DECOMPRESS=3Dy diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3236762..839de09 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -23,6 +23,7 @@ config ARCH_TEXT_BASE default 0x7ff00000 if MACH_MX53_SMD default 0x87f00000 if MACH_GUF_CUPID default 0x93d00000 if MACH_TX25 + default 0x83f00000 if MACH_MX25_NOAH default 0x7ff00000 if MACH_TQMA53 default 0x97f00000 if MACH_TX51 default 0x4fc00000 if MACH_MX6Q_ARM2 @@ -47,6 +48,7 @@ config BOARDINFO default "Freescale i.MX53 SMD" if MACH_FREESCALE_MX53_SMD default "Garz+Fricke Cupid" if MACH_GUF_CUPID default "Ka-Ro tx25" if MACH_TX25 + default "SID1 NOAH" if MACH_MX25_NOAH default "TQ tqma53" if MACH_TQMA53 default "Ka-Ro tx51" if MACH_TX51 default "Freescale i.MX6q armadillo2" if MACH_MX6Q_ARM2 @@ -251,6 +253,12 @@ config MACH_TX25 help Say Y here if you are using the Ka-Ro tx25 board +config MACH_MX25_NOAH + bool "SID1 NOAH" + select MACH_HAS_LOWLEVEL_INIT + help + Say Y here if you are using the SID1 NOAH board + endchoice endif diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h index 73307c4..8225832 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -72,6 +72,7 @@ #define CCM_LTR1 0x44 #define CCM_LTR2 0x48 #define CCM_LTR3 0x4c +#define CCM_MCR 0x64 #define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) #define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) @@ -107,6 +108,22 @@ #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) +/* Chip Select Registers */ +#define IMX_WEIM_BASE WEIM_BASE +#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x Upper Register */ +#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x Lower Register */ +#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */ +#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */ + +#ifndef __ASSEMBLY__ +static inline void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional) +{ + CSxU(cs) =3D upper; + CSxL(cs) =3D lower; + CSxA(cs) =3D addional; +} +#endif /* __ASSEMBLY__ */ + /* * Definitions for the clocksource driver * Thanks and best regards Roberto --e89a8f3ba4b92fb4b004c12a1c34 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable ADDENDUM:

=
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 { .ptr_type =3D 4, .addr =3D 0xB80020= 00, .val =3D 0x0000D003, },
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 { .ptr_type =3D 4, .addr =3D 0xB8002004, .= val =3D 0x00330D01, },
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 { .ptr_type =3D 4, .addr =3D 0xB8002008, .= val =3D 0x00220800, },

Do these values match the ones you read out of the registers using yo= ur
U-Boot?

Yep, the corresponing dcd= header.S entries:

DCDGEN( 1, 4, 0xB8002000, 0= x0000D003) /* CS0_CSCRU */
DCDGEN( 2, 4, 0xB8002004, 0x00330d01) = /* CS0_CSCRL */
DCDGEN( 3, 4, 0xB8002008, 0x00220800) /* CS0_CSCRA */
=
So I reckon at least I got this part working fine.

> /* Set up 16bit NOR flash on WEIM CS0 */
> writel(0xB8002000, 0x0000D003);
> =C2=A0writel(0xB8002004, 0x00330D01);
> writel(0xB8002008, 0x00220800);

You mixed up the argument order.

Yikes!!!! I hope I didn't fry so= mething. I'll quickly try the reversed order and report back.

It does not change the fact that it stil= l does not recognize my NOR. I am at my wits' end here, so I go along p= osting my patch to support the mx25 based device for review:

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d0bfd71..483b47e 100644
--- a/arch/arm/Makefile
=
+++ b/arch/arm/Makefile
@@ -133,6 +133,7 @@ board-$(CONFIG_M= ACH_TX25) :=3D karo-tx25
=C2=A0board-$(CONFIG_MACH_TQMA53) :=3D tqma53
=C2=A0board-$(CONFIG_M= ACH_TX51) :=3D karo-tx51
=C2=A0board-$(CONFIG_MACH_MX6Q_ARM2) :=3D freescale-mx6-arm2
+board-$= (CONFIG_MACH_MX25_NOAH) :=3D fq-sid1-mx25-noah
=C2=A0
=C2=A0machdirs :=3D $(patsubst %,arch/arm/mach-%/,$(m= achine-y))
=C2=A0
diff --git a/arch/arm/boards/fq-sid1-= mx25-noah/Makefile b/arch/arm/boards/fq-sid1-mx25-noah/Makefile
n= ew file mode 100644
index 0000000..1e9cd54
--- /dev/null
+++ b/arch/ar= m/boards/fq-sid1-mx25-noah/Makefile
@@ -0,0 +1,26 @@
+#=
+# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
+#
+# See file CREDITS for list of people who contributed to= this
+# project.
+#
+# This program is free = software; you can redistribute it and/or
+# modify it under the t= erms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,=
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =C2=A0See the=
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+obj-y +=3D lowlevel.o
+obj-y = +=3D sid1_noah.o
+obj-y +=3D extra_commands.o
+obj-$(CONFIG_ARCH_IMX_INTERNAL_BOOT)<= span class=3D"Apple-tab-span" style=3D"white-space:pre"> +=3D flash_= header.o
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/config.h b/arch/arm/boa= rds/fq-sid1-mx25-noah/config.h
new file mode 100644
ind= ex 0000000..f35e8a0
--- /dev/null
+++ b/arch/arm/boards= /fq-sid1-mx25-noah/config.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007 Juerge= n Beisert <jbe@pengutronix.de&= gt;
+ *
+ * This program is free software; you can redi= stribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be u= seful,
+ * but WITHOUT ANY WARRANTY; without even the implied war= ranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.= =C2=A0See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ = * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_= H
+#define __CONFIG_H
+
+/*
+ * Def= initions related to passing arguments to kernel.
+ */
+
+#define CONFIG_MX25_HCLK_FREQ 24000000
+<= /div>
+#endif
+
+/* nothing to do here yet */
=
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/_update b/arch/arm/b= oards/fq-sid1-mx25-noah/env/bin/_update
new file mode 100644
index 0000000..014bce3
--- /dev/null
+++ b/arch/a= rm/boards/fq-sid1-mx25-noah/env/bin/_update
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+if [ -z &= quot;$part" -o -z "$image" ]; then
+ echo "define \$part= and \$image"
+ exit= 1
+fi
+
+if [ ! -e "$part" ]; then=
+ echo "Partition $part does not exist"
+ exit= 1
+fi
+
+if [ $# =3D 1 ]; then
+ image=3D$1
+fi
+
+if [ x$ip =3D xdhcp ]; then
+ dhcp
+fi<= /div>
+
+ping $eth0.serverip
+if [ $? -ne 0 ] ; the= n
+ echo= "update aborted"
+ exit 1
+fi
+
+un= protect $part
+
+echo
+echo "erasing partition $part"<= /div>
+erase $part
+
+echo
+echo "fl= ashing $image to $part"
+echo
+tftp $image $part
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/boot b/arch/arm= /boards/fq-sid1-mx25-noah/env/bin/boot
new file mode 100644
=
index 0000000..d06fc16
--- /dev/null
+++ b/arch/ar= m/boards/fq-sid1-mx25-noah/env/bin/boot
@@ -0,0 +1,38 @@
+#!/bin/sh
+
+. /env/co= nfig
+
+if [ x$1 !=3D x ]; then
+ boot=3D$1
+= kernel=3D$= 1
+fi
+
+if [ x$boot =3D xnor ]; then
+ bootargs=3D&q= uot;$bootargs root=3D$nor_rootpart rootfstype=3Djffs2"
+elif= [ x$boot =3D xmmc ]; then
+ boot= args=3D"$bootargs root=3D$mmc_rootpart rootfstype=3Dext3"
+elif [ x$boot =3D xnfs ]; then
+ bootargs=3D"$bootargs root=3D/dev/= nfs nfsroot=3D$eth0.serverip:$nfsroot,v3,tcp"
+ if [= x$getip =3D xdhcp ]; then
+ bootargs=3D"$bootargs ip=3Ddhcp"
+ e= lse
+ boo= targs=3D"$bootargs ip=3D$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth= 0.netmask:::"
+ fi
+fi
+
+# Generally add mtdparts to kernel cmdline<= /div>
+bootargs=3D"$bootargs mtdparts=3Dphysmap-flash.0:$nor_parts= "
+
+if [ x$kernel =3D xtftp -o x$kernel =3D xnfs = ]; then
+ if [= x$getip =3D xdhcp ]; then
+ echo "BOOT: Fetching IP address from $et= h0.serverip"
+ dhc= p
+ fi
+ = tftp $tftp_uimage uImage || exit 1
+ boot= m uImage
+elif [ x$kernel =3D xmmc ]; then
+ bootm $mmc_kernel
+elif [ x$kernel =3D xnor ]; then
+ bootm /dev/nor0.kernel
+fi
+
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/i= nit b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init
new file mode 100644
index 0000000..070220d
--- /d= ev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/init
@@ -0,0 +1,23 @@
+#!/bin/sh
+
+PATH=3D/= env/bin
+export PATH
+
+. /env/config
+
+if [ -e /dev/nor0 ]; then
+ addpart /dev/nor0 $nor_parts
+fi
+
+echo
+echo -n "Hit any key to stop autoboo= t: "
+timeout -a $autoboot_timeout
+if [ $? !=3D 0= ]; then
+ echo
+ echo= "type update_kernel nor [<imagename>] to update kernel into fla= sh"
+ echo "type update_root nor [<imagename>] to update roo= tfs into flash"
+ echo=
+ exit
+fi
+
+boot
diff --git a/arc= h/arm/boards/fq-sid1-mx25-noah/env/bin/update_kernel b/arch/arm/boards/fq-s= id1-mx25-noah/env/bin/update_kernel
new file mode 100644
index 0000000..49523aa
--- /d= ev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_ke= rnel
@@ -0,0 +1,13 @@
+#!/bin/sh
+
+. /env/config
+
+image=3D$uimage
+if [ x$1 = =3D xnor ]; then
+ part=3D/dev/nor0.kernel
+else
+ echo "usage= : $0 nor [imagename]"
+ exit= 1
+fi
+
+. /env/bin/_update $2
dif= f --git a/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_root b/arch/arm/= boards/fq-sid1-mx25-noah/env/bin/update_root
new file mode 100644
index 0000000..0935bc1
--- /d= ev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/env/bin/update_ro= ot
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+. /env/config
+
+image=3D$uimage
+if [ x$1 = =3D xnand ]; then
+ part=3D/dev/nand0.root.= bb
+elif [ x$1 =3D xnor ]; then
+ part=3D/dev/nor0.root
+else
+ e= cho "usage: $0 nor [imagename]"
+ exit= 1
+fi
+
+. /env/bin/_update $2
+
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/env/config b/arch/a= rm/boards/fq-sid1-mx25-noah/env/config
new file mode 100644
index 0000000..240056d
--- /d= ev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/env/config
<= div>@@ -0,0 +1,25 @@
+#!/bin/sh
+
+autoboot_t= imeout=3D5
+
+# can be either 'nfs', 'tftp', 'nor&#= 39;, or 'mmc'
+kernel=3Dtftp
+root=3Dmmc
<= div>+
+version=3D/v2.1.8-rc
+tftp_uimage=3D$version/uIm= age
+tftp_jffs2=3D$version/console-image.jffs2
+bootargs=3D"= ;console=3Dttymxc0,115200"
+nfsroot=3D"/home/develop/SI= D1/nfsroot"
+nor_parts=3D"512k(barebox)ro,512k(bareboxe= nv),3072k(kernel),-(root)"
+nor_rootpart=3D"/dev/mtdblock3"
+mmc_kernel=3D&qu= ot;/dev/mmcblk0p1"
+mmc_rootpart=3D"/dev/mmcblk0p2"= ;
+getip=3Ddhcp
+
+# or set your networking p= arameters here
+#eth0.ipaddr=3D192.168.1.80
+#eth0.netmask=3D255.255.255.0<= /div>
+#eth0.gateway=3Da.b.c.d
+eth0.serverip=3D192.168.1.23<= /div>
+eth0.ethaddr=3D00:50:c2:8c:e6:0e
diff --git a/arch/arm= /boards/fq-sid1-mx25-noah/extra_commands.c b/arch/arm/boards/fq-sid1-mx25-n= oah/extra_commands.c
new file mode 100644
index 0000000..e57c61f
--- /d= ev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/extra_commands.c<= /div>
@@ -0,0 +1,66 @@
+/*
+ * (C) 2012 FQ Ingenier= ia, Roberto Nibali <rnibali@gmail.c= om>
+ *
+ * This program is free software; you can redistribute = it and/or
+ * modify it under the terms of the GNU General Public= License as
+ * published by the Free Software Foundation; either= version 2 of
+ * the License, or (at your option) any later version.
+ *<= /div>
+ * This program is distributed in the hope that it will be usefu= l,
+ * but WITHOUT ANY WARRANTY; without even the implied warrant= y of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =C2=A0See the=
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public Lice= nse
+ * along with this program; if not, write to the Free Software
<= div>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *= MA 02111-1307 USA
+ *
+ */
+
+#include <io.h>
+#include <common.h>
+#include <command.h>
=
+#include <mach/imx-regs.h>
+#include <mach/imx-pll= .h>
+
+#define MPCTL_PARAM_399 =C2=A0 =C2=A0 (IMX_PL= L_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
+#define MPCTL_PARAM_532 =C2=A0 =C2=A0 ((1 << 31) | IMX_PLL_PD(0= ) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
+
+static int do_cpufreq(int argc, char *argv[])
+{
+<= span class=3D"Apple-tab-span" style=3D"white-space:pre"> /* 15.3.3.1= Core PLL (= MPLL) Control Register (MPCTL) */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0unsigned long freq;
+
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0if (argc !=3D 2)
+ =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return COMMAND_ERROR_USAGE;
<= div>+
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0freq =3D simple_strtoul(argv[1= ], NULL, 0);
+
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0switch (freq) {
+ =C2=A0 =C2=A0= =C2=A0 =C2=A0case 399:
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0case 532:
+ =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0writel(MPCTL_PARAM_532, IMX_CCM_BASE + CC= M_MPCTL);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
<= div>+ =C2=A0 =C2=A0 =C2=A0 =C2=A0default:
+ =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return COMMAND_ERROR_USAGE;
+ = =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+ =C2=A0 =C2=A0 =C2=A0 = =C2=A0printf("Switched CPU frequency to %ldMHz\n", freq);
+
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
+}
<= div>+
+static const __maybe_unused char cmd_cpufreq_help[] =3D
+"Usage: cpufreq 399|532\n"
+"\n"
+"Set CPU frequency to <freq> MHz\n";
+
+BAREBOX_CMD_START(cpufreq)
+ .cmd =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0=3D do_cpufreq,
+ .usage =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =3D "adjust CPU frequency",
+ BARE= BOX_CMD_HELP(cmd_cpufreq_help)
+BAREBOX_CMD_END
+
=
diff --git a/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c b/arch/a= rm/boards/fq-sid1-mx25-noah/flash_header.c
new file mode 100644
index 0000000..982fc52
--- /d= ev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/flash_header.c
@@ -0,0 +1,88 @@
+#include <common.h>
+#include <mach/imx-flash-header.h>
+#include <mach/imx-= regs.h>
+#include <asm/barebox-arm-head.h>
+
+extern void exception_vectors(void);
+
+void = __naked __flash_header_start go(void)
+{
+ barebox_arm_head();
+}
+
+/*
+ =C2=A0 The Flash header is a data structure that the boot code reads f= rom
+ =C2=A0 Flash which provides information about the application. The F= lash
+ =C2=A0 header must be located at a known fixed address dep= ending on the
+ =C2=A0 type of external Flash device connected to= i.MX25. The Flash header
+ =C2=A0 is only required when an internal boot mode is selected from<= /div>
+ =C2=A0 BOOT_MODE[0:1]. The required offsets of the Flash header= for each
+ =C2=A0 device type are described in Table 7-10.
=
+
+ =C2=A0 NOR: =C2=A04 Kbyte =3D 0x1000 bytes
+ =C2=A0 NAND: =C2=A01 Kbyte =3D= 0x400 bytes
+ =C2=A0 OneNAND: 256 bytes =3D 0x100 bytes
+ =C2=A0 SD/eSD/MMC/eMMC: =C2=A01 kbyte =3D 0x400 bytes
+ =C2=A0 I2C/= CSPI EEPROM: =C2=A01 kbyte =3D 0x400 bytes
+
+ =C2=A0 The above flash header offsets are set accordingl= y in:
+ = arch/arm/mach-imx/include/mach/imx-flash-header.h
+
<= div> + =C2=A0 TEXT_BASE =3D 0x83F00000
+ =C2=A0 IMX_CS0_BASE =3D 0xA0000000
+ =C2=A0 #if INTERNAL_B= OOT
+ DEST_BASE =3D IMX_CS0_BASE
+ =C2=A0 #else
+ DEST_BASE =3D TEX= T_BASE
+ =C2=A0 #endif
+ =C2=A0 FLASH_HEADER_BASE =3D (DEST_BASE + = FLASH_HEADER_OFFSET)
+ */
+
+struct imx_dcd_e= ntry __dcd_entry_section dcd_entry[] =3D {
+ /* NOR flash, CS0_CSCRU, CS0_CS= CRL, CS0_CSCRA */
+ { .p= tr_type =3D 4, .addr =3D 0xB8002000, .val =3D 0x0000D003, },
+ { .ptr_type = =3D 4, .addr =3D 0xB8002004, .val =3D 0x00330D01, },
+ { .p= tr_type =3D 4, .addr =3D 0xB8002008, .val =3D 0x00220800, },
+ /* DDR2 init = */
+ { .ptr_ty= pe =3D 4, .addr =3D 0xb8001004, .val =3D 0x0076e83a, }, /* initial value fo= r ESDCFG0 */
+ { .ptr_type =3D 4, .addr =3D 0xb8001010, .val =3D 0x00000204,= }, /* ESD_MISC */
+ { .p= tr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0x92210000, }, /* CS0 prechar= ge command */
+ { .ptr_type =3D 4, .addr =3D 0x80000f00, .val =3D 0x12344321= , }, /* precharge all dummy write */
+ { .p= tr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0xb2210000, }, /* Load Mode R= egister command */
+ { .ptr_type =3D 1, .addr =3D 0x82000000, .val =3D 0xda,= }, =C2=A0= /* dummy write Load EMR2 */
+ { .p= tr_type =3D 1, .addr =3D 0x83000000, .val =3D 0xda, }, =C2=A0 /* dummy write Load EMR= 3 */
+ { .ptr_ty= pe =3D 1, .addr =3D 0x81000400, .val =3D 0xda, }, =C2=A0 /* dummy write Load EMR1; en= able DLL */
+ { .p= tr_type =3D 1, .addr =3D 0x80000333, .val =3D 0xda, }, =C2=A0 /* dummy write Load MR;= reset DLL */
+
+= { .ptr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0x92210000, }, /*= CS0 precharge command */
+ { .ptr_type =3D 4, .addr =3D 0x80000400, .val = =3D 0x12345678, }, /* precharge all dummy write */
+ { .p= tr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0xA2210000, }, /* select manu= al refresh mode */
+ { .ptr_type =3D 4, .addr =3D 0x80000000, .val =3D 0x876= 54321, }, /* manual refresh */
+ { .p= tr_type =3D 4, .addr =3D 0x80000000, .val =3D 0x87654321, }, /* manual refr= esh twice */
+
+ { .ptr_type =3D 4, .addr =3D 0xb8001000, .val =3D= 0xb2210000, }, /* Load Mode Register command */
+ { .p= tr_type =3D 1, .addr =3D 0x80000233, .val =3D 0xda, }, =C2=A0 /* Load MR; CL=3D3, BL= =3D8, end DLL reset */
+ { .p= tr_type =3D 1, .addr =3D 0x81000780, .val =3D 0xda, }, =C2=A0 /* Load EMR1; OCD defau= lt */
+ { .ptr_ty= pe =3D 1, .addr =3D 0x81000400, .val =3D 0xda, }, =C2=A0 /* Load EMR1; OCD exit */
+ {= .ptr_type =3D 4, .addr =3D 0xb8001000, .val =3D 0x82216080, }, /* normal m= ode */
+ /* I= OMUX_SW_PAD setup */
+ { .ptr_type =3D 4, .addr =3D 0x43FAC454, .val =3D 0x0= 0001000, }, /* IOMUXC_SW_PAD_CTL_GRP_DDRTYPE(1-5) */
+ { .p= tr_type =3D 4, .addr =3D 0x43FAC448, .val =3D 0x00002000, }, /* IOMUXC_SW_P= AD NFC voltage 1.8 */
+
+ /* CLKCTL */
+ { .p= tr_type =3D 4, .addr =3D 0x53f80008, .val =3D 0x20034000, }, /* CLKCTL ARM= =3D399 AHB=3D133 */
+};
+
+struct imx_flash_h= eader __flash_header_section flash_header =3D {
+ .app= _code_jump_vector = =3D DEST_BASE + ((unsigned int)&exception_vectors - TEXT_BASE),<= /div>
+ .app_code= _barker =3D= APP_CODE_BARKER,
+ .app_code_csf =3D 0, /* non-secure boot (table 7-11) */
+ .dcd= _ptr_ptr = =3D FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
+= .super_roo= t_key =3D = 0, /* non-secure boot (table 7-11) */
+ .dcd= =3D FLAS= H_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker),
+<= span class=3D"Apple-tab-span" style=3D"white-space:pre"> .app_dest =3D DEST_BA= SE,
+ .dcd= _barker = =3D DCD_BARKER,
+ .dcd_block_len =3D sizeof(dcd_entry),
+};
+
+unsigned long __image_len_section barebox_l= en =3D DCD_BAREBOX_SIZE;
diff --git a/arch/arm/boards/fq-sid1-mx2= 5-noah/lowlevel.c b/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c
new file mode 100644
index 0000000..04ece36
--- /dev/nu= ll
+++ b/arch/arm/boards/fq-sid1-mx25-noah/lowlevel.c
@= @ -0,0 +1,188 @@
+/*
+ *
+ * (c) 2011 Pengutr= onix, Sascha Hauer <s.hauer@pe= ngutronix.de>
+ *
+ * See file CREDITS for list of people who contributed = to this
+ * project.
+ *
+ * This program is = free software; you can redistribute it and/or
+ * modify it under= the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ = *
+ * This program is distributed in the hope that it will be use= ful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =C2=A0See t= he
+ * GNU General Public License for more details.
+ *=
+ * You should have received a copy of the GNU General Public License<= /div>
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h&= gt;
+#include <init.h>
+#include <mach/imx-reg= s.h>
+#include <mach/esdctl.h>
+#include <i= o.h>
+#include <mach/imx-nand.h>
+#include <asm/barebox-= arm.h>
+#include <asm/system.h>
+#include <= asm-generic/sections.h>
+#include <asm-generic/memory_layou= t.h>
+
+#ifdef CONFIG_NAND_IMX_BOOT
+static void __bare= _init __naked insdram(void)
+{
+ uint32_t r;
+
+ /* setup = a stack to be able to call imx_nand_load_image() */
+ r =3D STACK_BASE + ST= ACK_SIZE - 12;
+ __as= m__ __volatile__("mov sp, %0" : : "r"(r));
+<= /div>
+ imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
+
+= board_init_lowlevel_return();
+}
+#endif
<= div>+
+/* Check 24.3.3.1 and 24.5.4.1.1 */
+static inli= ne void __bare_init =C2=A0setup_sdram(uint32_t base, uint32_t esdctl,
+ uin= t32_t esdcfg)
+{
+ uint32_t esdctlreg =3D ESDCTL0;
+ uint32_t esdc= fgreg =3D ESDCFG0;
+
+= if (base =3D=3D 0x90000000) {
+ esdctlreg +=3D 8;
+ esdcfgreg +=3D = 8;
+ }
+
+ esdctl |=3D ESDCTL0_SDE;
+
+ writel(esdcfg, esdcfgreg);=
+ writ= el(esdctl | ESDCTL0_SMODE_PRECHARGE, esdctlreg);
+ writel(0, base + 1024);
+ writ= el(esdctl | ESDCTL0_SMODE_AUTO_REFRESH, esdctlreg);
+ readb(base);
+ readb(b= ase);
+ writ= el(esdctl | ESDCTL0_SMODE_LOAD_MODE, esdctlreg);
+ writeb(0, base + 0x33);
+ writ= el(esdctl, esdctlreg);
+}
+
+void __bare_init= __naked board_init_lowlevel(void)
+{
+ uint32_t r;
+#ifdef CONFIG_NAND_IMX_BOOT
+ unsigned int *trg, *src;
+#end= if
+
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0/* restart the MPLL a= nd wait until it's stable */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0writel(readl(IMX_CCM_BASE + CCM_CCTL) | (= 1 << 27),
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0IMX_CCM_BASE + CCM_CCTL);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0while (readl(IMX_CCM_BASE + CCM_CCTL)= & (1 << 27)) {};
+
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Configure dividers and ARM= clock source
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 * =C2=A0 =C2=A0 =C2= =A0ARM @ 400 MHz
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 * =C2=A0 =C2=A0 = =C2=A0AHB @ 133 MHz
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 */
+<= span class=3D"Apple-tab-span" style=3D"white-space:pre"> writel(0x20= 034000, IMX_CCM_BASE + CCM_CCTL);
+
+= /* Set up 16bit NOR flash on WEIM CS0 */
+ writel(0x0000D003, 0xB800= 2000);
+ writ= el(0x00330D01, 0xB8002004);
+ writel(0x00220800, 0xB8002008);
+
+ /* AIPS s= etup - Only setup MPROTx registers. The PACR default values are good.
=
+ * S= et all MPROTx to be non-bufferable, trusted for R/W,
+ * n= ot forced to user-mode.
+ */
+ writel(0x77777777, 0x43f00000);
+ writ= el(0x77777777, 0x43f00004);
+ writel(0x77777777, 0x53f00000);
+ writel(0x7777= 7777, 0x53f00004);
+
+= /* MAX (Multi-Layer AHB Crossbar Switch) setup
+ * MPR - priority f= or MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
+ */<= /div>
+ writel(0x00043210, 0x43f04000);
+ writel(0x00043210, 0x43f04100);
+ writ= el(0x00043210, 0x43f04200);
+ writel(0x00043210, 0x43f04300);
+ writel(0x0004= 3210, 0x43f04400);
+ /* S= GPCR - always park on last master */
+ writel(0x10, 0x43f04010);
+= writel(0x1= 0, 0x43f04110);
+ writ= el(0x10, 0x43f04210);
+ writel(0x10, 0x43f04310);
+ writel(0x10, 0x43f04410);=
+ /* M= GPCR - restore default values */
+ writel(0x0, 0x43f04800);
+ writel(0x0, 0x4= 3f04900);
+ writ= el(0x0, 0x43f04a00);
+ writel(0x0, 0x43f04b00);
+ writel(0x0, 0x43f04c00);
+
+= /* Configure M3IF registers
+ * M3IF Control Register (M3IFCTL) for= MX25
+ * M= RRP[0] =3D LCDC =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 on priority list (1 <= < 0) =C2=A0=3D 0x00000001
+ * MRRP[1] =3D MAX1 =C2=A0 =C2=A0 =C2=A0 not = on priority list (0 << 1) =C2=A0=3D 0x00000000
+ * M= RRP[2] =3D MAX0 =C2=A0 =C2=A0 =C2=A0 not on priority list (0 << 2) = =C2=A0=3D 0x00000000
+ * MRRP[3] =3D USB HOST =C2=A0 not on priority list (= 0 << 3) =C2=A0=3D 0x00000000
+ * M= RRP[4] =3D SDMA =C2=A0 =C2=A0 =C2=A0 not on priority list (0 << 4) = =C2=A0=3D 0x00000000
+ * MRRP[5] =3D SD/ATA/FEC not on priority list (0 <= ;< 5) =C2=A0=3D 0x00000000
+ * M= RRP[6] =3D SCMFBC =C2=A0 =C2=A0 not on priority list (0 << 6) =C2=A0= =3D 0x00000000
+ * MRRP[7] =3D CSI =C2=A0 =C2=A0 =C2=A0 =C2=A0not on priori= ty list (0 << 7) =C2=A0=3D 0x00000000
+ * = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ----------
+ * =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 0x00000001
+ */<= /div>
+ writel(0x1, 0xb8003000);
+
+ /* enable all the clocks */
+ writ= el(0x1fffffff, IMX_CCM_BASE + CCM_CGCR0);
+ writel(0xffffffff, IMX_CCM_BASE = + CCM_CGCR1);
+ writ= el(0x000fdfff, IMX_CCM_BASE + CCM_CGCR2);
+
+ /* Set DDR2 and NFC = group driver voltages */
+ writ= el(0x1000, IMX_IOMUXC_BASE + 0x454);
+ writel(0x2000, IMX_IOMUXC_BASE + 0x44= 8);
+
+= /* Skip SDRAM initialization if we run from RAM */
+ r =3D get_pc();=
+ if (= r > 0x80000000 && r < 0x90000000)
+ board_init_lowlevel_retur= n();
+
+= writel(ESDMISC_RST, ESDMISC);
+
+ while (!(readl(ESDMISC) = & (1 << 31)));
+
+#define ESDCTLVAL (ESDCTL0_ROW13 | ESDCTL0_COL9 | ESDCTL0_DSIZ_15_0 | \
+ ESDCTL= 0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL)
+#define ESDCFGVAL (ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 | ESDCFGx_tRAS_6 | \
+ ESDCF= Gx_tRRD_2 | ESDCFGx_tCAS_3 | ESDCFGx_tRCD_3 | \
+ E= SDCFGx_tRC_9)
+
+ setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL);=
+ setu= p_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL);
+
+#ifdef CO= NFIG_NAND_IMX_BOOT
+ /* skip NAND boot if not running from NFC space */
+ r = =3D get_pc();
+ if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+ bo= ard_init_lowlevel_return();
+
+= src =3D (unsigned int *)IMX_NFC_BASE;
+ trg =3D (unsigned int *)TEXT= _BASE;
+
+= /* Move ourselves out of NFC SRAM */
+ for (i =3D 0; i < 0x800 / = sizeof(int); i++)
+ *tr= g++ =3D *src++;
+
+ /* Jump to SDRAM */
+ r =3D (unsigned int)&= insdram;
+ __as= m__ __volatile__("mov pc, %0" : : "r"(r));
+#= else
+ <= /span>board_init_lowlevel_return();
+#endif
+}
diff --git a/arch/arm/boards/fq-sid1-mx= 25-noah/sid1_noah.c b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c
new file mode 100644
index 0000000..239d72a
--- /dev= /null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/sid1_noah.c
@@ -0,0 = +1,377 @@
+/*
+ * (C) 2012 FQ Ingenieria, Roberto Nibal= i <rnibali@gmail.com>
+ *
+ * This program is free software; you can redistribute = it and/or
+ * modify it under the terms of the GNU General Public= License as
+ * published by the Free Software Foundation; either= version 2 of
+ * the License, or (at your option) any later version.
+ *<= /div>
+ * This program is distributed in the hope that it will be usefu= l,
+ * but WITHOUT ANY WARRANTY; without even the implied warrant= y of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =C2=A0See the=
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public Lice= nse
+ * along with this program; if not, write to the Free Software
<= div>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *= MA 02111-1307 USA
+ *
+ */
+
+#include <io.h>
+#include <sizes.h>
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <environment.h>
+#include <partition.h>
+#include <driver.h>
+#include <fec.h>
+#include <linux/err.h>
+#include <i2c/i2c.h>
<= div>+#include <generated/mach-types.h>
+#include <asm/ar= mlinux.h>
+#include <asm/mmu.h>
+#include <asm/barebox-arm-he= ad.h>
+#include <asm-generic/sections.h>
+#inc= lude <mach/gpio.h>
+#include <mach/iim.h>
+#include <mach/usb.h>
+#include <mach/imx-regs.h>
+#include <mach/imx-pll.h>
+#include <mach/imx-f= lash-header.h>
+#include <mach/iomux-mx25.h>
+#include <mach/generic.h>
+#include <mach/devices-imx25= .h>
+
+/* The currently used MOSFET IRLMLL6402 needs=
+ =C2=A0 3.3V driver voltage to function, however the
+ =C2=A0 basic GPIO driver voltage is 1.8V, which is
+ =C2=A0 not sufficient, unless the MOSFET switches
+ =C2=A0= starting from VGS > 1.5V.
+ */
+#define MX25_PAD_CS= 1__GPIO_4_3_DVS =C2=A0 =C2=A0 =C2=A0IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_= PAD_CTRL | PAD_CTL_DVS)
+
+static struct fec_platform_data fec_info =3D {
= + .xcv_type= =3D RMII,<= /div>
+ .phy_addr= =3D 1,
+};
+
+#ifdef CONFIG_USB
+static void = imx25_usb_init(void)
+{
+ uint32_t reg;
+
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0/= * Host 1 */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0reg =3D readl(IMX_OTG_BA= SE + 0x600);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0reg &=3D ~(MX35_H1_= SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MX35_H1_USBTE= _BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+ =C2=A0 = =C2=A0 =C2=A0 =C2=A0reg |=3D (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_= H1_SIC_SHIFT;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0reg |=3D MX35_H1_USBTE= _BIT;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0reg |=3D MX35_H1_IPPUE_DOWN_BIT;
+ writel(= reg, IMX_OTG_BASE + 0x600);
+
+ reg =3D readl(IMX_OTG_BASE + 0x584= );
+ reg = |=3D 3 << 30;
+ writel(reg, IMX_OTG_BASE + 0x584);
+
+ /* Set= to Host mode */
+ reg = =3D readl(IMX_OTG_BASE + 0x5a8);
+ writel(reg | 0x3, IMX_OTG_BASE + 0x5a8);<= /div>
+}
+#endif
+
+/*
+static struct at2= 4_platform_data board_eeprom =3D {
+ .byte_len =3D 65536,
+ .page_size =3D 12= 8,
+ .fla= gs =3D AT24_FLAG_ADDR16,
+};
+*/
+
= +static struct i2c_board_info i2c_devices[] =3D {
+ {
+ I2C= _BOARD_INFO("at24", 0x50),
+ //.platform_data =3D &board_eepr= om,
+ },
+};
+
+#if 0
+struct gpio_led noah_l= eds[] =3D {
+ {
+ .le= d =3D { .name =3D "GPIO-LED", },
+ .gpio =3D IMX_GPIO_NR(4, 10),<= /div>
+ .active_= low =3D 1,
+ },
+};
+
+static void noah_leds_i= nit(void)
+{
+ int i;
+ for (i =3D 0; i < ARRAY_SIZE(noah_leds); i++)
+ led_gpi= o_register(&noah_leds[i]);
+}
+#endif
+
+#define MX25_NOAH_BOOT_UNK= NOWN 0
+#define MX25_NOAH_BOOT_NOR 1
+#define MX25_NOAH_BOOT_MMC 2
+static int noah_read_ccm_regs(void) {
+ u= int32_t reg;
+
+= /* =C2=A015.3.3.12 CCM Reset and Debug Register (CRDR)=C2=A0
+ */
+ reg = =3D readl(IMX_CCM_BASE + CCM_CRDR);
+ printf("%s: CCM CRDR =3D %08X\n&q= uot;, __func__, reg);
+
+= /* 15.3.3.11 CCM Status Register (RCSR)
+ if (readl(IMX_CCM_BASE + CCM_RCSR) &a= mp; (1 << 14))
+ nan= d_info.width =3D 2;
+ */
+ reg =3D readl(IMX_CCM_BASE + CCM_RCSR);
+ prin= tf("%s: CCM RCSR =3D %08X\n", __func__, reg);
+ if ((reg & (0x= 3 << 30)) =3D=3D 0x3 << 30) {
+ pri= ntf("%s: Booting from expansion device: ", __func__);
+= if ((reg = & (0x3 << 28)) =3D=3D 0x0 << 28) {
+ pr= intf("SD/MMC\n");
+ return MX25_NOAH_BOOT_MMC;
+ } else {
+ pr= intf("unknown\n");
+ }
+ } else if ((reg & (0x3 << 30)) = =3D=3D 0x0 << 30) {
+ pri= ntf("%s: Booting from WEIM: ", __func__);
+ if ((reg & (0x3 = << 28)) =3D=3D 0x0 << 28) {
+ pr= intf("NOR\n");
+ return MX25_NOAH_BOOT_NOR;
+ } else {
+ pr= intf("unknown\n");
+ }
+ }
+
+= return MX25_NOAH_BOOT_UNKNOWN;
+}
+
+= #ifdef CONFIG_DRIVER_VIDEO_IMX
+static struct imx_fb_videomode im= xfb_mode =3D {
+ .mod= e =C2=A0 =3D {
+ .name =3D "Chunghwa CLAA057VA01CT",
+ .re= fresh =3D 6= 0,
+ .xres =3D 640,
+ .yr= es =3D 480= ,
+ .pixclock =3D KHZ2PICOS(25600),
+ .le= ft_margin = =3D 46,
+ .right_margin =3D 114,
+ .up= per_margin = =3D 34,
+ .lower_margin =3D 11,
+ .hs= ync_len =3D= 48,
+ = .vsync_len = =3D 3,
+ },
+ = .bpp =3D 16= ,
+ .pcr =3D 0xFA000080,= /* 16bpp: Check 33.3.10 of the IMX25RM: LPCR */
+};
+<= /div>
+static struct imx_fb_platform_data noah_fb_data =3D {
+ .mode =C2=A0 =3D &a= mp;imxfb_mode,
+ .num_modes =3D 1,
+ .pwm= r =C2=A0 =3D 0x00A903FF,
+ .lscr1 =C2=A0=3D 0x00120300,
+ .dmacr =C2=A0=3D 0x= 00020010,
+};
+#endif
+
+static iomux_v3_cfg_t imx= 25_pads[] =3D {
+ /* FEC RMII */
+ MX25_PAD_FEC_MDC__FEC_MDC, =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Management data clock */
+ MX25= _PAD_FEC_MDIO__FEC_MDIO, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Manage= ment data input/output */
+ MX25_PAD_FEC_TX_EN__FEC_TX_EN, =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0/* Transmit enable */
+ MX25= _PAD_FEC_RX_DV__FEC_RX_DV, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Carrier sen= se / receive data valid */
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, =C2=A0 =C2=A0= =C2=A0 =C2=A0/* Synchronous clock reference (REF_CLK) */
+ MX25= _PAD_UART2_CTS__FEC_RX_ER, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Receive err= or */
+ = MX25_PAD_FEC_RDATA0__FEC_RDATA0, =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Recei= ve data */
+ MX25= _PAD_FEC_RDATA1__FEC_RDATA1, =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Receive data */<= /div>
+ MX25_PAD_FEC_TDATA0__FEC_TDATA0, =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Transmit da= ta */
+ MX25= _PAD_FEC_TDATA1__FEC_TDATA1, =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Transmit data */=
+#ifdef CONFIG_DRIVER_SERIAL_IMX
+ /* UART1 */
+ MX25= _PAD_UART1_RXD__UART1_RXD,
+ MX25_PAD_UART1_TXD__UART1_TXD,
+ MX25_PAD_UART1= _RTS__UART1_RTS,
+ MX25= _PAD_UART1_CTS__UART1_CTS,
+#endif
+#ifdef CONFIG_USB
+ = /* USBH2 */
+ MX25= _PAD_D9__USBH2_PWR,
+ MX25_PAD_D8__USBH2_OC,
+ MX25_PAD_LD0__USBH2_CLK,
+ MX25= _PAD_LD1__USBH2_DIR,
+ MX25_PAD_LD2__USBH2_STP,
+ MX25_PAD_LD3__USBH2_NXT,
+ MX25= _PAD_LD4__USBH2_DATA0,
+ MX25_PAD_LD5__USBH2_DATA1,
+ MX25_PAD_LD6__USBH2_D= ATA2,
+ MX25= _PAD_LD7__USBH2_DATA3,
+ MX25_PAD_HSYNC__USBH2_DATA4,
+ MX25_PAD_VSYNC__USBH2= _DATA5,
+ MX25= _PAD_LSCLK__USBH2_DATA6,
+ MX25_PAD_OE_ACD__USBH2_DATA7,
+#endif
+ /* I= 2C1 */
+= MX25_PAD_I2C1_CLK__I2C1_CLK,
+ MX25_PAD_I2C1_DAT__I2C1_DAT,
+ /* E= SDHC */
+ /*
+ MX25_PAD_SD1_CMD__SD1_CMD_NPU,
+ MX25= _PAD_SD1_CLK__SD1_CLK_NPU,
+ MX25_PAD_SD1_DATA0__SD1_DATA0_NPU,
+= MX25_PAD_S= D1_DATA1__SD1_DATA1_NPU,
+ MX25= _PAD_SD1_DATA2__SD1_DATA2_NPU,
+ MX25_PAD_SD1_DATA3__SD1_DATA3_NPU,
+ */
+#ifdef CONFIG_DRIVER_VIDEO_IMX
+ /* LCD */
+ MX25_PAD_LD0__LD0, =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT= [19]: Blue[0] (LSB)*/
+ MX25= _PAD_LD1__LD1, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0/* TFT[18]: Blue[1] */
+ MX25_PAD_LD2__LD2, =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT[17]: B= lue[2] */
+ MX25= _PAD_LD3__LD3, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0/* TFT[15]: Blue[3] */
+ MX25_PAD_LD4__LD4, =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT[14]: B= lue[4] */
+ MX25= _PAD_LD5__LD5, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0/* TFT[13]: Blue[5] (MSB) */
+ MX25_PAD_LD6__LD6, =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT= [27]: Green[0] (LSB) */
+ MX25= _PAD_LD7__LD7, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0/* TFT[26]: Green[1] */
+ MX25_PAD_LD8__LD8, =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT[25]: G= reen[2] */
+ MX25= _PAD_LD9__LD9, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0/* TFT[23]: Green[3] */
+ MX25_PAD_LD10__LD10, =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT[22]: Gree= n[4] */
+ MX25= _PAD_LD11__LD11, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0/* TFT[21]: Green[5] (MSB) */
+ MX25_PAD_LD12__LD12, =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT[35]: Red[= 0] (LSB) */
+ MX25= _PAD_LD13__LD13, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0/* TFT[34]: Red[1] */
+ MX25_PAD_LD14__LD14, =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT[33]: Red[2] */
+ MX25= _PAD_LD15__LD15, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0/* TFT[31]: Red[3] */
+ MX25_PAD_GPIO_E__LD16, =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT[30]: Red[4] */
+ MX25= _PAD_GPIO_F__LD17, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0/* TFT[29]: Red[5] (MSB) */
+ MX25_PAD_HSYNC__GPIO_1_22, =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT[ 3]: LCD_HSYNC */
+ MX25= _PAD_VSYNC__GPIO_1_23, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* T= FT[ 8]: LCD_VSYNC */
+ MX25_PAD_LSCLK__LSCLK, =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TFT[38]: LCD_LSCLK */
+ MX25= _PAD_OE_ACD__OE_ACD, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0/* TFT[ 9]: LCD_DRDY */
+ MX25_PAD_CONTRAST__PWM4_PWMO, =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 /* TFT[12]: LCD backlight (PWM): */
+ MX25= _PAD_CS1__GPIO_4_3_DVS, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* TFT[xx= ]: LCD_EN */
+ MX25_PAD_EB1__GPIO_2_13, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0/* TFT[ 1]: LCD_UP_DOWN */
+ MX25= _PAD_BCLK__GPIO_4_4, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0/* TFT[40]: LCD_LEFT_RIGHT */
+ MX25_PAD_CSI_D4__GPIO_1_29, =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* TFT[ 2]: LCD_DMS */
+#endif
+};
+
+static int noah_fec_init(= void)
+{
+ /*
+ * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.=
+ * A= ssert FEC_RESET_B, then power up the PHY by asserting
+ * FEC_ENABLE, at th= e same time lifting FEC_RESET_B.
+ *
+ = * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17
+ * FEC_ENABLE_B: gpio4[8= ] is ALT 5 mode of pin D12
+ */<= /div>
+ writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */
+ writel(0x0, IMX_I= OMUXC_BASE + 0x028C); /* cmos, no pu/pd */
+
+#define FEC_ENABLE_GPIO 35
+#define FEC_RESET_B_GPIO 104
+=
+ /* m= ake the pins output */
+ gpio_direction_output(FEC_ENABLE_GPIO, 0); =C2=A0/*= drop PHY power */
+ gpio= _direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
+ udelay(2);
+
+ /* turn on power & lift reset */
+ gpio_set_value(FEC_ENABLE_GPIO, 1)= ;
+ gpio= _set_value(FEC_RESET_B_GPIO, 1);
+
+ return 0;
+}
<= div> +late_initcall(noah_fec_init);
+
+static int imx25_mem_= init(void)
+{
+ /* add memory bank to 0x80000000 (barebox_add_memo= ry_bank()) */
+ arm_= add_mem_device("ram0", IMX_SDRAM_CS0, 64 * 1024 * 1024);
+
+ return 0;
+}
+mem_initcall(imx25_mem_init);
+
+sta= tic int imx25_devices_init(void)
+{
+ int bootdev;
+
+ boot= dev =3D noah_read_ccm_regs();
+ mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZ= E(imx25_pads));
+ i2c_= register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
+ imx25_add_i2= c0(NULL);
+ imx2= 5_add_mmc0(NULL);
+ imx25_iim_register_fec_ethaddr();
+ imx25_add_fec(&fe= c_info);
+
+= printf("%s: Adding NOR flash device\n", __func__);
<= div>+ /* Co= nfigure 16 bit nor flash on WEIM cs0 */
+ imx2= 5_setup_weimcs(0, 0x0000D003, 0x00330D01, 0x00220800);
+ /* NOR flash starts= at CS0 addr 0xA0000000, set to 64MB */
+ add_= cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, SZ_64M, 0);
+ printf("= ;%s: Adding initial NOR flash partitions\n", __func__);
+ devf= s_add_partition("nor0", 0x00000, SZ_512K, PARTITION_FIXED, "= self0");
+ devfs_add_partition("nor0", SZ_512K, SZ_512K, PART= ITION_FIXED, "env0");
+ //pr= otect_file("/dev/env0", 1);
+#ifdef CONFIG_USB
+ imx25_u= sb_init();
+ add_= generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
+#endif
+#ifdef CONFIG_DRIVER_VIDEO_IMX
+ //imx25_add_fb(&a= mp;noah_fb_data);
+#endif
+ //noah_leds_init();
+ armlinux_set_bootparams((void *)0x800001= 00);
+ arml= inux_set_architecture(MACH_TYPE_MX25_3DS);
+ armlinux_set_serial(imx_uid());=
+
+= return 0;
+}
+device_initcall(imx25_devices_ini= t);
+
+static int imx25_console_init(void)
+{=
+ //im= x25_init_lowlevel(800) + imx25_core_setup();
+ imx25_add_uart0();
= + return 0;=
+}
+console_initcall(imx25_console_init);
+
<= div>+/*=C2=AC=E2=80=A0Check arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35= .c
+ =C2=A0 for more information, especially with regard to low_l= evel
+ =C2=A0 setup inside the core_setup part.
+*/
+static = int imx25_core_setup(void)
+{
+ uint32_t reg;
+ /* Enable clocks:
+ =C2= =A0 UART1: 15
+ =C2=A0 FEC : 23
+ =C2= =A0 SDHC1: 3/21
+ =C2=A0 USB : 28=C2=A0
+ =C2= =A0 I2C : 6=
+ */
+ reg =3D r= eadl(IMX_CCM_BASE + CCM_CGCR0);
+ reg |=3D (1 << 6) | (1 << 23) = | (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28);
+ reg = =3D writel(reg, IMX_CCM_BASE + CCM_CGCR0);
+
+ reg =3D readl(IMX_C= CM_BASE + CCM_CGCR1);
+ reg = |=3D (1 << 23) | (1 << 15) | (1 << 13);
+ reg =3D writel(r= eg, IMX_CCM_BASE + CCM_CGCR1);
+
+= reg =3D readl(IMX_CCM_BASE + CCM_CGCR2);
+ reg |=3D (1 << 14);=
+ reg =3D w= ritel(reg, IMX_CCM_BASE + CCM_CGCR2);
+ /* CCM clocks: PER_12 -- PER_15 (15.= 3.3.10) */
+ //wr= itel(0x03010101, IMX_CCM_BASE + CCM_PCDR3);
+ /* CCM clocks: PER_8 -- PER_11= (15.3.3.9) */
+ //wr= itel(0x01010103, IMX_CCM_BASE + CCM_PCDR2);
+ return 0;
+
+}
+core_initcall(imx25_core_setup);
diff --git a/arch/arm/boar= ds/fq-sid1-mx25-noah/sid1_noah.dox b/arch/arm/boards/fq-sid1-mx25-noah/sid1= _noah.dox
new file mode 100644
index 0000000..8b0e28a
--- /dev/null
+++ b/arch/arm/boards/fq-sid1-mx25-noah/sid1_n= oah.dox
@@ -0,0 +1,79 @@
+/** @page SID1 (FQ=C2=AC=E2= =80=A0Ingenier=E2=88=9A=E2=89=A0a)
+
+This device is al= so known as "NOAH" (http:= //www.fqingenieria.es/)
+
+This CPU card is based on a Freescale i.MX25 CPU. The car= d is shipped with:
+
+- 64 MiB synchronous dynamic RAM = (DDR type)
+- 4=C2=AC=E2=80=A0SIM/SAM=C2=AC=E2=80=A0sockets
=
+- USB OTG
+- ...
+
+Memory layout when @b barebox is running:
+
+- 0x80000000 start of SDRAM (IMX_SDRAM_CS0)
+= - 0x80000100 start of kernel's boot parameters
+ =C2=A0- belo= w malloc area: stack area
+ =C2=A0- below barebox: malloc area
+- 0x82000000 start of = @b barebox
+
+@section get_sid1_noah_binary How to get = the bootloader binary image:
+
+Using the default confi= guration:
+
+@verbatim
+make ARCH=3Darm noah_defconfig
=
+@endverbatim
+
+Build the bootloader binary image= :
+
+@verbatim
+make ARCH=3Darm CROSS_COMPILE= =3Darmv5compiler
+@endverbatim
+
+@note replace the armv5compiler w= ith your ARM v5 cross compiler.
+
+@section setup_falco= nwing How to prepare an MCI card to boot the "chumby one" with ba= rebox
+
+- Create four primary partitions on the SD=C2=AC=E2=80=A0= card
+ - the second one for the persistant environment (512 kiB, = at least 256k)
+ - the third one for the kernel (3 MiB ... 4 MiB = in size)
+ - the fourth one for the root filesystem which can fill the rest of = the available space
+
+- Copy the default @b barebox en= vironment into the second partition (no filesystem required).
+
+- Copy the kernel into the third partition (no filesystem requ= ired).
+
+- Create the root filesystem in the 4th parti= tion. You may copy an image into this
+ =C2=A0partition or you ca= n do it in the classic way: mkfs on it, mount it and copy
+ =C2=A0all required data and programs into it.
+
= +@section gpio_falconwing Available GPIOs
+
+The SID1 N= OAH=C2=AC=E2=80=A0uses some GPIOs to control various features. With the reg= ular
+GPIO commands these features can be controlled at @a barebox's runtime= .
+
+<table width=3D"100%" border=3D"= 1" cellspacing=3D"1" cellpadding=3D"3">
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0<tr>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<td>No&= lt;/td>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0<td>Direction</td>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0<td>Function</td>
+ =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<td>Reset</td>=
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<td>Set</= td>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0</tr>
+ =C2= =A0 =C2=A0 =C2=A0 =C2=A0<tr>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0<td>60</td>
+ =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<td>Output</td>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<td>= Display Backlight</td>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<td>Bac= klight<br>Off</td>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0<td>Backlight<br>On (100 %)</td><= /div>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0</tr>
+ =C2=A0 =C2= =A0 =C2=A0 =C2=A0<tr>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0<td>62</td>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<td>Inp= ut</td>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0<td>Bend</td>
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0<td>Not pressed</td>
+ =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<td>Pressed</td&g= t;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0</tr>
+</table>
+*/
diff --git a/arch/arm/configs/noah_defconfig b/arch/ar= m/configs/noah_defconfig
new file mode 100644
index 000= 0000..152f0bf
--- /dev/null
+++ b/arch/arm/configs/noah_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARCH_IMX=3Dy
+CONFIG_ARCH_IM= X_EXTERNAL_BOOT=3Dy
+CONFIG_ARCH_IMX25=3Dy
+CONFIG_MACH= _MX25_NOAH=3Dy
+CONFIG_IMX_CLKO=3Dy
+CONFIG_IMX_IIM=3Dy
+CONFIG_A= EABI=3Dy
+CONFIG_ARM_UNWIND=3Dy
+CONFIG_MMU=3Dy
+CONFIG_BROKEN=3Dy
+CONFIG_EXPERIMENTAL=3Dy
+CONFIG_= PROMPT=3D"sid1-noah:"
+CONFIG_LONGHELP=3Dy
+CONFIG_GLOB=3Dy
+CONFIG_CMDL= INE_EDITING=3Dy
+CONFIG_AUTO_COMPLETE=3Dy
+CONFIG_DEFAU= LT_ENVIRONMENT_GENERIC=3Dy
+CONFIG_DEFAULT_ENVIRONMENT_PATH=3D&qu= ot;arch/arm/boards/fq-sid1-mx25-noah/env"
+CONFIG_BAREBOXENV_TARGET=3Dy
+CONFIG_ENABLE_FLASH_NOISE=3Dy=
+CONFIG_ENABLE_PARTITION_NOISE=3Dy
+CONFIG_ENABLE_DEVI= CE_NOISE=3Dy
+CONFIG_CMD_EDIT=3Dy
+CONFIG_CMD_SLEEP=3Dy=
+CONFIG_CMD_SAVEENV=3Dy
+CONFIG_CMD_EXPORT=3Dy
+CONFIG_= CMD_PRINTENV=3Dy
+CONFIG_CMD_READLINE=3Dy
+CONFIG_CMD_T= IME=3Dy
+CONFIG_CMD_AUTOMOUNT=3Dy
+CONFIG_CMD_ECHO_E=3D= y
+CONFIG_CMD_LOADB=3Dy
+CONFIG_CMD_LOADY=3Dy
+CONFIG_CMD= _LOADS=3Dy
+CONFIG_CMD_SAVES=3Dy
+CONFIG_CMD_MEMINFO=3D= y
+CONFIG_CMD_IOMEM=3Dy
+CONFIG_CMD_MD5SUM=3Dy
+CONFIG_CMD_SHA1SUM=3Dy
+CONFIG_CMD_SHA256SUM=3Dy
+CONFIG_CMD_SHA224SUM=3Dy
+CONFIG_CMD_MTEST=3Dy
+CONFIG_CMD_MTEST_ALTERNATIVE=3Dy
+CONFIG_CMD_FLASH=3Dy
+CONFIG_CMD_BOOTM_SHOW_TYPE=3Dy
+CONFIG_CMD_BOOTM_VERBOSE=3Dy
+CONFIG_CMD_BOOTM_INITRD=3Dy
+CONFIG_CMD_BOOTM_OFTREE=3Dy
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=3Dy
+CONFIG_CMD_UIMAGE=3D= y
+CONFIG_CMD_RESET=3Dy
+CONFIG_CMD_GO=3Dy
+C= ONFIG_CMD_OFTREE=3Dy
+CONFIG_CMD_TIMEOUT=3Dy
+CONFIG_CMD_PARTITION=3Dy
= +CONFIG_CMD_MAGICVAR=3Dy
+CONFIG_CMD_MAGICVAR_HELP=3Dy
= +CONFIG_CMD_BMP=3Dy
+CONFIG_CMD_GPIO=3Dy
+CONFIG_CMD_UN= COMPRESS=3Dy
+CONFIG_CMD_I2C=3Dy
+CONFIG_CMD_LED=3Dy
+CONFIG_NE= T=3Dy
+CONFIG_NET_DHCP=3Dy
+CONFIG_NET_NFS=3Dy
+CONFIG_NET_PING=3Dy
+CONFIG_NET_TFTP=3Dy
+CONFIG_NET= _TFTP_PUSH=3Dy
+CONFIG_NET_NETCONSOLE=3Dy
+CONFIG_NET_RESOLV=3Dy
= +CONFIG_DRIVER_NET_FEC_IMX=3Dy
+CONFIG_DRIVER_SPI_IMX=3Dy
+CONFIG_I2C=3Dy
+CONFIG_I2C_IMX=3Dy
+CONFIG_DRIVER_C= FI=3Dy
+# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
+# CONFIG_DRIVE= R_CFI_BANK_WIDTH_4 is not set
+CONFIG_MTD=3Dy
+CONFIG_U= SB=3Dy
+CONFIG_USB_EHCI=3Dy
+CONFIG_USB_OHCI=3Dy
<= div> +CONFIG_USB_STORAGE=3Dy
+CONFIG_VIDEO=3Dy
+CONFIG_DRIVE= R_VIDEO_IMX=3Dy
+CONFIG_MCI=3Dy
+CONFIG_MCI_STARTUP=3Dy=
+CONFIG_MCI_IMX_ESDHC=3Dy
+CONFIG_LED=3Dy
+C= ONFIG_LED_GPIO=3Dy
+CONFIG_EEPROM_AT25=3Dy
+CONFIG_FS_CRAMFS=3Dy
+CON= FIG_FS_TFTP=3Dy
+CONFIG_FS_FAT=3Dy
+CONFIG_FS_FAT_WRITE= =3Dy
+CONFIG_FS_FAT_LFN=3Dy
+CONFIG_BZLIB=3Dy
+CONFIG_LZO_DECOMPRESS=3Dy
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3236762..839de09 100644
--- a/arch/arm/mach-imx/Kcon= fig
+++ b/arch/arm/mach-imx/Kconfig
@@ -23,6 +23,7 @@ c= onfig ARCH_TEXT_BASE
=C2=A0 default 0x7ff00000 if MACH_MX53_SMD
=C2=A0 default 0x87f00000 if MACH_GUF_C= UPID
=C2=A0 defa= ult 0x93d00000 if MACH_TX25
+ default 0x83f00000 if MACH_MX25_NOAH
=C2=A0 def= ault 0x7ff00000 if MACH_TQMA53
=C2=A0 default 0x97f00000 if MACH_TX51
=C2=A0 default 0x4fc00000 if MACH_MX6Q_ARM2=
@@ -47,6 +48,7 @@ config BOARDINFO
=C2=A0 default "Freescale i.MX53 SMD" if MACH_FREESCALE_MX53_SMD
<= div>=C2=A0 = default "Garz+Fricke Cupid" if MACH_GUF_CUPID
=C2=A0 default "Ka-Ro tx25" if MACH_TX25
+ default "SID1 NOAH"= if MACH_MX25_NOAH
=C2=A0 default "TQ tqma53" if MACH_TQMA53
=C2=A0 default "Ka-Ro t= x51" if MACH_TX51
=C2=A0 default "Freescale i.MX6q armadillo2" if MACH_MX6Q_ARM2
@@ -251,6 +253,12 @@ config MACH_TX25
=C2=A0 help
=C2=A0 =C2=A0Say Y here if you are using the Ka-Ro tx25 board
=C2=A0
+config MACH_MX25_NOAH
+ bool "SID1 NOAH"
+ sele= ct MACH_HAS_LOWLEVEL_INIT
+ help
+ =C2=A0Say Y here if you are using the S= ID1 NOAH board
+
=C2=A0endchoice
=C2=A0
=C2=A0endif
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/= mach-imx/include/mach/imx25-regs.h
index 73307c4..8225832 100644<= /div>
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -72,6 += 72,7 @@
=C2=A0#define CCM_LTR1 0x44
=C2=A0#define CCM_LTR2 0x48
=C2=A0#define CCM_LTR3 0x4c
+#define CCM_MCR 0x64
=C2=A0
=C2= =A0#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
=C2=A0#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
@@ -10= 7,6 +108,22 @@
=C2=A0#define CSCR_L(x) =C2=A0 =C2=A0 (WEIM_BASE += 4 + (x) * 0x10)
=C2=A0#define CSCR_A(x) =C2=A0 =C2=A0 (WEIM_BASE + 8 + (x) * 0x10)
=C2=A0
+/* Chip Select Registers */
+#define IMX= _WEIM_BASE WEIM_BASE
+#define CSxU(x) __REG(IMX_WEIM_BASE + (cs *= 0x10) + 0x00) /* Chip Select x Upper Register =C2=A0 =C2=A0*/
+#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Sel= ect x Lower Register =C2=A0 =C2=A0*/
+#define CSxA(x) __REG(IMX_W= EIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */
<= div>+#define EIM =C2=A0__REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Re= gister =C2=A0 =C2=A0 */
+
+#ifndef __ASSEMBLY__
+static inline void imx25_= setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional)<= /div>
+{
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0CSxU(cs) =3D upper;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0CSxL(cs) =3D lower;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0CSxA(cs) =3D addional;
+}
=
+#endif /* __ASSEMBLY__ */
+
=C2=A0/*
= =C2=A0 * Definitions for the clocksource driver
=C2=A0 *

Thanks and best regards
Roberto =C2=A0
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