* [PATCH 01/14] ARM i.MX31: give register base addresses a proper MX31_ prefix
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 02/14] ARM i.MX35: give register base addresses a proper MX35_ prefix Sascha Hauer
` (12 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm037/lowlevel_init.S | 42 ++---
arch/arm/boards/pcm037/pcm037.c | 42 ++---
arch/arm/mach-imx/imx31.c | 10 +-
arch/arm/mach-imx/include/mach/devices-imx31.h | 34 +++-
arch/arm/mach-imx/include/mach/imx31-regs.h | 202 ++++++++++++++----------
arch/arm/mach-imx/speed-imx31.c | 8 +-
6 files changed, 194 insertions(+), 144 deletions(-)
diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S
index 31ed6df..b727ad8 100644
--- a/arch/arm/boards/pcm037/lowlevel_init.S
+++ b/arch/arm/boards/pcm037/lowlevel_init.S
@@ -44,13 +44,13 @@
board_init_lowlevel:
mov r10, lr
- writel(IPU_CONF_DI_EN, IPU_CONF)
- writel(0x074B0BF5, IMX_CCM_BASE + CCM_CCMR)
+
+ writel(0x074B0BF5, MX31_CCM_BASE_ADDR + CCM_CCMR)
DELAY 0x40000
- writel(0x074B0BF5 | CCMR_MPE, IMX_CCM_BASE + CCM_CCMR)
- writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, IMX_CCM_BASE + CCM_CCMR)
+ writel(0x074B0BF5 | CCMR_MPE, MX31_CCM_BASE_ADDR + CCM_CCMR)
+ writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, MX31_CCM_BASE_ADDR + CCM_CCMR)
writel(PDR0_CSI_PODF(0xff1) | \
PDR0_PER_PODF(7) | \
@@ -59,10 +59,10 @@ board_init_lowlevel:
PDR0_IPG_PODF(1) | \
PDR0_MAX_PODF(3) | \
PDR0_MCU_PODF(0), \
- IMX_CCM_BASE + CCM_PDR0)
+ MX31_CCM_BASE_ADDR + CCM_PDR0)
- writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), IMX_CCM_BASE + CCM_MPCTL)
- writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), IMX_CCM_BASE + CCM_SPCTL)
+ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), MX31_CCM_BASE_ADDR + CCM_MPCTL)
+ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + CCM_SPCTL)
/* Configure IOMUXC
* Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
@@ -98,15 +98,15 @@ clear_iomux:
writel(0x00000004, ESDMISC)
writel(0x006ac73a, ESDCFG0)
writel(0x90100000 | ROWS0, ESDCTL0)
- writel(0x12344321, IMX_SDRAM_CS0 + 0xf00)
+ writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00)
writel(0xa0100000 | ROWS0, ESDCTL0)
- writel(0x12344321, IMX_SDRAM_CS0)
- writel(0x12344321, IMX_SDRAM_CS0)
+ writel(0x12344321, MX31_CSD0_BASE_ADDR)
+ writel(0x12344321, MX31_CSD0_BASE_ADDR)
writel(0xb0100000 | ROWS0, ESDCTL0)
- writeb(0xda, IMX_SDRAM_CS0 + 0x33)
- writeb(0xff, IMX_SDRAM_CS0 + 0x01000000)
+ writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33)
+ writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000)
writel(0x80226080 | ROWS0, ESDCTL0)
- writel(0xDEADBEEF, IMX_SDRAM_CS0)
+ writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR)
writel(0x0000000c, ESDMISC)
#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
@@ -117,23 +117,23 @@ clear_iomux:
#endif
writel(0x006ac73a, ESDCFG1)
writel(0x90100000 | ROWS1, ESDCTL1)
- writel(0x12344321, IMX_SDRAM_CS1 + 0xf00)
+ writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00)
writel(0xa0100000 | ROWS1, ESDCTL1)
- writel(0x12344321, IMX_SDRAM_CS1)
- writel(0x12344321, IMX_SDRAM_CS1)
+ writel(0x12344321, MX31_CSD1_BASE_ADDR)
+ writel(0x12344321, MX31_CSD1_BASE_ADDR)
writel(0xb0100000 | ROWS1, ESDCTL1)
- writeb(0xda, IMX_SDRAM_CS1 + 0x33)
- writeb(0xff, IMX_SDRAM_CS1 + 0x01000000)
+ writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33)
+ writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000)
writel(0x80226080 | ROWS1, ESDCTL1)
- writel(0xDEADBEEF, IMX_SDRAM_CS1)
+ writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR)
writel(0x0000000c, ESDMISC)
#endif
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =0x80f00000 /* Setup a temporary stack in SDRAM */
- ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
- ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
+ ldr r0, =MX31_NFC_BASE_ADDR /* start of NFC SRAM */
+ ldr r2, =MX31_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index 28d3b13..a63bd23 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -66,15 +66,15 @@ static void pcm037_usb_init(void)
writel(tmp, 0x53f80000);
/* Host 1 */
- tmp = readl(IMX_OTG_BASE + 0x600);
+ tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
tmp &= ~((3 << 21) | 1);
tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20);
- writel(tmp, IMX_OTG_BASE + 0x600);
+ writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
- tmp = readl(IMX_OTG_BASE + 0x184);
+ tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x184);
tmp &= ~(3 << 30);
tmp |= 2 << 30;
- writel(tmp, IMX_OTG_BASE + 0x184);
+ writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x184);
imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0);
imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1);
@@ -90,10 +90,10 @@ static void pcm037_usb_init(void)
imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP);
mdelay(50);
- ulpi_setup((void *)(IMX_OTG_BASE + 0x170), 1);
+ ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1);
/* Host 2 */
- tmp = readl(IOMUXC_BASE + 0x8);
+ tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x8);
tmp |= 1 << 11;
writel(tmp, IOMUXC_BASE + 0x8);
@@ -124,31 +124,31 @@ static void pcm037_usb_init(void)
imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
- tmp = readl(IMX_OTG_BASE + 0x600);
+ tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
tmp &= ~((3 << 21) | 1);
tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
- writel(tmp, IMX_OTG_BASE + 0x600);
+ writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
- tmp = readl(IMX_OTG_BASE + 0x584);
+ tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584);
tmp &= ~(3 << 30);
tmp |= 2 << 30;
- writel(tmp, IMX_OTG_BASE + 0x584);
+ writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584);
mdelay(50);
- ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1);
+ ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1);
/* Set to Host mode */
- tmp = readl(IMX_OTG_BASE + 0x1a8);
- writel(tmp | 0x3, IMX_OTG_BASE + 0x1a8);
+ tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8);
+ writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8);
}
#endif
static int pcm037_mem_init(void)
{
- arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM0 * 1024 * 1024);
+ arm_add_mem_device("ram0", MX31_CSD0_BASE_ADDR, SDRAM0 * 1024 * 1024);
#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
- arm_add_mem_device("ram1", IMX_SDRAM_CS1, SDRAM1 * 1024 * 1024);
+ arm_add_mem_device("ram1", MX31_CSD1_BASE_ADDR, SDRAM1 * 1024 * 1024);
#endif
return 0;
@@ -185,7 +185,7 @@ static int imx31_devices_init(void)
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
- add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
+ add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
/*
* Create partitions that should be
@@ -200,7 +200,7 @@ static int imx31_devices_init(void)
* up to 2MiB static RAM type memory, connected
* to CS4, data width is 16 bit
*/
- add_mem_device("sram0", IMX_CS4_BASE, IMX_CS4_RANGE, /* area size */
+ add_mem_device("sram0", MX31_CS4_BASE_ADDR, MX31_CS4_SIZE, /* area size */
IORESOURCE_MEM_WRITEABLE);
imx31_add_nand(&nand_info);
@@ -209,13 +209,13 @@ static int imx31_devices_init(void)
* connected to CS line 1 and interrupt line
* GPIO3, data width is 16 bit
*/
- add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, IMX_CS1_BASE,
- IMX_CS1_RANGE, IORESOURCE_MEM, NULL);
+ add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX31_CS1_BASE_ADDR,
+ MX31_CS1_SIZE, IORESOURCE_MEM, NULL);
#ifdef CONFIG_USB
pcm037_usb_init();
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE, NULL);
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_OTG_BASE_ADDR, NULL);
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_HS2_BASE_ADDR, NULL);
#endif
armlinux_set_bootparams((void *)0x80000100);
diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c
index 881c3e5..60745a7 100644
--- a/arch/arm/mach-imx/imx31.c
+++ b/arch/arm/mach-imx/imx31.c
@@ -18,13 +18,13 @@
static int imx31_init(void)
{
- add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
+ add_generic_device("imx_iim", 0, NULL, MX31_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpt", 0, NULL, 0x53f90000, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpt", 0, NULL, MX31_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 0, NULL, MX31_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 1, NULL, MX31_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 2, NULL, MX31_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h
index 5dcea82..d45e4e1 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx31.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx31.h
@@ -2,34 +2,52 @@
#include <mach/imx-regs.h>
#include <mach/devices.h>
-#if 0
static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata)
{
- return imx_add_spi((void *)IMX_SPI1_BASE, 0, pdata);
+ return imx_add_spi((void *)MX31_CSPI1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx31_add_spi1(struct spi_imx_master *pdata)
{
- return imx_add_spi((void *)IMX_SPI2_BASE, 1, pdata);
+ return imx_add_spi((void *)MX31_CSPI2_BASE_ADDR, 1, pdata);
+}
+
+static inline struct device_d *imx31_add_spi2(struct spi_imx_master *pdata)
+{
+ return imx_add_spi((void *)MX31_CSPI3_BASE_ADDR, 2, pdata);
}
-#endif
static inline struct device_d *imx31_add_uart0(void)
{
- return imx_add_uart((void *)IMX_UART1_BASE, 0);
+ return imx_add_uart((void *)MX31_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx31_add_uart1(void)
{
- return imx_add_uart((void *)IMX_UART2_BASE, 1);
+ return imx_add_uart((void *)MX31_UART2_BASE_ADDR, 1);
+}
+
+static inline struct device_d *imx31_add_uart2(void)
+{
+ return imx_add_uart((void *)MX31_UART3_BASE_ADDR, 2);
+}
+
+static inline struct device_d *imx31_add_uart3(void)
+{
+ return imx_add_uart((void *)MX31_UART4_BASE_ADDR, 3);
+}
+
+static inline struct device_d *imx31_add_uart4(void)
+{
+ return imx_add_uart((void *)MX31_UART5_BASE_ADDR, 4);
}
static inline struct device_d *imx31_add_nand(struct imx_nand_platform_data *pdata)
{
- return imx_add_nand((void *)0xb8000000, pdata);
+ return imx_add_nand((void *)MX31_NFC_BASE_ADDR, pdata);
}
static inline struct device_d *imx31_add_fb(struct imx_ipu_fb_platform_data *pdata)
{
- return imx_add_ipufb((void *)IPU_BASE, pdata);
+ return imx_add_ipufb((void *)MX31_IPU_CTRL_BASE_ADDR, pdata);
}
diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h
index e3473d4..4d0efd5 100644
--- a/arch/arm/mach-imx/include/mach/imx31-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx31-regs.h
@@ -19,6 +19,8 @@
#ifndef __ASM_ARCH_MX31_REGS_H
#define __ASM_ARCH_MX31_REGS_H
+#include <sizes.h>
+
/*
* sanity check
*/
@@ -26,72 +28,125 @@
# error "Please do not include directly. Use imx-regs.h instead."
#endif
-#define IMX_OTG_BASE 0x43F88000
-#define IMX_UART1_BASE 0x43F90000
-#define IMX_UART2_BASE 0x43F94000
-#define IMX_WDT_BASE 0x53FDC000
-#define IMX_RTC_BASE 0x53FD8000
-#define IMX_TIM1_BASE 0x53F90000
-#define IMX_IIM_BASE 0x5001C000
-
-#define IMX_SDRAM_CS0 0x80000000
-#define IMX_SDRAM_CS1 0x90000000
-
-/*
- * Adresses and ranges of the external chip select lines
- */
-#define IMX_CS0_BASE 0xA0000000
-#define IMX_CS0_RANGE (128 * 1024 * 1024)
-#define IMX_CS1_BASE 0xA8000000
-#define IMX_CS1_RANGE (128 * 1024 * 1024)
-#define IMX_CS2_BASE 0xB0000000
-#define IMX_CS2_RANGE (32 * 1024 * 1024)
-#define IMX_CS3_BASE 0xB2000000
-#define IMX_CS3_RANGE (32 * 1024 * 1024)
-#define IMX_CS4_BASE 0xB4000000
-#define IMX_CS4_RANGE (32 * 1024 * 1024)
-#define IMX_CS5_BASE 0xB6000000
-#define IMX_CS5_RANGE (32 * 1024 * 1024)
-
-#if 0
-#define IMX_IO_BASE 0x00200000
-
-/*
- * Register BASEs, based on OFFSETs
- */
-#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
-#define (0x01000 + IMX_IO_BASE)
- (0x02000 + IMX_IO_BASE)
-#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
- (0x04000 + IMX_IO_BASE)
-#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
-#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
-#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
-#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
-#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
-#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
-#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
-#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
-#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
-#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
-#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
-#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
-#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
-#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
-#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
-#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)
-#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
-#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
-#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
-#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
-#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
-#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
-#endif
+#define MX31_AIPS1_BASE_ADDR 0x43f00000
+#define MX31_AIPS1_SIZE SZ_1M
+#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
+#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
+#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
+#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
+#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
+#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
+#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
+#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
+#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
+#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
+#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
+#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
+#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
+#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
+#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
+#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
+#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
+#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
+#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
+#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
+#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
+#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
+#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
+#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
+
+#define MX31_SPBA0_BASE_ADDR 0x50000000
+#define MX31_SPBA0_SIZE SZ_1M
+#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
+#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
+#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
+#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
+#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
+#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
+#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
+#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
+#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
+#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
+
+#define MX31_AIPS2_BASE_ADDR 0x53f00000
+#define MX31_AIPS2_SIZE SZ_1M
+#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
+#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
+#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
+#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
+#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
+#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
+#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
+#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
+#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
+#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
+#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
+#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
+#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
+#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
+#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
+#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
+#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
+#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
+#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
+#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
+#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
+
+#define MX31_ROMP_BASE_ADDR 0x60000000
+#define MX31_ROMP_SIZE SZ_1M
+
+#define MX31_AVIC_BASE_ADDR 0x68000000
+#define MX31_AVIC_SIZE SZ_1M
+
+#define MX31_IPU_MEM_BASE_ADDR 0x70000000
+#define MX31_CSD0_BASE_ADDR 0x80000000
+#define MX31_CSD1_BASE_ADDR 0x90000000
+
+#define MX31_CS0_BASE_ADDR 0xa0000000
+#define MX31_CS0_SIZE SZ_128M
+
+#define MX31_CS1_BASE_ADDR 0xa8000000
+#define MX31_CS1_SIZE SZ_128M
+
+#define MX31_CS2_BASE_ADDR 0xb0000000
+#define MX31_CS2_SIZE SZ_32M
+
+#define MX31_CS3_BASE_ADDR 0xb2000000
+#define MX31_CS3_SIZE SZ_32M
+
+#define MX31_CS4_BASE_ADDR 0xb4000000
+#define MX31_CS4_SIZE SZ_32M
+
+#define MX31_CS5_BASE_ADDR 0xb6000000
+#define MX31_CS5_SIZE SZ_32M
+
+#define MX31_X_MEMC_BASE_ADDR 0xb8000000
+#define MX31_X_MEMC_SIZE SZ_64K
+#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
+#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
+#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
+#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
+#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
+#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
+
+#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
+#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
+#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
+#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
+
+#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
+
+/* FIXME: Get rid of these */
+#define IMX_TIM1_BASE MX31_GPT1_BASE_ADDR
+#define IMX_WDT_BASE MX31_WDOG_BASE_ADDR
+#define IMX_ESD_BASE MX31_ESDCTL_BASE_ADDR
+#define IMX_NFC_BASE MX31_NFC_BASE_ADDR
+#define IOMUXC_BASE MX31_IOMUXC_BASE_ADDR
/*
* Clock Controller Module (CCM)
*/
-#define IMX_CCM_BASE 0x53f80000
#define CCM_CCMR 0x00
#define CCM_PDR0 0x04
#define CCM_PDR1 0x08
@@ -124,15 +179,9 @@
#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
#define PDR0_MCU_PODF(x) ((x) & 0x7)
-#define IMX_ESD_BASE 0xb8001000
#include "esdctl.h"
/*
- * NFC Registers
- */
-#define IMX_NFC_BASE (0xb8000000)
-
-/*
* Chip Select Registers
*/
#define WEIM_BASE 0xb8002000
@@ -143,26 +192,10 @@
/*
* ???????????
*/
-#define IOMUXC_BASE 0x43FAC000
#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
-#define IPU_BASE 0x53fc0000
-#define IPU_CONF IPU_BASE
-
-#define IPU_CONF_PXL_ENDIAN (1<<8)
-#define IPU_CONF_DU_EN (1<<7)
-#define IPU_CONF_DI_EN (1<<6)
-#define IPU_CONF_ADC_EN (1<<5)
-#define IPU_CONF_SDC_EN (1<<4)
-#define IPU_CONF_PF_EN (1<<3)
-#define IPU_CONF_ROT_EN (1<<2)
-#define IPU_CONF_IC_EN (1<<1)
-#define IPU_CONF_SCI_EN (1<<0)
-
-#define WDOG_BASE 0x53FDC000
-
/*
* Signal Multiplexing (IOMUX)
*/
@@ -214,4 +247,3 @@
#define MUX_CSPI2_MISO_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
#endif /* __ASM_ARCH_MX31_REGS_H */
-
diff --git a/arch/arm/mach-imx/speed-imx31.c b/arch/arm/mach-imx/speed-imx31.c
index 64476b7..f8f73c1 100644
--- a/arch/arm/mach-imx/speed-imx31.c
+++ b/arch/arm/mach-imx/speed-imx31.c
@@ -21,12 +21,12 @@ ulong imx_get_mpl_dpdgck_clk(void)
{
ulong infreq;
- if ((readl(IMX_CCM_BASE + CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+ if ((readl(MX31_CCM_BASE_ADDR + CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
infreq = CONFIG_MX31_CLK32 * 1024;
else
infreq = CONFIG_MX31_HCLK_FREQ;
- return imx_decode_pll(readl(IMX_CCM_BASE + CCM_MPCTL), infreq);
+ return imx_decode_pll(readl(MX31_CCM_BASE_ADDR + CCM_MPCTL), infreq);
}
ulong imx_get_mcu_main_clk(void)
@@ -43,7 +43,7 @@ ulong imx_get_mcu_main_clk(void)
*/
ulong imx_get_lcdclk(void)
{
- ulong hsp_podf = (readl(IMX_CCM_BASE + CCM_PDR0) >> 11) & 0x03;
+ ulong hsp_podf = (readl(MX31_CCM_BASE_ADDR + CCM_PDR0) >> 11) & 0x03;
ulong base_clk = imx_get_mcu_main_clk();
return base_clk / (hsp_podf + 1);
@@ -52,7 +52,7 @@ ulong imx_get_lcdclk(void)
ulong imx_get_perclk1(void)
{
u32 freq = imx_get_mcu_main_clk();
- u32 pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
+ u32 pdr0 = readl(MX31_CCM_BASE_ADDR + CCM_PDR0);
freq /= ((pdr0 >> 3) & 0x7) + 1;
freq /= ((pdr0 >> 6) & 0x3) + 1;
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 02/14] ARM i.MX35: give register base addresses a proper MX35_ prefix
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
2012-09-24 10:46 ` [PATCH 01/14] ARM i.MX31: give register base addresses a proper MX31_ prefix Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 03/14] ARM i.MX21: give register base addresses a proper MX21_ prefix Sascha Hauer
` (11 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c | 100 ++++++------
arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 24 +--
arch/arm/boards/freescale-mx35-3-stack/3stack.c | 78 +++++-----
.../boards/freescale-mx35-3-stack/lowlevel_init.S | 6 +-
arch/arm/boards/guf-cupid/board.c | 74 ++++-----
arch/arm/boards/guf-cupid/lowlevel.c | 28 ++--
arch/arm/boards/pcm043/lowlevel.c | 26 ++--
arch/arm/boards/pcm043/pcm043.c | 78 +++++-----
arch/arm/mach-imx/imx35.c | 14 +-
arch/arm/mach-imx/include/mach/devices-imx35.h | 34 ++--
arch/arm/mach-imx/include/mach/imx35-regs.h | 162 ++++++++++++++------
arch/arm/mach-imx/speed-imx35.c | 30 ++--
12 files changed, 368 insertions(+), 286 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 3c7fb69..53cc428 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -97,21 +97,21 @@ static void imx35_usb_init(void)
unsigned int tmp;
/* Host 1 */
- tmp = readl(IMX_OTG_BASE + 0x600);
+ tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x600);
tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT;
tmp |= MX35_H1_USBTE_BIT | MX35_H1_PM_BIT | MX35_H1_TLL_BIT ;
tmp |= MX35_H1_IPPUE_DOWN_BIT;
- writel(tmp, IMX_OTG_BASE + 0x600);
+ writel(tmp, MX35_USB_OTG_BASE_ADDR + 0x600);
- tmp = readl(IMX_OTG_BASE + 0x584);
+ tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x584);
tmp |= 3 << 30;
- writel(tmp, IMX_OTG_BASE + 0x584);
+ writel(tmp, MX35_USB_OTG_BASE_ADDR + 0x584);
/* Set to Host mode */
- tmp = readl(IMX_OTG_BASE + 0x5a8);
- writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
+ tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x5a8);
+ writel(tmp | 0x3, MX35_USB_OTG_BASE_ADDR + 0x5a8);
}
#endif
@@ -124,7 +124,7 @@ static struct fsl_usb2_platform_data usb_pdata = {
static int eukrea_cpuimx35_mem_init(void)
{
- arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
+ arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, 128 * 1024 * 1024);
return 0;
}
@@ -216,13 +216,13 @@ static int eukrea_cpuimx35_devices_init(void)
#ifdef CONFIG_USB
imx35_usb_init();
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX35_USB_HS_BASE_ADDR, NULL);
#endif
#ifdef CONFIG_USB_GADGET
/* Workaround ENGcm09152 */
- tmp = readl(IMX_OTG_BASE + 0x608);
- writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608);
- add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200,
+ tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x608);
+ writel(tmp | (1 << 23), MX35_USB_OTG_BASE_ADDR + 0x608);
+ add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX35_USB_OTG_BASE_ADDR, 0x200,
IORESOURCE_MEM, &usb_pdata);
#endif
armlinux_set_bootparams((void *)0x80000100);
@@ -246,70 +246,70 @@ static int eukrea_cpuimx35_core_init(void)
u32 reg;
/* enable clock for I2C1, SDHC1, USB and FEC */
- reg = readl(IMX_CCM_BASE + CCM_CGR1);
+ reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT;
reg |= 0x3 << CCM_CGR1_I2C1_SHIFT,
- reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
- reg = readl(IMX_CCM_BASE + CCM_CGR2);
+ reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1);
+ reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR2);
reg |= 0x3 << CCM_CGR2_USB_SHIFT;
- reg = writel(reg, IMX_CCM_BASE + CCM_CGR2);
+ reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR2);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
- writel(0x77777777, IMX_AIPS1_BASE);
- writel(0x77777777, IMX_AIPS1_BASE + 0x4);
- writel(0x77777777, IMX_AIPS2_BASE);
- writel(0x77777777, IMX_AIPS2_BASE + 0x4);
+ writel(0x77777777, MX35_AIPS1_BASE_ADDR);
+ writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
+ writel(0x77777777, MX35_AIPS2_BASE_ADDR);
+ writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
- writel(0x0, IMX_AIPS1_BASE + 0x40);
- writel(0x0, IMX_AIPS1_BASE + 0x44);
- writel(0x0, IMX_AIPS1_BASE + 0x48);
- writel(0x0, IMX_AIPS1_BASE + 0x4C);
- reg = readl(IMX_AIPS1_BASE + 0x50);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
+ reg = readl(MX35_AIPS1_BASE_ADDR + 0x50);
reg &= 0x00FFFFFF;
- writel(reg, IMX_AIPS1_BASE + 0x50);
+ writel(reg, MX35_AIPS1_BASE_ADDR + 0x50);
- writel(0x0, IMX_AIPS2_BASE + 0x40);
- writel(0x0, IMX_AIPS2_BASE + 0x44);
- writel(0x0, IMX_AIPS2_BASE + 0x48);
- writel(0x0, IMX_AIPS2_BASE + 0x4C);
- reg = readl(IMX_AIPS2_BASE + 0x50);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
+ reg = readl(MX35_AIPS2_BASE_ADDR + 0x50);
reg &= 0x00FFFFFF;
- writel(reg, IMX_AIPS2_BASE + 0x50);
+ writel(reg, MX35_AIPS2_BASE_ADDR + 0x50);
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
#define MAX_PARAM1 0x00302154
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
/* SGPCR - always park on last master */
- writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
- writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
- writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
- writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
- writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */
/* MGPCR - restore default values */
- writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
- writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
- writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
- writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
- writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
- writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */
/*
* M3IF Control Register (M3IFCTL)
@@ -324,7 +324,7 @@ static int eukrea_cpuimx35_core_init(void)
* ------------
* 0x00000040
*/
- writel(0x40, IMX_M3IF_BASE);
+ writel(0x40, MX35_M3IF_BASE_ADDR);
return 0;
}
@@ -345,10 +345,10 @@ static int do_cpufreq(int argc, char *argv[])
switch (freq) {
case 399:
- writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
+ writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
break;
case 532:
- writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index b421dfc..60a438a 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -40,10 +40,10 @@ static void __bare_init __naked insdram(void)
uint32_t r;
/* Speed up NAND controller by adjusting the NFC divider */
- r = readl(IMX_CCM_BASE + CCM_PDR4);
+ r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
- writel(r, IMX_CCM_BASE + CCM_PDR4);
+ writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
r = STACK_BASE + STACK_SIZE - 12;
@@ -58,7 +58,7 @@ static void __bare_init __naked insdram(void)
void __bare_init __naked board_init_lowlevel(void)
{
uint32_t r, s;
- unsigned long ccm_base = IMX_CCM_BASE;
+ unsigned long ccm_base = MX35_CCM_BASE_ADDR;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
@@ -125,9 +125,9 @@ void __bare_init __naked board_init_lowlevel(void)
r |= 0x03000000;
writel(r, ccm_base + CCM_CGR2);
- r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL);
+ r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
r |= 0x1000;
- writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL);
+ writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -143,22 +143,22 @@ void __bare_init __naked board_init_lowlevel(void)
writel(0x0009572B, ESDCFG0);
writel(0x92220000, ESDCTL0);
- writeb(0xda, IMX_SDRAM_CS0 + 0x400);
+ writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400);
writel(0xA2220000, ESDCTL0);
- writeb(0xda, IMX_SDRAM_CS0);
- writeb(0xda, IMX_SDRAM_CS0);
+ writeb(0xda, MX35_CSD0_BASE_ADDR);
+ writeb(0xda, MX35_CSD0_BASE_ADDR);
writel(0xB2220000, ESDCTL0);
- writeb(0xda, IMX_SDRAM_CS0 + 0x33);
- writeb(0xda, IMX_SDRAM_CS0 + 0x2000000);
+ writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33);
+ writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000);
writel(0x82228080, ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+ if (r < MX35_NFC_BASE_ADDR || r > MX35_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
- src = (unsigned int *)IMX_NFC_BASE;
+ src = (unsigned int *)MX35_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index 199841f..3d4a9cf 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -128,8 +128,8 @@ static void set_board_rev(int rev)
static int f3s_mem_init(void)
{
- arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
- arm_add_mem_device("ram1", IMX_SDRAM_CS1, 128 * 1024 * 1024);
+ arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, 128 * 1024 * 1024);
+ arm_add_mem_device("ram1", MX35_CSD1_BASE_ADDR, 128 * 1024 * 1024);
return 0;
}
@@ -144,7 +144,7 @@ static int f3s_devices_init(void)
writel(0x10000d03, CSCR_L(0));
writel(0x00720900, CSCR_A(0));
- reg = readl(IMX_CCM_BASE + CCM_RCSR);
+ reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
@@ -155,7 +155,7 @@ static int f3s_devices_init(void)
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
- add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 64 * 1024 * 1024, 0);
+ add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0);
switch ((reg >> 25) & 0x3) {
case 0x01: /* NAND is the source */
@@ -178,7 +178,7 @@ static int f3s_devices_init(void)
imx35_add_i2c0(NULL);
imx35_add_fec(&fec_info);
- add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, IMX_CS5_BASE, IMX_CS5_RANGE,
+ add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX35_CS5_BASE_ADDR, MX35_CS5_SIZE,
IORESOURCE_MEM, NULL);
imx35_add_mmc0(NULL);
@@ -283,66 +283,66 @@ static int f3s_core_init(void)
writel(0x22220A00, CSCR_A(5));
/* enable clock for I2C1 and FEC */
- reg = readl(IMX_CCM_BASE + CCM_CGR1);
+ reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
reg |= 0x3 << CCM_CGR1_I2C1_SHIFT;
- reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
+ reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
- writel(0x77777777, IMX_AIPS1_BASE);
- writel(0x77777777, IMX_AIPS1_BASE + 0x4);
- writel(0x77777777, IMX_AIPS2_BASE);
- writel(0x77777777, IMX_AIPS2_BASE + 0x4);
+ writel(0x77777777, MX35_AIPS1_BASE_ADDR);
+ writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
+ writel(0x77777777, MX35_AIPS2_BASE_ADDR);
+ writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
- writel(0x0, IMX_AIPS1_BASE + 0x40);
- writel(0x0, IMX_AIPS1_BASE + 0x44);
- writel(0x0, IMX_AIPS1_BASE + 0x48);
- writel(0x0, IMX_AIPS1_BASE + 0x4C);
- reg = readl(IMX_AIPS1_BASE + 0x50);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
+ reg = readl(MX35_AIPS1_BASE_ADDR + 0x50);
reg &= 0x00FFFFFF;
- writel(reg, IMX_AIPS1_BASE + 0x50);
+ writel(reg, MX35_AIPS1_BASE_ADDR + 0x50);
- writel(0x0, IMX_AIPS2_BASE + 0x40);
- writel(0x0, IMX_AIPS2_BASE + 0x44);
- writel(0x0, IMX_AIPS2_BASE + 0x48);
- writel(0x0, IMX_AIPS2_BASE + 0x4C);
- reg = readl(IMX_AIPS2_BASE + 0x50);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
+ reg = readl(MX35_AIPS2_BASE_ADDR + 0x50);
reg &= 0x00FFFFFF;
- writel(reg, IMX_AIPS2_BASE + 0x50);
+ writel(reg, MX35_AIPS2_BASE_ADDR + 0x50);
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
#define MAX_PARAM1 0x00302154
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
/* SGPCR - always park on last master */
- writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
- writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
- writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
- writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
- writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */
/* MGPCR - restore default values */
- writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
- writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
- writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
- writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
- writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
- writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */
return 0;
}
diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
index d1be7e8..f5f0998 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
@@ -52,7 +52,7 @@ CCM_PDR0_W: .word 0x00001000
MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
PPCTL_PARAM_W: .word PPCTL_PARAM_300
-CCM_BASE_ADDR_W: .word IMX_CCM_BASE
+CCM_BASE_ADDR_W: .word MX35_CCM_BASE_ADDR
.globl board_init_lowlevel
board_init_lowlevel:
@@ -155,8 +155,8 @@ board_init_lowlevel:
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
- ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
- ldr r2, =IMX_NFC_BASE + 0x800 /* end of NFC SRAM */
+ ldr r0, =MX35_NFC_BASE_ADDR /* start of NFC SRAM */
+ ldr r2, =MX35_NFC_BASE_ADDR + 0x800 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
index d5f2291..977d71c 100644
--- a/arch/arm/boards/guf-cupid/board.c
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -95,7 +95,7 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = {
static int cupid_mem_init(void)
{
- arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
+ arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, 128 * 1024 * 1024);
return 0;
}
@@ -116,7 +116,7 @@ static int cupid_devices_init(void)
gpio_direction_output(GPIO_LCD_ENABLE, 0);
gpio_direction_output(GPIO_LCD_BACKLIGHT, 0);
- reg = readl(IMX_CCM_BASE + CCM_RCSR);
+ reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
@@ -250,56 +250,56 @@ static int cupid_core_setup(void)
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
- writel(0x77777777, IMX_AIPS1_BASE);
- writel(0x77777777, IMX_AIPS1_BASE + 0x4);
- writel(0x77777777, IMX_AIPS2_BASE);
- writel(0x77777777, IMX_AIPS2_BASE + 0x4);
+ writel(0x77777777, MX35_AIPS1_BASE_ADDR);
+ writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
+ writel(0x77777777, MX35_AIPS2_BASE_ADDR);
+ writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
- writel(0x0, IMX_AIPS1_BASE + 0x40);
- writel(0x0, IMX_AIPS1_BASE + 0x44);
- writel(0x0, IMX_AIPS1_BASE + 0x48);
- writel(0x0, IMX_AIPS1_BASE + 0x4C);
- tmp = readl(IMX_AIPS1_BASE + 0x50);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
+ tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50);
tmp &= 0x00FFFFFF;
- writel(tmp, IMX_AIPS1_BASE + 0x50);
+ writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50);
- writel(0x0, IMX_AIPS2_BASE + 0x40);
- writel(0x0, IMX_AIPS2_BASE + 0x44);
- writel(0x0, IMX_AIPS2_BASE + 0x48);
- writel(0x0, IMX_AIPS2_BASE + 0x4C);
- tmp = readl(IMX_AIPS2_BASE + 0x50);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
+ tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50);
tmp &= 0x00FFFFFF;
- writel(tmp, IMX_AIPS2_BASE + 0x50);
+ writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50);
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
#define MAX_PARAM1 0x00302154
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
/* SGPCR - always park on last master */
- writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
- writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
- writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
- writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
- writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */
/* MGPCR - restore default values */
- writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
- writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
- writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
- writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
- writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
- writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */
writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */
writel(0x444A4541, CSCR_L(0));
@@ -318,7 +318,7 @@ static int cupid_core_setup(void)
* ------------
* 0x00000040
*/
- writel(0x40, IMX_M3IF_BASE);
+ writel(0x40, MX35_M3IF_BASE_ADDR);
return 0;
}
@@ -339,10 +339,10 @@ static int do_cpufreq(int argc, char *argv[])
switch (freq) {
case 399:
- writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
+ writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
break;
case 532:
- writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
index 0f7d753..0160144 100644
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -47,10 +47,10 @@ static void __bare_init __naked insdram(void)
uint32_t r;
/* Speed up NAND controller by adjusting the NFC divider */
- r = readl(IMX_CCM_BASE + CCM_PDR4);
+ r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
- writel(r, IMX_CCM_BASE + CCM_PDR4);
+ writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
r = STACK_BASE + STACK_SIZE - 12;
@@ -65,7 +65,7 @@ static void __bare_init __naked insdram(void)
static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_addr)
{
volatile int loop;
- void *r9 = (void *)IMX_SDRAM_CS0;
+ void *r9 = (void *)MX35_CSD0_BASE_ADDR;
u32 r11 = 0xda; /* dummy constant */
u32 r1, r0;
@@ -246,7 +246,7 @@ void __bare_init __naked board_init_lowlevel(void)
#define WDOG_WMCR 0x8
/* silence reset WDOG */
- writew(0, IMX_WDOG_BASE + WDOG_WMCR);
+ writew(0, MX35_WDOG_BASE_ADDR + WDOG_WMCR);
/* Skip SDRAM initialization if we run from RAM */
r0 = get_pc();
@@ -296,27 +296,27 @@ void __bare_init __naked board_init_lowlevel(void)
/* Configure clocks */
/* setup cpu/bus clocks */
- writel(0x003f4208, IMX_CCM_BASE + CCM_CCMR);
+ writel(0x003f4208, MX35_CCM_BASE_ADDR + CCM_CCMR);
/* configure MPLL */
- writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
/* configure PPLL */
- writel(PPCTL_PARAM_300, IMX_CCM_BASE + CCM_PPCTL);
+ writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + CCM_PPCTL);
/* configure core dividers */
r0 = PDR0_CCM_PER_AHB(1) | PDR0_HSP_PODF(2);
- writel(r0, IMX_CCM_BASE + CCM_PDR0);
+ writel(r0, MX35_CCM_BASE_ADDR + CCM_PDR0);
/* configure clock-gates */
- r0 = readl(IMX_CCM_BASE + CCM_CGR0);
+ r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR0);
r0 |= 0x00300000;
- writel(r0, IMX_CCM_BASE + CCM_CGR0);
+ writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR0);
- r0 = readl(IMX_CCM_BASE + CCM_CGR1);
+ r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
r0 |= 0x00000c03;
- writel(r0, IMX_CCM_BASE + CCM_CGR1);
+ writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR1);
/* Configure SDRAM */
/* Try 32-Bit 256 MB DDR memory */
@@ -326,10 +326,10 @@ void __bare_init __naked board_init_lowlevel(void)
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r0 = get_pc();
- if (r0 < IMX_NFC_BASE || r0 > IMX_NFC_BASE + 0x800)
+ if (r0 < MX35_NFC_BASE_ADDR || r0 > MX35_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
- src = (unsigned int *)IMX_NFC_BASE;
+ src = (unsigned int *)MX35_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c
index 32d12dd..cff7330 100644
--- a/arch/arm/boards/pcm043/lowlevel.c
+++ b/arch/arm/boards/pcm043/lowlevel.c
@@ -45,10 +45,10 @@ static void __bare_init __naked insdram(void)
uint32_t r;
/* Speed up NAND controller by adjusting the NFC divider */
- r = readl(IMX_CCM_BASE + CCM_PDR4);
+ r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
- writel(r, IMX_CCM_BASE + CCM_PDR4);
+ writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
r = STACK_BASE + STACK_SIZE - 12;
@@ -63,8 +63,8 @@ static void __bare_init __naked insdram(void)
void __bare_init __naked board_init_lowlevel(void)
{
uint32_t r, s;
- unsigned long ccm_base = IMX_CCM_BASE;
- unsigned long iomuxc_base = IMX_IOMUXC_BASE;
+ unsigned long ccm_base = MX35_CCM_BASE_ADDR;
+ unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
@@ -115,7 +115,7 @@ void __bare_init __naked board_init_lowlevel(void)
writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL);
/* Check silicon revision and use 532MHz if >=2.1 */
- r = readl(IMX_IIM_BASE + 0x24);
+ r = readl(MX35_IIM_BASE_ADDR + 0x24);
if (r >= IMX35_CHIP_REVISION_2_1)
writel(CCM_PDR0_532, ccm_base + CCM_PDR0);
else
@@ -130,9 +130,9 @@ void __bare_init __naked board_init_lowlevel(void)
r |= 0x00000003;
writel(r, ccm_base + CCM_CGR1);
- r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL);
+ r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
r |= 0x1000;
- writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL);
+ writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -158,7 +158,7 @@ void __bare_init __naked board_init_lowlevel(void)
/* select Precharge-All mode */
writel(0x92220000, ESDCTL0);
/* Precharge-All */
- writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
+ writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400);
/* select Load-Mode-Register mode */
writel(0xB8001000, ESDCTL0);
@@ -174,13 +174,13 @@ void __bare_init __naked board_init_lowlevel(void)
/* select Precharge-All mode */
writel(0x92220000, ESDCTL0);
/* Precharge-All */
- writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
+ writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400);
/* select Manual-Refresh mode */
writel(0xA2220000, ESDCTL0);
/* Manual-Refresh 2 times */
- writel(0x87654321, IMX_SDRAM_CS0);
- writel(0x87654321, IMX_SDRAM_CS0);
+ writel(0x87654321, MX35_CSD0_BASE_ADDR);
+ writel(0x87654321, MX35_CSD0_BASE_ADDR);
/* select Load-Mode-Register mode */
writel(0xB2220000, ESDCTL0);
@@ -205,10 +205,10 @@ void __bare_init __naked board_init_lowlevel(void)
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+ if (r < MX35_NFC_BASE_ADDR || r > MX35_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
- src = (unsigned int *)IMX_NFC_BASE;
+ src = (unsigned int *)MX35_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 3170161..3b4ec77 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -93,13 +93,13 @@ static struct fb_videomode pcm043_fb_mode[] = {
static struct imx_ipu_fb_platform_data ipu_fb_data = {
.mode = pcm043_fb_mode,
.num_modes = ARRAY_SIZE(pcm043_fb_mode),
- .framebuffer_ovl = (void *) (IMX_SDRAM_CS0 + SZ_128M - SZ_1M),
+ .framebuffer_ovl = (void *) (MX35_CSD0_BASE_ADDR + SZ_128M - SZ_1M),
.bpp = 16,
};
static int pcm043_mem_init(void)
{
- arm_add_mem_device("ram0", IMX_SDRAM_CS0, SZ_128M);
+ arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, SZ_128M);
return 0;
}
@@ -128,7 +128,7 @@ static int imx35_devices_init(void)
led_gpio_register(&led0);
- reg = readl(IMX_CCM_BASE + CCM_RCSR);
+ reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
@@ -144,7 +144,7 @@ static int imx35_devices_init(void)
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
- add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
+ add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
if ((reg & 0xc00) == 0x800) { /* reset mode: external boot */
switch ( (reg >> 25) & 0x3) {
@@ -224,56 +224,56 @@ static int pcm043_core_setup(void)
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
- writel(0x77777777, IMX_AIPS1_BASE);
- writel(0x77777777, IMX_AIPS1_BASE + 0x4);
- writel(0x77777777, IMX_AIPS2_BASE);
- writel(0x77777777, IMX_AIPS2_BASE + 0x4);
+ writel(0x77777777, MX35_AIPS1_BASE_ADDR);
+ writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
+ writel(0x77777777, MX35_AIPS2_BASE_ADDR);
+ writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
- writel(0x0, IMX_AIPS1_BASE + 0x40);
- writel(0x0, IMX_AIPS1_BASE + 0x44);
- writel(0x0, IMX_AIPS1_BASE + 0x48);
- writel(0x0, IMX_AIPS1_BASE + 0x4C);
- tmp = readl(IMX_AIPS1_BASE + 0x50);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
+ writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
+ tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50);
tmp &= 0x00FFFFFF;
- writel(tmp, IMX_AIPS1_BASE + 0x50);
+ writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50);
- writel(0x0, IMX_AIPS2_BASE + 0x40);
- writel(0x0, IMX_AIPS2_BASE + 0x44);
- writel(0x0, IMX_AIPS2_BASE + 0x48);
- writel(0x0, IMX_AIPS2_BASE + 0x4C);
- tmp = readl(IMX_AIPS2_BASE + 0x50);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
+ writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
+ tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50);
tmp &= 0x00FFFFFF;
- writel(tmp, IMX_AIPS2_BASE + 0x50);
+ writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50);
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
#define MAX_PARAM1 0x00302154
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
- writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
+ writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
/* SGPCR - always park on last master */
- writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
- writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
- writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
- writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
- writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */
+ writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */
/* MGPCR - restore default values */
- writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
- writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
- writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
- writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
- writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
- writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */
+ writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */
/*
* M3IF Control Register (M3IFCTL)
@@ -288,7 +288,7 @@ static int pcm043_core_setup(void)
* ------------
* 0x00000040
*/
- writel(0x40, IMX_M3IF_BASE);
+ writel(0x40, MX35_M3IF_BASE_ADDR);
return 0;
}
@@ -309,10 +309,10 @@ static int do_cpufreq(int argc, char *argv[])
switch (freq) {
case 399:
- writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
+ writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
break;
case 532:
- writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 579e148..2e94f17 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -22,7 +22,7 @@
int imx_silicon_revision()
{
uint32_t reg;
- reg = readl(IMX_IIM_BASE + IIM_SREV);
+ reg = readl(MX35_IIM_BASE_ADDR + IIM_SREV);
/* 0×00 = TO 1.0, First silicon */
reg += IMX_CHIP_REV_1_0;
@@ -41,7 +41,7 @@ int imx_silicon_revision()
static int imx35_l2_fix(void)
{
- writel(0x515, IMX_CLKCTL_BASE + L2_MEM_VAL);
+ writel(0x515, MX35_CLKCTL_BASE_ADDR + L2_MEM_VAL);
return 0;
}
@@ -49,13 +49,13 @@ core_initcall(imx35_l2_fix);
static int imx35_init(void)
{
- add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
+ add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpt", 0, NULL, 0x53f90000, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpt", 0, NULL, MX35_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 0, NULL, MX35_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 1, NULL, MX35_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 2, NULL, MX35_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h
index 9ecaa35..27c49e7 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx35.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx35.h
@@ -3,60 +3,70 @@
static inline struct device_d *imx35_add_i2c0(struct i2c_platform_data *pdata)
{
- return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata);
+ return imx_add_i2c((void *)MX35_I2C1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx35_add_i2c1(struct i2c_platform_data *pdata)
{
- return imx_add_i2c((void *)IMX_I2C2_BASE, 1, pdata);
+ return imx_add_i2c((void *)MX35_I2C2_BASE_ADDR, 1, pdata);
}
static inline struct device_d *imx35_add_i2c2(struct i2c_platform_data *pdata)
{
- return imx_add_i2c((void *)IMX_I2C3_BASE, 2, pdata);
+ return imx_add_i2c((void *)MX35_I2C3_BASE_ADDR, 2, pdata);
}
static inline struct device_d *imx35_add_spi0(struct spi_imx_master *pdata)
{
- return imx_add_spi((void *)IMX_CSPI1_BASE, 0, pdata);
+ return imx_add_spi((void *)MX35_CSPI1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx35_add_spi(struct spi_imx_master *pdata)
+{
+ return imx_add_spi((void *)MX35_CSPI2_BASE_ADDR, 1, pdata);
}
static inline struct device_d *imx35_add_uart0(void)
{
- return imx_add_uart((void *)IMX_UART1_BASE, 0);
+ return imx_add_uart((void *)MX35_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx35_add_uart1(void)
{
- return imx_add_uart((void *)IMX_UART2_BASE, 1);
+ return imx_add_uart((void *)MX35_UART2_BASE_ADDR, 1);
+}
+
+static inline struct device_d *imx35_add_uart2(void)
+{
+ return imx_add_uart((void *)MX35_UART3_BASE_ADDR, 2);
}
static inline struct device_d *imx35_add_nand(struct imx_nand_platform_data *pdata)
{
- return imx_add_nand((void *)IMX_NFC_BASE, pdata);
+ return imx_add_nand((void *)MX35_NFC_BASE_ADDR, pdata);
}
static inline struct device_d *imx35_add_fb(struct imx_ipu_fb_platform_data *pdata)
{
- return imx_add_ipufb((void *)IMX_IPU_BASE, pdata);
+ return imx_add_ipufb((void *)MX35_IPU_CTRL_BASE_ADDR, pdata);
}
static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata)
{
- return imx_add_fec((void *)IMX_FEC_BASE, pdata);
+ return imx_add_fec((void *)MX35_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx35_add_mmc0(struct esdhc_platform_data *pdata)
{
- return imx_add_esdhc((void *)IMX_SDHC1_BASE, 0, pdata);
+ return imx_add_esdhc((void *)MX35_ESDHC1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx35_add_mmc1(struct esdhc_platform_data *pdata)
{
- return imx_add_esdhc((void *)IMX_SDHC2_BASE, 1, pdata);
+ return imx_add_esdhc((void *)MX35_ESDHC2_BASE_ADDR, 1, pdata);
}
static inline struct device_d *imx35_add_mmc2(struct esdhc_platform_data *pdata)
{
- return imx_add_esdhc((void *)IMX_SDHC3_BASE, 2, pdata);
+ return imx_add_esdhc((void *)MX35_ESDHC3_BASE_ADDR, 2, pdata);
}
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 5a4ab90..0a4f423 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -19,6 +19,8 @@
#ifndef __ASM_ARCH_MX35_REGS_H
#define __ASM_ARCH_MX35_REGS_H
+#include <sizes.h>
+
/*
* sanity check
*/
@@ -26,32 +28,121 @@
# error "Please do not include directly. Use imx-regs.h instead."
#endif
-#define IMX_L2CC_BASE 0x30000000
-#define IMX_CLKCTL_BASE 0x43F0C000
-#define IMX_UART1_BASE 0x43F90000
-#define IMX_UART2_BASE 0x43F94000
-#define IMX_TIM1_BASE 0x53F90000
-#define IMX_IOMUXC_BASE 0x43FAC000
-#define IMX_WDT_BASE 0x53FDC000
-#define IMX_MAX_BASE 0x43F04000
-#define IMX_ESD_BASE 0xb8001000
-#define IMX_AIPS1_BASE 0x43F00000
-#define IMX_AIPS2_BASE 0x53F00000
-#define IMX_CCM_BASE 0x53F80000
-#define IMX_IIM_BASE 0x53FF0000
-#define IMX_M3IF_BASE 0xB8003000
-#define IMX_NFC_BASE 0xBB000000
-#define IMX_FEC_BASE 0x50038000
-#define IMX_I2C1_BASE 0x43F80000
-#define IMX_I2C2_BASE 0x43F98000
-#define IMX_I2C3_BASE 0x43F84000
-#define IMX_CSPI1_BASE 0x43FA4000
-#define IMX_SDHC1_BASE 0x53FB4000
-#define IMX_SDHC2_BASE 0x53FB8000
-#define IMX_SDHC3_BASE 0x53FBC000
-#define IMX_IPU_BASE 0x53FC0000
-#define IMX_OTG_BASE 0x53FF4000
-#define IMX_WDOG_BASE 0x53fdc000
+#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
+#define MX35_IRAM_SIZE SZ_128K
+
+#define MX35_L2CC_BASE_ADDR 0x30000000
+#define MX35_L2CC_SIZE SZ_1M
+
+#define MX35_AIPS1_BASE_ADDR 0x43f00000
+#define MX35_AIPS1_SIZE SZ_1M
+#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
+#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
+#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
+#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
+#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
+#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
+#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
+#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
+#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
+#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
+#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
+#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
+#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
+#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
+#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
+#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
+#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
+
+#define MX35_SPBA0_BASE_ADDR 0x50000000
+#define MX35_SPBA0_SIZE SZ_1M
+#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
+#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
+#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
+#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
+#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
+#define MX35_FEC_BASE_ADDR 0x50038000
+#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
+
+#define MX35_AIPS2_BASE_ADDR 0x53f00000
+#define MX35_AIPS2_SIZE SZ_1M
+#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
+#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
+#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
+#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
+#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
+#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
+#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
+#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
+#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
+#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
+#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
+#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
+#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
+#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
+#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
+#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
+#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
+#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
+#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
+#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
+#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
+#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
+#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
+
+/*
+ * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
+ * HS. When host support was implemented only a preliminary document was
+ * available, which told 0x400. This works fine.
+ */
+#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
+
+#define MX35_ROMP_BASE_ADDR 0x60000000
+#define MX35_ROMP_SIZE SZ_1M
+
+#define MX35_AVIC_BASE_ADDR 0x68000000
+#define MX35_AVIC_SIZE SZ_1M
+
+/*
+ * Memory regions and CS
+ */
+#define MX35_IPU_MEM_BASE_ADDR 0x70000000
+#define MX35_CSD0_BASE_ADDR 0x80000000
+#define MX35_CSD1_BASE_ADDR 0x90000000
+
+#define MX35_CS0_BASE_ADDR 0xa0000000
+#define MX35_CS1_BASE_ADDR 0xa8000000
+#define MX35_CS2_BASE_ADDR 0xb0000000
+#define MX35_CS3_BASE_ADDR 0xb2000000
+
+#define MX35_CS4_BASE_ADDR 0xb4000000
+#define MX35_CS4_SIZE SZ_32M
+
+#define MX35_CS5_BASE_ADDR 0xb6000000
+#define MX35_CS5_SIZE SZ_32M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MX35_X_MEMC_BASE_ADDR 0xb8000000
+#define MX35_X_MEMC_SIZE SZ_64K
+#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
+#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
+#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
+#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
+#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
+
+#define MX35_NFC_BASE_ADDR 0xbb000000
+#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
+
+/* FIXME: Get rid of these */
+#define IMX_WDT_BASE MX35_WDOG_BASE_ADDR
+#define IMX_TIM1_BASE MX35_GPT1_BASE_ADDR
+#define IMX_ESD_BASE MX35_ESDCTL_BASE_ADDR
+#define IMX_IOMUXC_BASE MX35_IOMUXC_BASE_ADDR
+#define IMX_CCM_BASE MX35_CCM_BASE_ADDR
/*
* Clock Controller Module (CCM)
@@ -88,25 +179,6 @@
#define PDR0_AUTO_CON (1 << 0)
#define PDR0_PER_SEL (1 << 26)
-/*
- * Adresses and ranges of the external chip select lines
- */
-#define IMX_CS0_BASE 0xA0000000
-#define IMX_CS0_RANGE (128 * 1024 * 1024)
-#define IMX_CS1_BASE 0xA8000000
-#define IMX_CS1_RANGE (128 * 1024 * 1024)
-#define IMX_CS2_BASE 0xB0000000
-#define IMX_CS2_RANGE (32 * 1024 * 1024)
-#define IMX_CS3_BASE 0xB2000000
-#define IMX_CS3_RANGE (32 * 1024 * 1024)
-#define IMX_CS4_BASE 0xB4000000
-#define IMX_CS4_RANGE (32 * 1024 * 1024)
-#define IMX_CS5_BASE 0xB6000000
-#define IMX_CS5_RANGE (32 * 1024 * 1024)
-
-#define IMX_SDRAM_CS0 0x80000000
-#define IMX_SDRAM_CS1 0x90000000
-
#define WEIM_BASE 0xb8002000
#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c
index a4e0120..a8063f2 100644
--- a/arch/arm/mach-imx/speed-imx35.c
+++ b/arch/arm/mach-imx/speed-imx35.c
@@ -21,13 +21,13 @@
unsigned long imx_get_mpllclk(void)
{
- ulong mpctl = readl(IMX_CCM_BASE + CCM_MPCTL);
+ ulong mpctl = readl(MX35_CCM_BASE_ADDR + CCM_MPCTL);
return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ);
}
static unsigned long imx_get_ppllclk(void)
{
- ulong ppctl = readl(IMX_CCM_BASE + CCM_PPCTL);
+ ulong ppctl = readl(MX35_CCM_BASE_ADDR + CCM_PPCTL);
return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ);
}
@@ -56,7 +56,7 @@ static struct arm_ahb_div clk_consumer[] = {
static unsigned long imx_get_armclk(void)
{
- unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
+ unsigned long pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
struct arm_ahb_div *aad;
unsigned long fref = imx_get_mpllclk();
@@ -70,7 +70,7 @@ static unsigned long imx_get_armclk(void)
unsigned long imx_get_ahbclk(void)
{
- unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
+ unsigned long pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
struct arm_ahb_div *aad;
unsigned long fref = imx_get_mpllclk();
@@ -100,8 +100,8 @@ static unsigned long get_6_div(unsigned long in)
static unsigned long imx_get_ipg_perclk(void)
{
- ulong pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
- ulong pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
+ ulong pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
+ ulong pdr4 = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
ulong div;
ulong fref;
@@ -129,7 +129,7 @@ unsigned long imx_get_gptclk(void)
*/
unsigned long imx_get_lcdclk(void)
{
- unsigned long hsp_podf = (readl(IMX_CCM_BASE + CCM_PDR0) >> 20) & 0x03;
+ unsigned long hsp_podf = (readl(MX35_CCM_BASE_ADDR + CCM_PDR0) >> 20) & 0x03;
unsigned long base_clk = imx_get_armclk();
if (base_clk > 400 * 1000 * 1000) {
@@ -156,8 +156,8 @@ unsigned long imx_get_lcdclk(void)
unsigned long imx_get_uartclk(void)
{
- unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);
- unsigned long pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
+ unsigned long pdr3 = readl(MX35_CCM_BASE_ADDR + CCM_PDR3);
+ unsigned long pdr4 = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
unsigned long div = get_3_3_div(pdr4 >> 10);
if (pdr3 & (1 << 14))
@@ -169,7 +169,7 @@ unsigned long imx_get_uartclk(void)
/* mmc0 clk only */
unsigned long imx_get_mmcclk(void)
{
- unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);
+ unsigned long pdr3 = readl(MX35_CCM_BASE_ADDR + CCM_PDR3);
unsigned long div = get_6_div(pdr3);
if (pdr3 & (1 << 6))
@@ -213,7 +213,7 @@ void imx_dump_clocks(void)
*/
int imx_clko_set_div(int num, int div)
{
- unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR);
+ unsigned long cosr = readl(MX35_CCM_BASE_ADDR + CCM_COSR);
if (num != 1)
return -ENODEV;
@@ -224,7 +224,7 @@ int imx_clko_set_div(int num, int div)
cosr &= ~(0x3f << 10);
cosr |= div << 10;
- writel(cosr, IMX_CCM_BASE + CCM_COSR);
+ writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
return div + 1;
}
@@ -234,14 +234,14 @@ int imx_clko_set_div(int num, int div)
*/
void imx_clko_set_src(int num, int src)
{
- unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR);
+ unsigned long cosr = readl(MX35_CCM_BASE_ADDR + CCM_COSR);
if (num != 1)
return;
if (src < 0) {
cosr &= ~(1 << 5);
- writel(cosr, IMX_CCM_BASE + CCM_COSR);
+ writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
return;
}
@@ -250,6 +250,6 @@ void imx_clko_set_src(int num, int src)
cosr &= ~(1 << 6);
cosr |= src & 0x1f;
- writel(cosr, IMX_CCM_BASE + CCM_COSR);
+ writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
}
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 03/14] ARM i.MX21: give register base addresses a proper MX21_ prefix
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
2012-09-24 10:46 ` [PATCH 01/14] ARM i.MX31: give register base addresses a proper MX31_ prefix Sascha Hauer
2012-09-24 10:46 ` [PATCH 02/14] ARM i.MX35: give register base addresses a proper MX35_ prefix Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 04/14] ARM i.MX1: give register base addresses a proper MX1_ prefix Sascha Hauer
` (10 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/imx21ads/imx21ads.c | 6 +-
arch/arm/boards/imx21ads/lowlevel_init.S | 4 +-
arch/arm/mach-imx/imx21.c | 16 +--
arch/arm/mach-imx/include/mach/devices-imx21.h | 8 +-
arch/arm/mach-imx/include/mach/imx21-regs.h | 179 +++++++++++++++---------
5 files changed, 132 insertions(+), 81 deletions(-)
diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c
index 1aecf18..42b0162 100644
--- a/arch/arm/boards/imx21ads/imx21ads.c
+++ b/arch/arm/boards/imx21ads/imx21ads.c
@@ -163,9 +163,11 @@ static int mx21ads_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
- add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC8000000, 32 * 1024 * 1024, 0);
+ add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX21_CS0_BASE_ADDR,
+ 32 * 1024 * 1024, 0);
imx21_add_nand(&nand_info);
- add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL, IMX_CS1_BASE, 0x1000,
+ add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL,
+ MX21_CS1_BASE_ADDR, 0x1000,
IORESOURCE_MEM, NULL);
imx21_add_fb(&imx_fb_data);
diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S
index 961029b..03b62df 100644
--- a/arch/arm/boards/imx21ads/lowlevel_init.S
+++ b/arch/arm/boards/imx21ads/lowlevel_init.S
@@ -120,8 +120,8 @@ board_init_lowlevel:
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
- ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
- ldr r2, =IMX_NFC_BASE + 0x800 /* end of NFC SRAM */
+ ldr r0, =MX21_NFC_BASE_ADDR /* start of NFC SRAM */
+ ldr r2, =MX21_NFC_BASE_ADDR + 0x800 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c
index df3eaf2..8d909ce 100644
--- a/arch/arm/mach-imx/imx21.c
+++ b/arch/arm/mach-imx/imx21.c
@@ -25,14 +25,14 @@ int imx_silicon_revision(void)
static int imx21_init(void)
{
- add_generic_device("imx1-gpt", 0, NULL, 0x10003000, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 0, NULL, 0x10015000, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 1, NULL, 0x10015100, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 2, NULL, 0x10015200, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 3, NULL, 0x10015300, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 4, NULL, 0x10015400, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 5, NULL, 0x10015500, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpt", 0, NULL, MX21_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 0, NULL, MX21_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 1, NULL, MX21_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 2, NULL, MX21_GPIO3_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 3, NULL, MX21_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 4, NULL, MX21_GPIO5_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx-gpio", 5, NULL, MX21_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
return 0;
}
-coredevice_initcall(imx21_init);
+postcore_initcall(imx21_init);
diff --git a/arch/arm/mach-imx/include/mach/devices-imx21.h b/arch/arm/mach-imx/include/mach/devices-imx21.h
index 1e1fbbd..31c5f8c 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx21.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx21.h
@@ -3,22 +3,22 @@
static inline struct device_d *imx21_add_uart0(void)
{
- return imx_add_uart((void *)IMX_UART1_BASE, 0);
+ return imx_add_uart((void *)MX21_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx21_add_uart1(void)
{
- return imx_add_uart((void *)IMX_UART2_BASE, 1);
+ return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx21_add_uart2(void)
{
- return imx_add_uart((void *)IMX_UART3_BASE, 2);
+ return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 2);
}
static inline struct device_d *imx21_add_uart3(void)
{
- return imx_add_uart((void *)IMX_UART4_BASE, 3);
+ return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 3);
}
static inline struct device_d *imx21_add_nand(struct imx_nand_platform_data *pdata)
diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h
index 98e73ef..e58af72 100644
--- a/arch/arm/mach-imx/include/mach/imx21-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx21-regs.h
@@ -5,40 +5,96 @@
#error "Please do not include directly"
#endif
-#define IMX_IO_BASE 0x10000000
-
-#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
-#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
-#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
-#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
-#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
-#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE)
-#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
-#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
-#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
-#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
-#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
-#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
-#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
-
-#define IMX_SDRAM_BASE (0xdf000000)
-#define IMX_EIM_BASE (0xdf001000)
-#define IMX_NFC_BASE (0xdf003000)
+#define MX21_AIPI_BASE_ADDR 0x10000000
+#define MX21_AIPI_SIZE SZ_1M
+#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
+#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
+#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
+#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
+#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
+#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
+#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
+#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
+#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
+#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
+#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
+#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
+#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
+#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
+#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
+#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
+#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
+#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
+#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
+#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
+#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
+#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000)
+#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100)
+#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200)
+#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300)
+#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400)
+#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500)
+#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
+#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
+#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
+#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
+#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
+#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
+#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
+#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
+#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
+#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
+#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
+
+#define MX21_AVIC_BASE_ADDR 0x10040000
+
+#define MX21_SAHB1_BASE_ADDR 0x80000000
+#define MX21_SAHB1_SIZE SZ_1M
+#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
+
+/* Memory regions and CS */
+#define MX21_SDRAM_BASE_ADDR 0xc0000000
+#define MX21_CSD1_BASE_ADDR 0xc4000000
+
+#define MX21_CS0_BASE_ADDR 0xc8000000
+#define MX21_CS1_BASE_ADDR 0xcc000000
+#define MX21_CS2_BASE_ADDR 0xd0000000
+#define MX21_CS3_BASE_ADDR 0xd1000000
+#define MX21_CS4_BASE_ADDR 0xd2000000
+#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
+#define MX21_CS5_BASE_ADDR 0xdd000000
+
+/* NAND, SDRAM, WEIM etc controllers */
+#define MX21_X_MEMC_BASE_ADDR 0xdf000000
+#define MX21_X_MEMC_SIZE SZ_256K
+
+#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
+#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
+#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
+#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
+
+#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
+
+/* FIXME: Get rid of these */
+#define IMX_GPIO_BASE MX21_GPIO_BASE_ADDR
+#define IMX_TIM1_BASE MX21_GPT1_BASE_ADDR
+#define IMX_WDT_BASE MX21_WDOG_BASE_ADDR
+#define IMX_SYSTEM_CTL_BASE MX21_SYSCTRL_BASE_ADDR
/* AIPI */
-#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00)
-#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04)
-#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00)
-#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04)
+#define AIPI1_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x00)
+#define AIPI1_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x04)
+#define AIPI2_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x20000 + 0x00)
+#define AIPI2_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x20000 + 0x04)
/* System Control */
-#define SUID0 __REG(IMX_SYSTEM_CTL_BASE + 0x4) /* Silicon ID Register (12 bytes) */
-#define SUID1 __REG(IMX_SYSTEM_CTL_BASE + 0x8) /* Silicon ID Register (12 bytes) */
-#define CID __REG(IMX_SYSTEM_CTL_BASE + 0xC) /* Silicon ID Register (12 bytes) */
-#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14) /* Function Multeplexing Control Register */
-#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18) /* Global Peripheral Control Register */
-#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */
-#define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
+#define SUID0 __REG(MX21_SYSCTRL_BASE_ADDR + 0x4) /* Silicon ID Register (12 bytes) */
+#define SUID1 __REG(MX21_SYSCTRL_BASE_ADDR + 0x8) /* Silicon ID Register (12 bytes) */
+#define CID __REG(MX21_SYSCTRL_BASE_ADDR + 0xC) /* Silicon ID Register (12 bytes) */
+#define FMCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */
+#define GPCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */
+#define WBCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */
+#define DSCR(x) __REG(MX21_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
#define GPCR_BOOT_SHIFT 16
#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT)
@@ -51,39 +107,39 @@
#define GPCR_BOOT_8BIT_NAND_512 7
/* SDRAM Controller registers bitfields */
-#define SDCTL0 __REG(IMX_SDRAM_BASE + 0x00) /* SDRAM 0 Control Register */
-#define SDCTL1 __REG(IMX_SDRAM_BASE + 0x04) /* SDRAM 0 Control Register */
-#define SDRST __REG(IMX_SDRAM_BASE + 0x18) /* SDRAM Reset Register */
-#define SDMISC __REG(IMX_SDRAM_BASE + 0x14) /* SDRAM Miscellaneous Register */
+#define SDCTL0 __REG(MX21_X_MEMC_BASE_ADDR + 0x00) /* SDRAM 0 Control Register */
+#define SDCTL1 __REG(MX21_X_MEMC_BASE_ADDR + 0x04) /* SDRAM 0 Control Register */
+#define SDRST __REG(MX21_X_MEMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */
+#define SDMISC __REG(MX21_X_MEMC_BASE_ADDR + 0x14) /* SDRAM Miscellaneous Register */
/* Chip Select Registers */
-#define CS0U __REG(IMX_EIM_BASE + 0x00) /* Chip Select 0 Upper Register */
-#define CS0L __REG(IMX_EIM_BASE + 0x04) /* Chip Select 0 Lower Register */
-#define CS1U __REG(IMX_EIM_BASE + 0x08) /* Chip Select 1 Upper Register */
-#define CS1L __REG(IMX_EIM_BASE + 0x0C) /* Chip Select 1 Lower Register */
-#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
-#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
-#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
-#define CS3L __REG(IMX_EIM_BASE + 0x1C) /* Chip Select 3 Lower Register */
-#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
-#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
-#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
-#define CS5L __REG(IMX_EIM_BASE + 0x2C) /* Chip Select 5 Lower Register */
-#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
+#define CS0U __REG(MX21_EIM_BASE_ADDR + 0x00) /* Chip Select 0 Upper Register */
+#define CS0L __REG(MX21_EIM_BASE_ADDR + 0x04) /* Chip Select 0 Lower Register */
+#define CS1U __REG(MX21_EIM_BASE_ADDR + 0x08) /* Chip Select 1 Upper Register */
+#define CS1L __REG(MX21_EIM_BASE_ADDR + 0x0C) /* Chip Select 1 Lower Register */
+#define CS2U __REG(MX21_EIM_BASE_ADDR + 0x10) /* Chip Select 2 Upper Register */
+#define CS2L __REG(MX21_EIM_BASE_ADDR + 0x14) /* Chip Select 2 Lower Register */
+#define CS3U __REG(MX21_EIM_BASE_ADDR + 0x18) /* Chip Select 3 Upper Register */
+#define CS3L __REG(MX21_EIM_BASE_ADDR + 0x1C) /* Chip Select 3 Lower Register */
+#define CS4U __REG(MX21_EIM_BASE_ADDR + 0x20) /* Chip Select 4 Upper Register */
+#define CS4L __REG(MX21_EIM_BASE_ADDR + 0x24) /* Chip Select 4 Lower Register */
+#define CS5U __REG(MX21_EIM_BASE_ADDR + 0x28) /* Chip Select 5 Upper Register */
+#define CS5L __REG(MX21_EIM_BASE_ADDR + 0x2C) /* Chip Select 5 Lower Register */
+#define EIM __REG(MX21_EIM_BASE_ADDR + 0x30) /* EIM Configuration Register */
/* PLL registers */
-#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */
-#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */
-#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */
-#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
-#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */
-#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */
-#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */
-#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */
-#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */
-#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */
+#define CSCR __REG(MX21_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */
+#define MPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */
+#define MPCTL1 __REG(MX21_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */
+#define SPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */
+#define SPCTL1 __REG(MX21_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
+#define OSC26MCTL __REG(MX21_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */
+#define PCDR0 __REG(MX21_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */
+#define PCDR1 __REG(MX21_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */
+#define PCCR0 __REG(MX21_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */
+#define PCCR1 __REG(MX21_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */
+#define CCSR __REG(MX21_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */
#define CSCR_MPEN (1 << 0)
#define CSCR_SPEN (1 << 1)
@@ -107,11 +163,4 @@
#define CCSR_32K_SR (1 << 15)
-#define IMX_CS0_BASE 0xC8000000
-#define IMX_CS1_BASE 0xCC000000
-#define IMX_CS2_BASE 0xD0000000
-#define IMX_CS3_BASE 0xD1000000
-#define IMX_CS4_BASE 0xD2000000
-#define IMX_CS5_BASE 0xD3000000
-
#endif /* _IMX21_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 04/14] ARM i.MX1: give register base addresses a proper MX1_ prefix
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (2 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 03/14] ARM i.MX21: give register base addresses a proper MX21_ prefix Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 05/14] ARM i.MX27: give register base addresses a proper MX27_ prefix Sascha Hauer
` (9 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/imx1.c | 11 +-
arch/arm/mach-imx/include/mach/devices-imx1.h | 4 +-
arch/arm/mach-imx/include/mach/imx1-regs.h | 140 +++++++++++++++----------
3 files changed, 92 insertions(+), 63 deletions(-)
diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c
index b32e371..e6fba16 100644
--- a/arch/arm/mach-imx/imx1.c
+++ b/arch/arm/mach-imx/imx1.c
@@ -13,14 +13,15 @@
#include <common.h>
#include <init.h>
+#include <mach/imx-regs.h>
static int imx1_init(void)
{
- add_generic_device("imx1-gpt", 0, NULL, 0x00202000, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 0, NULL, 0x0021c000, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 1, NULL, 0x0021c100, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 2, NULL, 0x0021c200, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 3, NULL, 0x0021c300, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpt", 0, NULL, MX1_TIM1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpio", 0, NULL, MX1_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpio", 1, NULL, MX1_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpio", 2, NULL, MX1_GPIO3_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpio", 3, NULL, MX1_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx1.h b/arch/arm/mach-imx/include/mach/devices-imx1.h
index a45363f..c73113c 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx1.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx1.h
@@ -2,10 +2,10 @@
static inline struct device_d *imx1_add_uart0(void)
{
- return imx_add_uart((void *)IMX_UART1_BASE, 0);
+ return imx_add_uart((void *)MX1_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx1_add_uart1(void)
{
- return imx_add_uart((void *)IMX_UART2_BASE, 1);
+ return imx_add_uart((void *)MX1_UART2_BASE_ADDR, 1);
}
diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h
index d5ee3f5..52d2dfe 100644
--- a/arch/arm/mach-imx/include/mach/imx1-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx1-regs.h
@@ -5,77 +5,105 @@
#error "Please do not include directly"
#endif
-#define IMX_IO_BASE 0x00200000
+#define MX1_IO_BASE_ADDR 0x00200000
+#define MX1_IO_SIZE SZ_1M
+
+#define MX1_CS0_PHYS 0x10000000
+#define MX1_CS0_SIZE 0x02000000
+
+#define MX1_CS1_PHYS 0x12000000
+#define MX1_CS1_SIZE 0x01000000
+
+#define MX1_CS2_PHYS 0x13000000
+#define MX1_CS2_SIZE 0x01000000
+
+#define MX1_CS3_PHYS 0x14000000
+#define MX1_CS3_SIZE 0x01000000
+
+#define MX1_CS4_PHYS 0x15000000
+#define MX1_CS4_SIZE 0x01000000
+
+#define MX1_CS5_PHYS 0x16000000
+#define MX1_CS5_SIZE 0x01000000
/*
* Register BASEs, based on OFFSETs
*/
-#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
-#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
-#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
-#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
-#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
-#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
-#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
-#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
-#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
-#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
-#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
-#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
-#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
-#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
-#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
-#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
-#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
-#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
-#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
-#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
-#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
-#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
-#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)
-#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
-#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
-#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
-#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
-#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
-#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
+#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
+#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
+#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
+#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
+#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
+#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
+#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
+#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
+#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
+#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
+#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
+#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
+#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
+#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
+#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
+#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
+#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
+#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
+#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
+#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
+#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
+#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
+#define MX1_SCM_BASE_ADDR (0x1B800 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
+#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
+#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
+#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
+#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
+#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
+
+/* FIXME: get rid of these */
+#define IMX_TIM1_BASE MX1_CCM_BASE_ADDR
+#define IMX_WDT_BASE MX1_WDT_BASE_ADDR
+#define IMX_GPIO_BASE MX1_GPIO_BASE_ADDR
/* SYSCTRL Registers */
-#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
-#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
-#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
+#define SIDR __REG(MX1_SCM_BASE_ADDR + 0x4) /* Silicon ID Register */
+#define FMCR __REG(MX1_SCM_BASE_ADDR + 0x8) /* Function Multiplex Control Register */
+#define GPCR __REG(MX1_SCM_BASE_ADDR + 0xC) /* Function Multiplex Control Register */
/* SDRAM controller registers */
-#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */
-#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */
-#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
-#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
+#define SDCTL0 __REG(MX1_SDRAMC_BASE_ADDR) /* SDRAM 0 Control Register */
+#define SDCTL1 __REG(MX1_SDRAMC_BASE_ADDR + 0x4) /* SDRAM 1 Control Register */
+#define SDMISC __REG(MX1_SDRAMC_BASE_ADDR + 0x14) /* Miscellaneous Register */
+#define SDRST __REG(MX1_SDRAMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */
/* PLL registers */
-#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
-#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
-#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
-#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
-#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
+#define CSCR __REG(MX1_CCM_BASE_ADDR) /* Clock Source Control Register */
+#define MPCTL0 __REG(MX1_CCM_BASE_ADDR + 0x4) /* MCU PLL Control Register 0 */
+#define MPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x8) /* MCU PLL and System Clock Register 1 */
+#define SPCTL0 __REG(MX1_CCM_BASE_ADDR + 0xc) /* System PLL Control Register 0 */
+#define SPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
+#define PCDR __REG(MX1_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Divider Register */
#define CSCR_MPLL_RESTART (1<<21)
/* Chip Select Registers */
-#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */
-#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */
-#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */
-#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */
-#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
-#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
-#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
-#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
-#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
-#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
-#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
-#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
-#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
+#define CS0U __REG(MX1_EIM_BASE_ADDR) /* Chip Select 0 Upper Register */
+#define CS0L __REG(MX1_EIM_BASE_ADDR + 0x4) /* Chip Select 0 Lower Register */
+#define CS1U __REG(MX1_EIM_BASE_ADDR + 0x8) /* Chip Select 1 Upper Register */
+#define CS1L __REG(MX1_EIM_BASE_ADDR + 0xc) /* Chip Select 1 Lower Register */
+#define CS2U __REG(MX1_EIM_BASE_ADDR + 0x10) /* Chip Select 2 Upper Register */
+#define CS2L __REG(MX1_EIM_BASE_ADDR + 0x14) /* Chip Select 2 Lower Register */
+#define CS3U __REG(MX1_EIM_BASE_ADDR + 0x18) /* Chip Select 3 Upper Register */
+#define CS3L __REG(MX1_EIM_BASE_ADDR + 0x1c) /* Chip Select 3 Lower Register */
+#define CS4U __REG(MX1_EIM_BASE_ADDR + 0x20) /* Chip Select 4 Upper Register */
+#define CS4L __REG(MX1_EIM_BASE_ADDR + 0x24) /* Chip Select 4 Lower Register */
+#define CS5U __REG(MX1_EIM_BASE_ADDR + 0x28) /* Chip Select 5 Upper Register */
+#define CS5L __REG(MX1_EIM_BASE_ADDR + 0x2c) /* Chip Select 5 Lower Register */
+#define EIM __REG(MX1_EIM_BASE_ADDR + 0x30) /* EIM Configuration Register */
/* assignements for GPIO alternate/primary functions */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 05/14] ARM i.MX27: give register base addresses a proper MX27_ prefix
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (3 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 04/14] ARM i.MX1: give register base addresses a proper MX1_ prefix Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 06/14] ARM i.MX25: give register base addresses a proper MX25_ prefix Sascha Hauer
` (8 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c | 4 +-
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 4 +-
arch/arm/boards/guf-neso/board.c | 12 +-
arch/arm/boards/guf-neso/lowlevel.c | 4 +-
arch/arm/boards/imx27ads/imx27ads.c | 4 +-
arch/arm/boards/pcm038/lowlevel.c | 4 +-
arch/arm/boards/pcm038/pcm970.c | 16 +-
arch/arm/boards/phycard-i.MX27/lowlevel_init.S | 4 +-
arch/arm/boards/phycard-i.MX27/pca100.c | 20 +-
arch/arm/mach-imx/external-nand-boot.c | 2 +-
arch/arm/mach-imx/imx27.c | 18 +-
arch/arm/mach-imx/include/mach/devices-imx27.h | 28 +--
arch/arm/mach-imx/include/mach/imx27-regs.h | 225 +++++++++++++--------
13 files changed, 199 insertions(+), 146 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index 068cc11..0ffe43f 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -223,13 +223,13 @@ device_initcall(eukrea_cpuimx27_devices_init);
static int eukrea_cpuimx27_console_init(void)
{
#ifdef CONFIG_DRIVER_SERIAL_IMX
- imx_add_uart((void *)IMX_UART1_BASE, DEVICE_ID_DYNAMIC);
+ imx27_add_uart0();
#endif
/* configure 8 bit UART on cs3 */
FMCR &= ~0x2;
imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000);
#ifdef CONFIG_DRIVER_SERIAL_NS16550
- add_ns16550_device(DEVICE_ID_DYNAMIC, IMX_CS3_BASE + QUART_OFFSET, 0xf,
+ add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf,
IORESOURCE_MEM_16BIT, &quad_uart_serial_plat);
#endif
return 0;
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
index 0dae3ec..4db5765 100644
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
@@ -110,8 +110,8 @@ board_init_lowlevel:
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
- ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
- ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
+ ldr r0, =MX27_NFC_BASE_ADDR /* start of NFC SRAM */
+ ldr r2, =MX27_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c
index 7f25a11..7adee92 100644
--- a/arch/arm/boards/guf-neso/board.c
+++ b/arch/arm/boards/guf-neso/board.c
@@ -115,21 +115,21 @@ static void neso_usbh_init(void)
{
uint32_t temp;
- temp = readl(IMX_OTG_BASE + 0x600);
+ temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600);
temp &= ~((3 << 21) | 1);
temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20) | (1<<11);
- writel(temp, IMX_OTG_BASE + 0x600);
+ writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600);
- temp = readl(IMX_OTG_BASE + 0x584);
+ temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584);
temp &= ~(3 << 30);
temp |= 2 << 30;
- writel(temp, IMX_OTG_BASE + 0x584);
+ writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584);
mdelay(10);
gpio_set_value(USBH2_PHY_CS_GPIO, 0);
mdelay(10);
- ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1);
+ ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
}
#endif
@@ -276,7 +276,7 @@ static int neso_devices_init(void)
#ifdef CONFIG_USB
neso_usbh_init();
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
#endif
imx27_add_fec(&fec_info);
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c
index e6059fe..3a78054 100644
--- a/arch/arm/boards/guf-neso/lowlevel.c
+++ b/arch/arm/boards/guf-neso/lowlevel.c
@@ -97,10 +97,10 @@ void __bare_init __naked board_init_lowlevel(void)
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+ if (r < MX27_NFC_BASE_ADDR || r > MX27_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
- src = (unsigned int *)IMX_NFC_BASE;
+ src = (unsigned int *)MX27_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c
index 0a9074d..f9416e1 100644
--- a/arch/arm/boards/imx27ads/imx27ads.c
+++ b/arch/arm/boards/imx27ads/imx27ads.c
@@ -54,10 +54,10 @@ static int imx27ads_timing_init(void)
imx27_setup_weimcs(0, 0x23524E80, 0x10000D03, 0x00720900);
/* Select FEC data through data path */
- writew(0x0020, IMX_CS4_BASE + 0x10);
+ writew(0x0020, MX27_CS4_BASE_ADDR + 0x10);
/* Enable CPLD FEC data path */
- writew(0x0010, IMX_CS4_BASE + 0x14);
+ writew(0x0010, MX27_CS4_BASE_ADDR + 0x14);
return 0;
}
diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c
index 04438f6..f975d0e 100644
--- a/arch/arm/boards/pcm038/lowlevel.c
+++ b/arch/arm/boards/pcm038/lowlevel.c
@@ -103,10 +103,10 @@ void __bare_init __naked board_init_lowlevel(void)
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+ if (r < MX27_NFC_BASE_ADDR || r > MX27_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
- src = (unsigned int *)IMX_NFC_BASE;
+ src = (unsigned int *)MX27_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c
index b2ed85f..d392ea4 100644
--- a/arch/arm/boards/pcm038/pcm970.c
+++ b/arch/arm/boards/pcm038/pcm970.c
@@ -31,28 +31,28 @@ static void pcm970_usbh2_init(void)
{
uint32_t temp;
- temp = readl(IMX_OTG_BASE + 0x600);
+ temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600);
temp &= ~((3 << 21) | 1);
temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
- writel(temp, IMX_OTG_BASE + 0x600);
+ writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600);
- temp = readl(IMX_OTG_BASE + 0x584);
+ temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584);
temp &= ~(3 << 30);
temp |= 2 << 30;
- writel(temp, IMX_OTG_BASE + 0x584);
+ writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584);
mdelay(10);
- if (!ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1))
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
+ if (!ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1))
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
}
#endif
#ifdef CONFIG_DISK_INTF_PLATFORM_IDE
static struct resource pcm970_ide_resources[] = {
{
- .start = IMX_PCMCIA_MEM_BASE,
- .end = IMX_PCMCIA_MEM_BASE + SZ_1K - 1,
+ .start = MX27_PCMCIA_MEM_BASE_ADDR,
+ .end = MX27_PCMCIA_MEM_BASE_ADDR + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
};
diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
index c24edd4..b3c2e0c 100644
--- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
+++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
@@ -96,8 +96,8 @@ board_init_lowlevel:
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
- ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
- ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
+ ldr r0, =MX27_NFC_BASE_ADDR /* start of NFC SRAM */
+ ldr r2, =MX27_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 16f3e4f..9b8f8c2 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -136,10 +136,10 @@ static void pca100_usb_register(void)
mdelay(10);
- ulpi_setup((void *)(IMX_OTG_BASE + 0x170), 1);
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE, NULL);
- ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1);
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
+ ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x170), 1);
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR, NULL);
+ ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
}
#endif
@@ -155,10 +155,10 @@ static void pca100_usb_init(void)
{
u32 reg;
- reg = readl(IMX_OTG_BASE + 0x600);
+ reg = readl(MX27_USB_OTG_BASE_ADDR + 0x600);
reg &= ~((3 << 21) | 1);
reg |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20);
- writel(reg, IMX_OTG_BASE + 0x600);
+ writel(reg, MX27_USB_OTG_BASE_ADDR + 0x600);
/*
* switch usbotg and usbh2 to ulpi mode. Do this *before*
@@ -166,15 +166,15 @@ static void pca100_usb_init(void)
* triggering. Also, do this even when USB support is
* disabled to give Linux USB support a good start.
*/
- reg = readl(IMX_OTG_BASE + 0x584);
+ reg = readl(MX27_USB_OTG_BASE_ADDR + 0x584);
reg &= ~(3 << 30);
reg |= 2 << 30;
- writel(reg, IMX_OTG_BASE + 0x584);
+ writel(reg, MX27_USB_OTG_BASE_ADDR + 0x584);
- reg = readl(IMX_OTG_BASE + 0x184);
+ reg = readl(MX27_USB_OTG_BASE_ADDR + 0x184);
reg &= ~(3 << 30);
reg |= 2 << 30;
- writel(reg, IMX_OTG_BASE + 0x184);
+ writel(reg, MX27_USB_OTG_BASE_ADDR + 0x184);
/* disable the usb phys */
imx_gpio_mode((GPIO_PORTB | 23) | GPIO_GPIO | GPIO_IN);
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index 5cab32f..a590992 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -122,7 +122,7 @@ static int __maybe_unused is_pagesize_2k(void)
return 0;
#endif
#ifdef CONFIG_ARCH_IMX27
- if (readl(IMX_SYSTEM_CTL_BASE + 0x14) & (1 << 5))
+ if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
return 1;
else
return 0;
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index 32a32a3..76bb910 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -43,7 +43,7 @@ int imx_silicon_revision(void)
static void imx27_init_max(void)
{
- void __iomem *max_base = (void *)IMX_MAX_BASE;
+ void __iomem *max_base = (void *)MX27_MAX_BASE_ADDR;
u32 val;
/* 0 is the highest priority */
@@ -64,18 +64,18 @@ static void imx27_init_max(void)
static int imx27_init(void)
{
- add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
+ add_generic_device("imx_iim", 0, NULL, MX27_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
imx27_init_max();
- add_generic_device("imx1-gpt", 0, NULL, 0x10003000, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 0, NULL, 0x10015000, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 1, NULL, 0x10015100, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 2, NULL, 0x10015200, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 3, NULL, 0x10015300, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 4, NULL, 0x10015400, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx1-gpio", 5, NULL, 0x10015500, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpt", 0, NULL, MX27_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpio", 0, NULL, MX27_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpio", 1, NULL, MX27_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpio", 2, NULL, MX27_GPIO3_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpio", 3, NULL, MX27_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpio", 4, NULL, MX27_GPIO5_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-gpio", 5, NULL, MX27_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
return 0;
}
console_initcall(imx27_init);
diff --git a/arch/arm/mach-imx/include/mach/devices-imx27.h b/arch/arm/mach-imx/include/mach/devices-imx27.h
index 6a3a234..2799343 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx27.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx27.h
@@ -3,70 +3,70 @@
static inline struct device_d *imx27_add_spi0(struct spi_imx_master *pdata)
{
- return imx_add_spi((void *)IMX_SPI1_BASE, 0, pdata);
+ return imx_add_spi((void *)MX27_CSPI1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx27_add_spi1(struct spi_imx_master *pdata)
{
- return imx_add_spi((void *)IMX_SPI2_BASE, 1, pdata);
+ return imx_add_spi((void *)MX27_CSPI2_BASE_ADDR, 1, pdata);
}
static inline struct device_d *imx27_add_i2c0(struct i2c_platform_data *pdata)
{
- return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata);
+ return imx_add_i2c((void *)MX27_I2C1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx27_add_i2c1(struct i2c_platform_data *pdata)
{
- return imx_add_i2c((void *)IMX_I2C2_BASE, 1, pdata);
+ return imx_add_i2c((void *)MX27_I2C2_BASE_ADDR, 1, pdata);
}
static inline struct device_d *imx27_add_uart0(void)
{
- return imx_add_uart((void *)IMX_UART1_BASE, 0);
+ return imx_add_uart((void *)MX27_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx27_add_uart1(void)
{
- return imx_add_uart((void *)IMX_UART2_BASE, 1);
+ return imx_add_uart((void *)MX27_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx27_add_uart2(void)
{
- return imx_add_uart((void *)IMX_UART3_BASE, 2);
+ return imx_add_uart((void *)MX27_UART3_BASE_ADDR, 2);
}
static inline struct device_d *imx27_add_uart3(void)
{
- return imx_add_uart((void *)IMX_UART4_BASE, 3);
+ return imx_add_uart((void *)MX27_UART4_BASE_ADDR, 3);
}
static inline struct device_d *imx27_add_nand(struct imx_nand_platform_data *pdata)
{
- return imx_add_nand((void *)IMX_NFC_BASE, pdata);
+ return imx_add_nand((void *)MX27_NFC_BASE_ADDR, pdata);
}
static inline struct device_d *imx27_add_fb(struct imx_fb_platform_data *pdata)
{
- return imx_add_fb((void *)IMX_FB_BASE, pdata);
+ return imx_add_fb((void *)MX27_LCDC_BASE_ADDR, pdata);
}
static inline struct device_d *imx27_add_fec(struct fec_platform_data *pdata)
{
- return imx_add_fec((void *)IMX_FEC_BASE, pdata);
+ return imx_add_fec((void *)MX27_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx27_add_mmc0(void *pdata)
{
- return imx_add_mmc((void *)IMX_SDHC1_BASE, 0, pdata);
+ return imx_add_mmc((void *)MX27_SDHC1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx27_add_mmc1(void *pdata)
{
- return imx_add_mmc((void *)IMX_SDHC2_BASE, 1, pdata);
+ return imx_add_mmc((void *)MX27_SDHC2_BASE_ADDR, 1, pdata);
}
static inline struct device_d *imx27_add_mmc2(void *pdata)
{
- return imx_add_mmc((void *)IMX_SDHC3_BASE, 2, pdata);
+ return imx_add_mmc((void *)MX27_SDHC3_BASE_ADDR, 2, pdata);
}
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index 8686a9d..907afa4 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -5,66 +5,133 @@
#error "Please do not include directly"
#endif
-#define IMX_IO_BASE 0x10000000
-
-#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
-#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
-#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
-#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
-#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
-#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE)
-#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
-#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
-#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
-#define IMX_SPI1_BASE (0x0e000 + IMX_IO_BASE)
-#define IMX_SPI2_BASE (0x0f000 + IMX_IO_BASE)
-#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
-#define IMX_SDHC1_BASE (0x13000 + IMX_IO_BASE)
-#define IMX_SDHC2_BASE (0x14000 + IMX_IO_BASE)
-#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
-#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
-#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
-#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
-#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
-#define IMX_I2C2_BASE (0x1d000 + IMX_IO_BASE)
-#define IMX_SDHC3_BASE (0x1e000 + IMX_IO_BASE)
-#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
-#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
-#define IMX_FB_BASE (0x21000 + IMX_IO_BASE)
-#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
-#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
-#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
-#define IMX_OTG_BASE (0x24000 + IMX_IO_BASE)
-#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
-#define IMX_MAX_BASE (0x3f000 + IMX_IO_BASE)
-
-#define IMX_NFC_BASE (0xd8000000)
-#define IMX_ESD_BASE (0xd8001000)
-#define IMX_WEIM_BASE (0xd8002000)
-#define IMX_M3IF_BASE (0xd8003000)
-#define IMX_PCMCIA_CTL_BASE (0xd8004000)
-
-#define PCMCIA_PIPR (IMX_PCMCIA_CTL_BASE + 0x00)
-#define PCMCIA_PSCR (IMX_PCMCIA_CTL_BASE + 0x04)
-#define PCMCIA_PER (IMX_PCMCIA_CTL_BASE + 0x08)
-#define PCMCIA_PBR(x) (IMX_PCMCIA_CTL_BASE + 0x0c + ((x) << 2))
-#define PCMCIA_POR(x) (IMX_PCMCIA_CTL_BASE + 0x28 + ((x) << 2))
-#define PCMCIA_POFR(x) (IMX_PCMCIA_CTL_BASE + 0x44 + ((x) << 2))
-#define PCMCIA_PGCR (IMX_PCMCIA_CTL_BASE + 0x60)
-#define PCMCIA_PGSR (IMX_PCMCIA_CTL_BASE + 0x64)
+#define MX27_AIPI_BASE_ADDR 0x10000000
+#define MX27_AIPI_SIZE SZ_1M
+#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
+#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
+#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
+#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
+#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
+#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
+#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
+#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
+#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
+#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
+#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
+#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
+#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
+#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
+#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
+#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
+#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
+#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
+#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
+#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
+#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
+#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
+#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
+#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
+#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
+#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
+#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
+#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
+#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
+#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
+#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
+#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
+#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
+#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
+#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
+#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
+#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
+#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
+#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
+#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
+#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
+#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
+#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
+#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
+#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
+#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
+#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
+#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
+#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
+#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
+#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
+#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
+#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
+#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
+#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
+#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
+#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
+
+#define MX27_AVIC_BASE_ADDR 0x10040000
+
+/* ROM patch */
+#define MX27_ROMP_BASE_ADDR 0x10041000
+
+#define MX27_SAHB1_BASE_ADDR 0x80000000
+#define MX27_SAHB1_SIZE SZ_1M
+#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
+#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
+
+/* Memory regions and CS */
+#define MX27_CSD0_BASE_ADDR 0xa0000000
+#define MX27_CSD1_BASE_ADDR 0xb0000000
+
+#define MX27_CS0_BASE_ADDR 0xc0000000
+#define MX27_CS1_BASE_ADDR 0xc8000000
+#define MX27_CS2_BASE_ADDR 0xd0000000
+#define MX27_CS3_BASE_ADDR 0xd2000000
+#define MX27_CS4_BASE_ADDR 0xd4000000
+#define MX27_CS5_BASE_ADDR 0xd6000000
+
+/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
+#define MX27_X_MEMC_BASE_ADDR 0xd8000000
+#define MX27_X_MEMC_SIZE SZ_1M
+#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
+#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
+#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
+#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
+#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
+
+#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
+#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
+#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
+#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
+
+#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
+
+/* IRAM */
+#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
+
+/* FIXME: get rid of these */
+#define IMX_GPIO_BASE MX27_GPIO_BASE_ADDR
+#define IMX_NFC_BASE MX27_NFC_BASE_ADDR
+#define IMX_WDT_BASE MX27_WDOG_BASE_ADDR
+#define IMX_ESD_BASE MX27_SDRAMC_BASE_ADDR
+
+#define PCMCIA_PIPR (MX27_PCMCIA_CTL_BASE_ADDR + 0x00)
+#define PCMCIA_PSCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x04)
+#define PCMCIA_PER (MX27_PCMCIA_CTL_BASE_ADDR + 0x08)
+#define PCMCIA_PBR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x0c + ((x) << 2))
+#define PCMCIA_POR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x28 + ((x) << 2))
+#define PCMCIA_POFR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x44 + ((x) << 2))
+#define PCMCIA_PGCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x60)
+#define PCMCIA_PGSR (MX27_PCMCIA_CTL_BASE_ADDR + 0x64)
/* AIPI */
-#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00)
-#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04)
-#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00)
-#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04)
+#define AIPI1_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x00)
+#define AIPI1_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x04)
+#define AIPI2_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x00)
+#define AIPI2_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x04)
/* System Control */
-#define CID __REG(IMX_SYSTEM_CTL_BASE + 0x0) /* Chip ID Register */
-#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14) /* Function Multeplexing Control Register */
-#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18) /* Global Peripheral Control Register */
-#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */
-#define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
+#define CID __REG(MX27_SYSCTRL_BASE_ADDR + 0x0) /* Chip ID Register */
+#define FMCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */
+#define GPCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */
+#define WBCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */
+#define DSCR(x) __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
#define GPCR_BOOT_SHIFT 16
#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT)
@@ -76,26 +143,20 @@
#define GPCR_BOOT_32BIT_CS0 6
#define GPCR_BOOT_8BIT_NAND_512 7
-/* Chip Select Registers */
-#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x Upper Register */
-#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x Lower Register */
-#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */
-#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */
-
#include "esdctl.h"
/* PLL registers */
-#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */
-#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */
-#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */
-#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
-#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */
-#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */
-#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */
-#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */
-#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */
-#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */
+#define CSCR __REG(MX27_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */
+#define MPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */
+#define MPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */
+#define SPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */
+#define SPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
+#define OSC26MCTL __REG(MX27_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */
+#define PCDR0 __REG(MX27_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */
+#define PCDR1 __REG(MX27_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */
+#define PCCR0 __REG(MX27_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */
+#define PCCR1 __REG(MX27_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */
+#define CCSR __REG(MX27_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */
#define CSCR_MPEN (1 << 0)
#define CSCR_SPEN (1 << 1)
@@ -221,21 +282,13 @@
#define ESDCFG_TWTR (1 << 20)
#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
-#define IMX_CS0_BASE 0xC0000000
-#define IMX_CS1_BASE 0xC8000000
-#define IMX_CS2_BASE 0xD0000000
-#define IMX_CS3_BASE 0xD2000000
-#define IMX_CS4_BASE 0xD4000000
-#define IMX_CS5_BASE 0xD6000000
-
-#define IMX_PCMCIA_MEM_BASE (0xdc000000)
-
#ifndef __ASSEMBLY__
-static inline void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional)
+#include <io.h>
+static inline void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned additional)
{
- CSxU(cs) = upper;
- CSxL(cs) = lower;
- CSxA(cs) = addional;
+ writel(upper, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x0);
+ writel(lower, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
+ writel(additional, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
}
#endif /* __ASSEMBLY__ */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 06/14] ARM i.MX25: give register base addresses a proper MX25_ prefix
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (4 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 05/14] ARM i.MX27: give register base addresses a proper MX27_ prefix Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 07/14] ARM i.MX/MXS: Allow to include imx*-regs.h directly Sascha Hauer
` (7 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c | 32 ++---
arch/arm/boards/eukrea_cpuimx25/lowlevel.c | 32 ++---
arch/arm/boards/freescale-mx25-3-stack/3stack.c | 20 ++--
.../boards/freescale-mx25-3-stack/lowlevel_init.S | 26 ++---
arch/arm/boards/karo-tx25/board.c | 6 +-
arch/arm/boards/karo-tx25/lowlevel.c | 14 +--
arch/arm/mach-imx/imx25.c | 20 +++-
arch/arm/mach-imx/include/mach/devices-imx25.h | 55 +++++++--
arch/arm/mach-imx/include/mach/imx25-regs.h | 123 +++++++++++++-------
arch/arm/mach-imx/speed-imx25.c | 22 ++--
10 files changed, 217 insertions(+), 133 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index 4dc5501..bf3cbc3 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -93,21 +93,21 @@ static void imx25_usb_init(void)
unsigned int tmp;
/* Host 1 */
- tmp = readl(IMX_OTG_BASE + 0x600);
+ tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x600);
tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT;
tmp |= MX35_H1_USBTE_BIT;
tmp |= MX35_H1_IPPUE_DOWN_BIT;
- writel(tmp, IMX_OTG_BASE + 0x600);
+ writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x600);
- tmp = readl(IMX_OTG_BASE + 0x584);
+ tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x584);
tmp |= 3 << 30;
- writel(tmp, IMX_OTG_BASE + 0x584);
+ writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x584);
/* Set to Host mode */
- tmp = readl(IMX_OTG_BASE + 0x5a8);
- writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
+ tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x5a8);
+ writel(tmp | 0x3, MX25_USB_OTG_BASE_ADDR + 0x5a8);
}
#endif
@@ -119,7 +119,7 @@ static struct fsl_usb2_platform_data usb_pdata = {
static int eukrea_cpuimx25_mem_init(void)
{
- arm_add_mem_device("ram0", IMX_SDRAM_CS0, 64 * 1024 * 1024);
+ arm_add_mem_device("ram0", MX25_CSD0_BASE_ADDR, 64 * 1024 * 1024);
return 0;
}
@@ -219,12 +219,12 @@ static int eukrea_cpuimx25_devices_init(void)
#ifdef CONFIG_USB
imx25_usb_init();
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX25_USB_OTG_BASE_ADDR + 0x400, NULL);
#endif
#ifdef CONFIG_USB_GADGET
/* Workaround ENGcm09152 */
- writel(readl(IMX_OTG_BASE + 0x608) | (1 << 23), IMX_OTG_BASE + 0x608);
- add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200,
+ writel(readl(MX25_USB_OTG_BASE_ADDR + 0x608) | (1 << 23), MX25_USB_OTG_BASE_ADDR + 0x608);
+ add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX25_USB_OTG_BASE_ADDR, 0x200,
IORESOURCE_MEM, &usb_pdata);
#endif
@@ -253,13 +253,13 @@ void __bare_init nand_boot(void)
static int eukrea_cpuimx25_core_init(void) {
/* enable UART1, FEC, SDHC, USB & I2C clock */
- writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 6) | (1 << 23)
+ writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR0) | (1 << 6) | (1 << 23)
| (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28),
- IMX_CCM_BASE + CCM_CGCR0);
- writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 23) | (1 << 15)
- | (1 << 13), IMX_CCM_BASE + CCM_CGCR1);
- writel(readl(IMX_CCM_BASE + CCM_CGCR2) | (1 << 14),
- IMX_CCM_BASE + CCM_CGCR2);
+ MX25_CCM_BASE_ADDR + CCM_CGCR0);
+ writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR1) | (1 << 23) | (1 << 15)
+ | (1 << 13), MX25_CCM_BASE_ADDR + CCM_CGCR1);
+ writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR2) | (1 << 14),
+ MX25_CCM_BASE_ADDR + CCM_CGCR2);
return 0;
}
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
index 9c1b4f8..feddacc 100644
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
@@ -54,20 +54,20 @@ void __bare_init __naked board_init_lowlevel(void)
register uint32_t loops = 0x20000;
/* restart the MPLL and wait until it's stable */
- writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27),
- IMX_CCM_BASE + CCM_CCTL);
- while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {};
+ writel(readl(MX25_CCM_BASE_ADDR + CCM_CCTL) | (1 << 27),
+ MX25_CCM_BASE_ADDR + CCM_CCTL);
+ while (readl(MX25_CCM_BASE_ADDR + CCM_CCTL) & (1 << 27)) {};
/* Configure dividers and ARM clock source
* ARM @ 400 MHz
* AHB @ 133 MHz
*/
- writel(0x20034000, IMX_CCM_BASE + CCM_CCTL);
+ writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL);
/* Enable UART1 / FEC / */
-/* writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0);
- writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1);
- writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2);*/
+/* writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0);
+ writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1);
+ writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2);*/
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.
* Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -115,10 +115,10 @@ void __bare_init __naked board_init_lowlevel(void)
writel(0x1, 0xb8003000);
/* Speed up NAND controller by adjusting the NFC divider */
- r = readl(IMX_CCM_BASE + CCM_PCDR2);
+ r = readl(MX25_CCM_BASE_ADDR + CCM_PCDR2);
r &= ~0xf;
r |= 0x1;
- writel(r, IMX_CCM_BASE + CCM_PCDR2);
+ writel(r, MX25_CCM_BASE_ADDR + CCM_PCDR2);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -134,22 +134,22 @@ void __bare_init __naked board_init_lowlevel(void)
writel(0x0029572B, ESDCFG0);
writel(0x92210000, ESDCTL0);
- writeb(0xda, IMX_SDRAM_CS0 + 0x400);
+ writeb(0xda, MX25_CSD0_BASE_ADDR + 0x400);
writel(0xA2210000, ESDCTL0);
- writeb(0xda, IMX_SDRAM_CS0);
- writeb(0xda, IMX_SDRAM_CS0);
+ writeb(0xda, MX25_CSD0_BASE_ADDR);
+ writeb(0xda, MX25_CSD0_BASE_ADDR);
writel(0xB2210000, ESDCTL0);
- writeb(0xda, IMX_SDRAM_CS0 + 0x33);
- writeb(0xda, IMX_SDRAM_CS0 + 0x1000000);
+ writeb(0xda, MX25_CSD0_BASE_ADDR + 0x33);
+ writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000);
writel(0x82216080, ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+ if (r < MX25_NFC_BASE_ADDR || r > MX25_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
- src = (unsigned int *)IMX_NFC_BASE;
+ src = (unsigned int *)MX25_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
index 331c2e8..a0ae938 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
@@ -119,18 +119,18 @@ static void imx25_usb_init(void)
unsigned int tmp;
/* Host 2 */
- tmp = readl(IMX_OTG_BASE + 0x600);
+ tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x600);
tmp &= ~(3 << 21);
tmp |= (2 << 21) | (1 << 4) | (1 << 5);
- writel(tmp, IMX_OTG_BASE + 0x600);
+ writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x600);
- tmp = readl(IMX_OTG_BASE + 0x584);
+ tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x584);
tmp |= 3 << 30;
- writel(tmp, IMX_OTG_BASE + 0x584);
+ writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x584);
/* Set to Host mode */
- tmp = readl(IMX_OTG_BASE + 0x5a8);
- writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
+ tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x5a8);
+ writel(tmp | 0x3, MX25_USB_OTG_BASE_ADDR + 0x5a8);
}
#endif
@@ -195,7 +195,7 @@ static int imx25_mem_init(void)
#else
#error "Unsupported SDRAM type"
#endif
- arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM_SIZE);
+ arm_add_mem_device("ram0", MX25_CSD0_BASE_ADDR, SDRAM_SIZE);
add_mem_device("sram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE);
return 0;
@@ -209,13 +209,13 @@ static int imx25_devices_init(void)
* the CPLD has to be initialized.
*/
imx25_usb_init();
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX25_USB_OTG_BASE_ADDR + 0x400, NULL);
#endif
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
- if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
+ if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14))
nand_info.width = 2;
imx25_add_nand(&nand_info);
@@ -298,7 +298,7 @@ void __bare_init nand_boot(void)
static int imx25_core_setup(void)
{
- writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2);
+ writel(0x01010103, MX25_CCM_BASE_ADDR + CCM_PCDR2);
return 0;
}
diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
index 30b79d9..124ef25 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
@@ -46,7 +46,7 @@ CCM_PDR0_W: .word 0x00801000
MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
PPCTL_PARAM_W: .word PPCTL_PARAM_300
-CCM_BASE_ADDR_W: .word IMX_CCM_BASE
+CCM_BASE_ADDR_W: .word MX25_CCM_BASE_ADDR
.globl board_init_lowlevel
board_init_lowlevel:
@@ -65,10 +65,10 @@ board_init_lowlevel:
str r1, [r0, #MX25_CCM_MCR]
/* enable all the clocks */
- writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0)
- writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1)
- writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2)
- writel(0x0000FEFF, IMX_CCM_BASE + MX25_CCM_MCR)
+ writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0)
+ writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1)
+ writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2)
+ writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR)
/* Skip SDRAM initialization if we run from RAM */
cmp pc, #0x80000000
@@ -86,7 +86,7 @@ board_init_lowlevel:
mov r12, #0x00
mov r2, #0x1 /* mDDR */
- mov r1, #IMX_SDRAM_CS0
+ mov r1, #MX25_CSD0_BASE_ADDR
bl setup_sdram_bank
// cmp r3, #0x0
// orreq r12, r12, #1
@@ -99,8 +99,8 @@ board_init_lowlevel:
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
- ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
- ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
+ ldr r0, =MX25_NFC_BASE_ADDR /* start of NFC SRAM */
+ ldr r2, =MX25_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
@@ -147,7 +147,7 @@ setup_sdram_bank:
tst r2, #0x1
ldreq r3, [r4, #0x0]
ldrne r3, [r4, #0x4]
- cmp r1, #IMX_SDRAM_CS1
+ cmp r1, #MX25_CSD1_BASE_ADDR
strlo r3, [r0, #0x4]
strhs r3, [r0, #0xC]
@@ -161,7 +161,7 @@ setup_sdram_bank:
tst r2, #0x1
bne skip_set_mode
- cmp r1, #IMX_SDRAM_CS1
+ cmp r1, #MX25_CSD1_BASE_ADDR
ldr r3, ESDCTL_0xB2220000
strlo r3, [r0, #0x0]
strhs r3, [r0, #0x8]
@@ -183,7 +183,7 @@ setup_sdram_bank:
strb r3, [r1, r4]
skip_set_mode:
- cmp r1, #IMX_SDRAM_CS1
+ cmp r1, #MX25_CSD1_BASE_ADDR
ldr r3, ESDCTL_0xA2220000
strlo r3, [r0, #0x0]
strhs r3, [r0, #0x8]
@@ -207,7 +207,7 @@ skip_set_mode:
ldrne r4, [r4, #0x4]
strb r3, [r1, r4]
- cmp r1, #IMX_SDRAM_CS1
+ cmp r1, #MX25_CSD1_BASE_ADDR
ldr r3, ESDCTL_0x82226080
strlo r3, [r0, #0x0]
strhs r3, [r0, #0x8]
@@ -242,5 +242,5 @@ ESDCTL_0x82226080: .word 0x82216080
ESDCTL_CONFIG: .word 0x007FFC3F
.word 0x007FFC3F
ESDCTL_DELAY5: .word 0x00F49F00
-ESDCTL_BASE_W: .word IMX_ESD_BASE
+ESDCTL_BASE_W: .word MX25_ESDCTL_BASE_ADDR
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index 79d942d..5413ea8 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -52,8 +52,8 @@ struct imx_nand_platform_data nand_info = {
static int tx25_mem_init(void)
{
- arm_add_mem_device("ram0", IMX_SDRAM_CS0, 32 * 1024 * 1024);
- arm_add_mem_device("ram0", IMX_SDRAM_CS1, 32 * 1024 * 1024);
+ arm_add_mem_device("ram0", MX25_CSD0_BASE_ADDR, 32 * 1024 * 1024);
+ arm_add_mem_device("ram0", MX25_CSD1_BASE_ADDR, 32 * 1024 * 1024);
add_mem_device("ram0", 0x78000000, 128 * 1024,
IORESOURCE_MEM_WRITEABLE);
@@ -108,7 +108,7 @@ static int tx25_devices_init(void)
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
- if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
+ if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14))
nand_info.width = 2;
imx25_add_nand(&nand_info);
diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c
index 3d26257..21bedcb 100644
--- a/arch/arm/boards/karo-tx25/lowlevel.c
+++ b/arch/arm/boards/karo-tx25/lowlevel.c
@@ -119,12 +119,12 @@ void __bare_init __naked board_init_lowlevel(void)
writel(0x1, 0xb8003000);
/* configure ARM clk */
- writel(0x20034000, IMX_CCM_BASE + CCM_CCTL);
+ writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL);
/* enable all the clocks */
- writel(0x1fffffff, IMX_CCM_BASE + CCM_CGCR0);
- writel(0xffffffff, IMX_CCM_BASE + CCM_CGCR1);
- writel(0x000fdfff, IMX_CCM_BASE + CCM_CGCR2);
+ writel(0x1fffffff, MX25_CCM_BASE_ADDR + CCM_CGCR0);
+ writel(0xffffffff, MX25_CCM_BASE_ADDR + CCM_CGCR1);
+ writel(0x000fdfff, MX25_CCM_BASE_ADDR + CCM_CGCR2);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -132,7 +132,7 @@ void __bare_init __naked board_init_lowlevel(void)
board_init_lowlevel_return();
/* set to 3.3v SDRAM */
- writel(0x800, IMX_IOMUXC_BASE + 0x454);
+ writel(0x800, MX25_IOMUXC_BASE_ADDR + 0x454);
writel(ESDMISC_RST, ESDMISC);
@@ -150,10 +150,10 @@ void __bare_init __naked board_init_lowlevel(void)
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+ if (r < MX25_NFC_BASE_ADDR || r > MX25_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
- src = (unsigned int *)IMX_NFC_BASE;
+ src = (unsigned int *)MX25_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index dd10d58..3f44649 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -18,6 +18,14 @@
#include <io.h>
#include <sizes.h>
+/* IIM fuse definitions */
+#define IIM_BANK0_BASE (MX25_IIM_BASE_ADDR + 0x800)
+#define IIM_BANK1_BASE (MX25_IIM_BASE_ADDR + 0xc00)
+#define IIM_BANK2_BASE (MX25_IIM_BASE_ADDR + 0x1000)
+
+#define IIM_UID (IIM_BANK0_BASE + 0x20)
+#define IIM_MAC_ADDR (IIM_BANK0_BASE + 0x68)
+
u64 imx_uid(void)
{
u64 uid = 0;
@@ -41,14 +49,14 @@ static struct imx_iim_platform_data imx25_iim_pdata = {
static int imx25_init(void)
{
- add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
+ add_generic_device("imx_iim", 0, NULL, MX25_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, &imx25_iim_pdata);
- add_generic_device("imx31-gpt", 0, NULL, 0x53f90000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 3, NULL, 0x53f9c000, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpt", 0, NULL, MX25_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 0, NULL, MX25_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 1, NULL, MX25_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 2, NULL, MX25_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 3, NULL, MX25_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx25.h b/arch/arm/mach-imx/include/mach/devices-imx25.h
index bd9dd0a..86cda35 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx25.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx25.h
@@ -3,41 +3,80 @@
static inline struct device_d *imx25_add_i2c0(struct i2c_platform_data *pdata)
{
- return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata);
+ return imx_add_i2c((void *)MX25_I2C1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx25_add_i2c1(struct i2c_platform_data *pdata)
+{
+ return imx_add_i2c((void *)MX25_I2C2_BASE_ADDR, 1, pdata);
+}
+
+static inline struct device_d *imx25_add_i2c2(struct i2c_platform_data *pdata)
+{
+ return imx_add_i2c((void *)MX25_I2C3_BASE_ADDR, 2, pdata);
}
static inline struct device_d *imx25_add_spi0(struct spi_imx_master *pdata)
{
- return imx_add_spi((void *)IMX_CSPI1_BASE, 0, pdata);
+ return imx_add_spi((void *)MX25_CSPI1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx25_add_spi1(struct spi_imx_master *pdata)
+{
+ return imx_add_spi((void *)MX25_CSPI2_BASE_ADDR, 1, pdata);
+}
+
+static inline struct device_d *imx25_add_spi2(struct spi_imx_master *pdata)
+{
+ return imx_add_spi((void *)MX25_CSPI3_BASE_ADDR, 2, pdata);
}
static inline struct device_d *imx25_add_uart0(void)
{
- return imx_add_uart((void *)IMX_UART1_BASE, 0);
+ return imx_add_uart((void *)MX25_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx25_add_uart1(void)
{
- return imx_add_uart((void *)IMX_UART2_BASE, 1);
+ return imx_add_uart((void *)MX25_UART2_BASE_ADDR, 1);
+}
+
+static inline struct device_d *imx25_add_uart2(void)
+{
+ return imx_add_uart((void *)MX25_UART3_BASE_ADDR, 2);
+}
+
+static inline struct device_d *imx25_add_uart3(void)
+{
+ return imx_add_uart((void *)MX25_UART4_BASE_ADDR, 3);
+}
+
+static inline struct device_d *imx25_add_uart4(void)
+{
+ return imx_add_uart((void *)MX25_UART5_BASE_ADDR, 4);
}
static inline struct device_d *imx25_add_nand(struct imx_nand_platform_data *pdata)
{
- return imx_add_nand((void *)IMX_NFC_BASE, pdata);
+ return imx_add_nand((void *)MX25_NFC_BASE_ADDR, pdata);
}
static inline struct device_d *imx25_add_fb(struct imx_fb_platform_data *pdata)
{
- return imx_add_fb((void *)0x53fbc000, pdata);
+ return imx_add_fb((void *)MX25_LCDC_BASE_ADDR, pdata);
}
static inline struct device_d *imx25_add_fec(struct fec_platform_data *pdata)
{
- return imx_add_fec((void *)IMX_FEC_BASE, pdata);
+ return imx_add_fec((void *)MX25_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx25_add_mmc0(struct esdhc_platform_data *pdata)
{
- return imx_add_esdhc((void *)0x53fb4000, 0, pdata);
+ return imx_add_esdhc((void *)MX25_ESDHC1_BASE_ADDR, 0, pdata);
}
+static inline struct device_d *imx25_add_mmc1(struct esdhc_platform_data *pdata)
+{
+ return imx_add_esdhc((void *)MX25_ESDHC2_BASE_ADDR, 1, pdata);
+}
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
index 5176b5e..aca9849 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -26,24 +26,69 @@
# error "Please do not include directly. Use imx-regs.h instead."
#endif
-#define IMX_L2CC_BASE 0x30000000
-#define IMX_UART1_BASE 0x43F90000
-#define IMX_UART2_BASE 0x43F94000
-#define IMX_TIM1_BASE 0x53F90000
-#define IMX_IOMUXC_BASE 0x43FAC000
-#define IMX_WDT_BASE 0x53FDC000
-#define IMX_MAX_BASE 0x43F04000
-#define IMX_ESD_BASE 0xb8001000
-#define IMX_AIPS1_BASE 0x43F00000
-#define IMX_AIPS2_BASE 0x53F00000
-#define IMX_CCM_BASE 0x53F80000
-#define IMX_IIM_BASE 0x53FF0000
-#define IMX_OTG_BASE 0x53FF4000
-#define IMX_M3IF_BASE 0xB8003000
-#define IMX_NFC_BASE 0xBB000000
-#define IMX_FEC_BASE 0x50038000
-#define IMX_I2C1_BASE 0x43F80000
-#define IMX_CSPI1_BASE 0x43FA4000
+#define MX25_AIPS1_BASE_ADDR 0x43f00000
+#define MX25_AIPS1_SIZE SZ_1M
+#define MX25_AIPS2_BASE_ADDR 0x53f00000
+#define MX25_AIPS2_SIZE SZ_1M
+#define MX25_AVIC_BASE_ADDR 0x68000000
+#define MX25_AVIC_SIZE SZ_1M
+
+#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
+#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
+#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
+#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
+#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
+#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
+#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
+
+#define MX25_CCM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
+#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
+#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
+#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
+#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
+#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
+#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
+#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
+#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
+#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
+#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
+
+#define MX25_UART1_BASE_ADDR 0x43f90000
+#define MX25_UART2_BASE_ADDR 0x43f94000
+#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
+#define MX25_UART3_BASE_ADDR 0x5000c000
+#define MX25_UART4_BASE_ADDR 0x50008000
+#define MX25_UART5_BASE_ADDR 0x5002c000
+
+#define MX25_CSPI3_BASE_ADDR 0x50004000
+#define MX25_CSPI2_BASE_ADDR 0x50010000
+#define MX25_FEC_BASE_ADDR 0x50038000
+#define MX25_SSI2_BASE_ADDR 0x50014000
+#define MX25_SSI1_BASE_ADDR 0x50034000
+#define MX25_NFC_BASE_ADDR 0xbb000000
+#define MX25_IIM_BASE_ADDR 0x53ff0000
+#define MX25_DRYICE_BASE_ADDR 0x53ffc000
+#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
+#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
+#define MX25_LCDC_BASE_ADDR 0x53fbc000
+#define MX25_KPP_BASE_ADDR 0x43fa8000
+#define MX25_SDMA_BASE_ADDR 0x53fd4000
+#define MX25_USB_BASE_ADDR 0x53ff4000
+#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
+/*
+ * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
+ * for the host controller. Early documentation drafts specified 0x400 and
+ * Freescale internal sources confirm only the latter value to work.
+ */
+#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
+#define MX25_CSI_BASE_ADDR 0x53ff8000
+
+/* FIXME: Get rid of these */
+#define IMX_TIM1_BASE MX25_GPT1_BASE_ADDR
+#define IMX_IOMUXC_BASE MX25_IOMUXC_BASE_ADDR
+#define IMX_WDT_BASE MX25_WDOG_BASE_ADDR
+#define IMX_CCM_BASE MX25_CCM_BASE_ADDR
+#define IMX_ESD_BASE MX25_ESDCTL_BASE_ADDR
/*
* Clock Controller Module (CCM)
@@ -82,21 +127,23 @@
/*
* Adresses and ranges of the external chip select lines
*/
-#define IMX_CS0_BASE 0xA0000000
-#define IMX_CS0_RANGE (128 * 1024 * 1024)
-#define IMX_CS1_BASE 0xA8000000
-#define IMX_CS1_RANGE (128 * 1024 * 1024)
-#define IMX_CS2_BASE 0xB0000000
-#define IMX_CS2_RANGE (32 * 1024 * 1024)
-#define IMX_CS3_BASE 0xB2000000
-#define IMX_CS3_RANGE (32 * 1024 * 1024)
-#define IMX_CS4_BASE 0xB4000000
-#define IMX_CS4_RANGE (32 * 1024 * 1024)
-#define IMX_CS5_BASE 0xB6000000
-#define IMX_CS5_RANGE (32 * 1024 * 1024)
-
-#define IMX_SDRAM_CS0 0x80000000
-#define IMX_SDRAM_CS1 0x90000000
+#define MX25_CS0_BASE_ADDR 0xA0000000
+#define MX25_CS0_SIZE SZ_128M
+#define MX25_CS1_BASE_ADDR 0xA8000000
+#define MX25_CS1_SIZE SZ_128M
+#define MX25_CS2_BASE_ADDR 0xB0000000
+#define MX25_CS2_SIZE SZ_32M
+#define MX25_CS3_BASE_ADDR 0xB2000000
+#define MX25_CS3_SIZE SZ_32M
+#define MX25_CS4_BASE_ADDR 0xB4000000
+#define MX25_CS4_SIZE SZ_32M
+#define MX25_CS5_BASE_ADDR 0xB6000000
+#define MX25_CS5_SIZE SZ_32M
+
+#define MX25_CSD0_BASE_ADDR 0x80000000
+#define MX25_CSD1_BASE_ADDR 0x90000000
+
+#define MX25_ESDCTL_BASE_ADDR 0xb8001000
#define WEIM_BASE 0xb8002000
#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
@@ -113,14 +160,4 @@
/* important definition of some bits of WCR */
#define WCR_WDE 0x04
-/* IIM fuse definitions */
-#define IIM_BANK_SIZE 32 /* excluding alignment padding for each row */
-#define IIM_BANK0_BASE (IMX_IIM_BASE + 0x800)
-#define IIM_BANK1_BASE (IMX_IIM_BASE + 0xc00)
-#define IIM_BANK2_BASE (IMX_IIM_BASE + 0x1000)
-
-#define IIM_UID (IIM_BANK0_BASE + 0x20)
-#define IIM_MAC_ADDR (IIM_BANK0_BASE + 0x68)
-
#endif /* __ASM_ARCH_MX25_REGS_H */
-
diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c
index 39e68c8..3c85713 100644
--- a/arch/arm/mach-imx/speed-imx25.c
+++ b/arch/arm/mach-imx/speed-imx25.c
@@ -7,13 +7,13 @@
unsigned long imx_get_mpllclk(void)
{
- ulong mpctl = readl(IMX_CCM_BASE + CCM_MPCTL);
+ ulong mpctl = readl(MX25_CCM_BASE_ADDR + CCM_MPCTL);
return imx_decode_pll(mpctl, CONFIG_MX25_HCLK_FREQ);
}
unsigned long imx_get_upllclk(void)
{
- ulong ppctl = readl(IMX_CCM_BASE + CCM_UPCTL);
+ ulong ppctl = readl(MX25_CCM_BASE_ADDR + CCM_UPCTL);
return imx_decode_pll(ppctl, CONFIG_MX25_HCLK_FREQ);
}
@@ -21,7 +21,7 @@ unsigned long imx_get_armclk(void)
{
unsigned long rate, cctl;
- cctl = readl(IMX_CCM_BASE + CCM_CCTL);
+ cctl = readl(MX25_CCM_BASE_ADDR + CCM_CCTL);
rate = imx_get_mpllclk();
if (cctl & (1 << 14)) {
@@ -34,7 +34,7 @@ unsigned long imx_get_armclk(void)
unsigned long imx_get_ahbclk(void)
{
- ulong cctl = readl(IMX_CCM_BASE + CCM_CCTL);
+ ulong cctl = readl(MX25_CCM_BASE_ADDR + CCM_CCTL);
return imx_get_armclk() / (((cctl >> 28) & 0x3) + 1);
}
@@ -52,10 +52,10 @@ unsigned long imx_get_perclk(int per)
{
ulong ofs = (per & 0x3) * 8;
ulong reg = per & ~0x3;
- ulong val = (readl(IMX_CCM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
+ ulong val = (readl(MX25_CCM_BASE_ADDR + CCM_PCDR0 + reg) >> ofs) & 0x3f;
ulong fref;
- if (readl(IMX_CCM_BASE + 0x64) & (1 << per))
+ if (readl(MX25_CCM_BASE_ADDR + 0x64) & (1 << per))
fref = imx_get_upllclk();
else
fref = imx_get_ahbclk();
@@ -114,7 +114,7 @@ void imx_dump_clocks(void)
*/
int imx_clko_set_div(int num, int div)
{
- unsigned long mcr = readl(IMX_CCM_BASE + 0x64);
+ unsigned long mcr = readl(MX25_CCM_BASE_ADDR + 0x64);
if (num != 1)
return -ENODEV;
@@ -125,7 +125,7 @@ int imx_clko_set_div(int num, int div)
mcr &= ~(0x3f << 24);
mcr |= div << 24;
- writel(mcr, IMX_CCM_BASE + 0x64);
+ writel(mcr, MX25_CCM_BASE_ADDR + 0x64);
return div + 1;
}
@@ -135,14 +135,14 @@ int imx_clko_set_div(int num, int div)
*/
void imx_clko_set_src(int num, int src)
{
- unsigned long mcr = readl(IMX_CCM_BASE + 0x64);
+ unsigned long mcr = readl(MX25_CCM_BASE_ADDR + 0x64);
if (num != 1)
return;
if (src < 0) {
mcr &= ~(1 << 30);
- writel(mcr, IMX_CCM_BASE + 0x64);
+ writel(mcr, MX25_CCM_BASE_ADDR + 0x64);
return;
}
@@ -150,6 +150,6 @@ void imx_clko_set_src(int num, int src)
mcr &= ~(0xf << 20);
mcr |= (src & 0xf) << 20;
- writel(mcr, IMX_CCM_BASE + 0x64);
+ writel(mcr, MX25_CCM_BASE_ADDR + 0x64);
}
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 07/14] ARM i.MX/MXS: Allow to include imx*-regs.h directly
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (5 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 06/14] ARM i.MX25: give register base addresses a proper MX25_ prefix Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 08/14] ARM i.MX51: Use defines rather than hardcoded addresses Sascha Hauer
` (6 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
In fact we can be happy about everyone including the files directly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/include/mach/imx1-regs.h | 4 ----
arch/arm/mach-imx/include/mach/imx21-regs.h | 4 ----
arch/arm/mach-imx/include/mach/imx25-regs.h | 7 -------
arch/arm/mach-imx/include/mach/imx27-regs.h | 4 ----
arch/arm/mach-imx/include/mach/imx31-regs.h | 7 -------
arch/arm/mach-imx/include/mach/imx35-regs.h | 7 -------
arch/arm/mach-mxs/include/mach/imx23-regs.h | 7 -------
arch/arm/mach-mxs/include/mach/imx28-regs.h | 7 -------
8 files changed, 47 deletions(-)
diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h
index 52d2dfe..0e07dcd 100644
--- a/arch/arm/mach-imx/include/mach/imx1-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx1-regs.h
@@ -1,10 +1,6 @@
#ifndef _IMX1_REGS_H
#define _IMX1_REGS_H
-#ifndef _IMX_REGS_H
-#error "Please do not include directly"
-#endif
-
#define MX1_IO_BASE_ADDR 0x00200000
#define MX1_IO_SIZE SZ_1M
diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h
index e58af72..6f2000b 100644
--- a/arch/arm/mach-imx/include/mach/imx21-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx21-regs.h
@@ -1,10 +1,6 @@
#ifndef _IMX21_REGS_H
#define _IMX21_REGS_H
-#ifndef _IMX_REGS_H
-#error "Please do not include directly"
-#endif
-
#define MX21_AIPI_BASE_ADDR 0x10000000
#define MX21_AIPI_SIZE SZ_1M
#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
index aca9849..8e7ff85 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -19,13 +19,6 @@
#ifndef __ASM_ARCH_MX25_REGS_H
#define __ASM_ARCH_MX25_REGS_H
-/*
- * sanity check
- */
-#ifndef _IMX_REGS_H
-# error "Please do not include directly. Use imx-regs.h instead."
-#endif
-
#define MX25_AIPS1_BASE_ADDR 0x43f00000
#define MX25_AIPS1_SIZE SZ_1M
#define MX25_AIPS2_BASE_ADDR 0x53f00000
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index 907afa4..6e47b28 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -1,10 +1,6 @@
#ifndef _IMX27_REGS_H
#define _IMX27_REGS_H
-#ifndef _IMX_REGS_H
-#error "Please do not include directly"
-#endif
-
#define MX27_AIPI_BASE_ADDR 0x10000000
#define MX27_AIPI_SIZE SZ_1M
#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h
index 4d0efd5..e912665 100644
--- a/arch/arm/mach-imx/include/mach/imx31-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx31-regs.h
@@ -21,13 +21,6 @@
#include <sizes.h>
-/*
- * sanity check
- */
-#ifndef _IMX_REGS_H
-# error "Please do not include directly. Use imx-regs.h instead."
-#endif
-
#define MX31_AIPS1_BASE_ADDR 0x43f00000
#define MX31_AIPS1_SIZE SZ_1M
#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 0a4f423..223e629 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -21,13 +21,6 @@
#include <sizes.h>
-/*
- * sanity check
- */
-#ifndef _IMX_REGS_H
-# error "Please do not include directly. Use imx-regs.h instead."
-#endif
-
#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
#define MX35_IRAM_SIZE SZ_128K
diff --git a/arch/arm/mach-mxs/include/mach/imx23-regs.h b/arch/arm/mach-mxs/include/mach/imx23-regs.h
index ade3139..7fb664b 100644
--- a/arch/arm/mach-mxs/include/mach/imx23-regs.h
+++ b/arch/arm/mach-mxs/include/mach/imx23-regs.h
@@ -15,13 +15,6 @@
#ifndef __ASM_ARCH_MX23_REGS_H
#define __ASM_ARCH_MX23_REGS_H
-/*
- * sanity check
- */
-#ifndef _IMX_REGS_H
-# error "Please do not include directly. Use imx-regs.h instead."
-#endif
-
#define IMX_MEMORY_BASE 0x40000000
#define MXS_APBH_BASE 0x80004000
#define MXS_BCH_BASE 0x8000a000
diff --git a/arch/arm/mach-mxs/include/mach/imx28-regs.h b/arch/arm/mach-mxs/include/mach/imx28-regs.h
index 16bf5f7..fa8edd7 100644
--- a/arch/arm/mach-mxs/include/mach/imx28-regs.h
+++ b/arch/arm/mach-mxs/include/mach/imx28-regs.h
@@ -13,13 +13,6 @@
#ifndef __ASM_ARCH_MX28_REGS_H
#define __ASM_ARCH_MX28_REGS_H
-/*
- * sanity check
- */
-#ifndef _IMX_REGS_H
-# error "Please do not include directly. Use imx-regs.h instead."
-#endif
-
#define IMX_SRAM_BASE 0x00000000
#define IMX_MEMORY_BASE 0x40000000
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 08/14] ARM i.MX51: Use defines rather than hardcoded addresses
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (6 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 07/14] ARM i.MX/MXS: Allow to include imx*-regs.h directly Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 09/14] ARM i.MX: Add header file for WEIM cs setup Sascha Hauer
` (5 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/imx51.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 022614f..b1eeb0c 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -74,11 +74,11 @@ static int imx51_init(void)
add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpt", 0, NULL, 0x73fa0000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 0, NULL, 0x73f84000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 1, NULL, 0x73f88000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 2, NULL, 0x73f8c000, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx31-gpio", 3, NULL, 0x73f90000, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpt", 0, NULL, MX51_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 0, NULL, MX51_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 1, NULL, MX51_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 2, NULL, MX51_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 3, NULL, MX51_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 09/14] ARM i.MX: Add header file for WEIM cs setup
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (7 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 08/14] ARM i.MX51: Use defines rather than hardcoded addresses Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 10/14] ARM i.MX1: Add function to setup chipselect Sascha Hauer
` (4 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c | 1 +
arch/arm/boards/imx27ads/imx27ads.c | 1 +
arch/arm/boards/pcm038/pcm038.c | 1 +
arch/arm/boards/pcm038/pcm970.c | 1 +
arch/arm/mach-imx/imx27.c | 9 +++++++++
arch/arm/mach-imx/include/mach/imx27-regs.h | 10 ----------
arch/arm/mach-imx/include/mach/weim.h | 7 +++++++
7 files changed, 20 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/mach-imx/include/mach/weim.h
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index 0ffe43f..cff4f77 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -37,6 +37,7 @@
#include <io.h>
#include <mach/imx-nand.h>
#include <mach/imx-pll.h>
+#include <mach/weim.h>
#include <mach/imxfb.h>
#include <ns16550.h>
#include <asm/mmu.h>
diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c
index f9416e1..22c6e40 100644
--- a/arch/arm/boards/imx27ads/imx27ads.c
+++ b/arch/arm/boards/imx27ads/imx27ads.c
@@ -23,6 +23,7 @@
#include <io.h>
#include <fec.h>
#include <mach/gpio.h>
+#include <mach/weim.h>
#include <partition.h>
#include <fs.h>
#include <fcntl.h>
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index a51825b..58b1ec9 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -31,6 +31,7 @@
#include <io.h>
#include <mach/imx-nand.h>
#include <mach/imx-pll.h>
+#include <mach/weim.h>
#include <mach/imxfb.h>
#include <i2c/i2c.h>
#include <mach/spi.h>
diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c
index d392ea4..b8fc65b 100644
--- a/arch/arm/boards/pcm038/pcm970.c
+++ b/arch/arm/boards/pcm038/pcm970.c
@@ -18,6 +18,7 @@
#include <platform_ide.h>
#include <mach/imx-regs.h>
#include <mach/iomux-mx27.h>
+#include <mach/weim.h>
#include <mach/gpio.h>
#include <mach/devices-imx27.h>
#include <usb/ulpi.h>
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index 76bb910..0c92385 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <mach/imx-regs.h>
+#include <mach/weim.h>
#include <sizes.h>
#include <init.h>
#include <io.h>
@@ -22,6 +23,14 @@ int imx_silicon_revision(void)
return CID >> 28;
}
+void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
+ unsigned additional)
+{
+ writel(upper, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x0);
+ writel(lower, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
+ writel(additional, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x8);
+}
+
/*
* Initialize MAX on i.MX27. necessary to give the DMA engine
* higher priority to the memory than the CPU. Needed for proper
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index 6e47b28..5db1a3c 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -278,14 +278,4 @@
#define ESDCFG_TWTR (1 << 20)
#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
-#ifndef __ASSEMBLY__
-#include <io.h>
-static inline void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned additional)
-{
- writel(upper, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x0);
- writel(lower, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
- writel(additional, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
-}
-#endif /* __ASSEMBLY__ */
-
#endif /* _IMX27_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h
new file mode 100644
index 0000000..bc9b51e
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/weim.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_WEIM_H
+#define __MACH_WEIM_H
+
+void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
+ unsigned additional);
+
+#endif /* __MACH_WEIM_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 10/14] ARM i.MX1: Add function to setup chipselect
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (8 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 09/14] ARM i.MX: Add header file for WEIM cs setup Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 11/14] ARM i.MX21: " Sascha Hauer
` (3 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/scb9328/scb9328.c | 19 ++++++-------------
arch/arm/mach-imx/imx1.c | 8 ++++++++
arch/arm/mach-imx/include/mach/imx1-regs.h | 15 ---------------
arch/arm/mach-imx/include/mach/weim.h | 2 ++
4 files changed, 16 insertions(+), 28 deletions(-)
diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
index 9bd9a7c..c83132a 100644
--- a/arch/arm/boards/scb9328/scb9328.c
+++ b/arch/arm/boards/scb9328/scb9328.c
@@ -22,6 +22,7 @@
#include <mach/imx-regs.h>
#include <asm/armlinux.h>
#include <mach/gpio.h>
+#include <mach/weim.h>
#include <io.h>
#include <partition.h>
#include <fs.h>
@@ -70,19 +71,11 @@ static int scb9328_devices_init(void)
/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
FMCR = 0x1;
- CS0U = 0x000F2000;
- CS0L = 0x11110d01;
-
- CS1U = 0x000F0a00;
- CS1L = 0x11110601;
- CS2U = 0x0;
- CS2L = 0x0;
- CS3U = 0x000FFFFF;
- CS3L = 0x00000303;
- CS4U = 0x000F0a00;
- CS4L = 0x11110301;
- CS5U = 0x00008400;
- CS5L = 0x00000D03;
+ imx1_setup_eimcs(0, 0x000F2000, 0x11110d01);
+ imx1_setup_eimcs(1, 0x000F0a00, 0x11110601);
+ imx1_setup_eimcs(3, 0x000FFFFF, 0x00000303);
+ imx1_setup_eimcs(4, 0x000F0a00, 0x11110301);
+ imx1_setup_eimcs(5, 0x00008400, 0x00000D03);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x10000000, 16 * 1024 * 1024, 0);
add_dm9000_device(DEVICE_ID_DYNAMIC, 0x16000000, 0x16000004,
diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c
index e6fba16..536a9ad 100644
--- a/arch/arm/mach-imx/imx1.c
+++ b/arch/arm/mach-imx/imx1.c
@@ -13,7 +13,15 @@
#include <common.h>
#include <init.h>
+#include <io.h>
#include <mach/imx-regs.h>
+#include <mach/weim.h>
+
+void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
+{
+ writel(upper, MX1_EIM_BASE_ADDR + cs * 8);
+ writel(lower, MX1_EIM_BASE_ADDR + 4 + cs * 8);
+}
static int imx1_init(void)
{
diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h
index 0e07dcd..cb60c84 100644
--- a/arch/arm/mach-imx/include/mach/imx1-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx1-regs.h
@@ -86,21 +86,6 @@
#define CSCR_MPLL_RESTART (1<<21)
-/* Chip Select Registers */
-#define CS0U __REG(MX1_EIM_BASE_ADDR) /* Chip Select 0 Upper Register */
-#define CS0L __REG(MX1_EIM_BASE_ADDR + 0x4) /* Chip Select 0 Lower Register */
-#define CS1U __REG(MX1_EIM_BASE_ADDR + 0x8) /* Chip Select 1 Upper Register */
-#define CS1L __REG(MX1_EIM_BASE_ADDR + 0xc) /* Chip Select 1 Lower Register */
-#define CS2U __REG(MX1_EIM_BASE_ADDR + 0x10) /* Chip Select 2 Upper Register */
-#define CS2L __REG(MX1_EIM_BASE_ADDR + 0x14) /* Chip Select 2 Lower Register */
-#define CS3U __REG(MX1_EIM_BASE_ADDR + 0x18) /* Chip Select 3 Upper Register */
-#define CS3L __REG(MX1_EIM_BASE_ADDR + 0x1c) /* Chip Select 3 Lower Register */
-#define CS4U __REG(MX1_EIM_BASE_ADDR + 0x20) /* Chip Select 4 Upper Register */
-#define CS4L __REG(MX1_EIM_BASE_ADDR + 0x24) /* Chip Select 4 Lower Register */
-#define CS5U __REG(MX1_EIM_BASE_ADDR + 0x28) /* Chip Select 5 Upper Register */
-#define CS5L __REG(MX1_EIM_BASE_ADDR + 0x2c) /* Chip Select 5 Lower Register */
-#define EIM __REG(MX1_EIM_BASE_ADDR + 0x30) /* EIM Configuration Register */
-
/* assignements for GPIO alternate/primary functions */
/* FIXME: This list is not completed. The correct directions are
diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h
index bc9b51e..a15726f 100644
--- a/arch/arm/mach-imx/include/mach/weim.h
+++ b/arch/arm/mach-imx/include/mach/weim.h
@@ -4,4 +4,6 @@
void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
unsigned additional);
+void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
+
#endif /* __MACH_WEIM_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 11/14] ARM i.MX21: Add function to setup chipselect
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (9 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 10/14] ARM i.MX1: Add function to setup chipselect Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 12/14] ARM i.MX31: " Sascha Hauer
` (2 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/imx21ads/imx21ads.c | 27 +++++++++------------------
arch/arm/mach-imx/imx21.c | 8 ++++++++
arch/arm/mach-imx/include/mach/imx21-regs.h | 16 ----------------
arch/arm/mach-imx/include/mach/weim.h | 2 ++
4 files changed, 19 insertions(+), 34 deletions(-)
diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c
index 42b0162..22406be 100644
--- a/arch/arm/boards/imx21ads/imx21ads.c
+++ b/arch/arm/boards/imx21ads/imx21ads.c
@@ -27,6 +27,7 @@
#include <asm/barebox-arm.h>
#include <io.h>
#include <mach/gpio.h>
+#include <mach/weim.h>
#include <partition.h>
#include <fs.h>
#include <fcntl.h>
@@ -83,26 +84,16 @@ static int imx21ads_timing_init(void)
/* Configure External Interface Module */
/* CS0: burst flash */
- CS0U = 0x00003E00;
- CS0L = 0x00000E01;
+ imx21_setup_eimcs(0, 0x00003E00, 0x00000E01);
/* CS1: Ethernet controller, external UART, memory-mapped I/O (16-bit) */
- CS1U = 0x00002000;
- CS1L = 0x11118501;
-
- /* CS2: disable (not available, since CSD0 in use) */
- CS2U = 0x0;
- CS2L = 0x0;
-
- /* CS3: disable */
- CS3U = 0x0;
- CS3L = 0x0;
- /* CS4: disable */
- CS4U = 0x0;
- CS4L = 0x0;
- /* CS5: disable */
- CS5U = 0x0;
- CS5L = 0x0;
+ imx21_setup_eimcs(1, 0x00002000, 0x11118501);
+
+ /* CS2-CS5: disable */
+ imx21_setup_eimcs(2, 0x0, 0x0);
+ imx21_setup_eimcs(3, 0x0, 0x0);
+ imx21_setup_eimcs(4, 0x0, 0x0);
+ imx21_setup_eimcs(5, 0x0, 0x0);
temp = PCDR0;
temp &= ~0xF000;
diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c
index 8d909ce..5448ca4 100644
--- a/arch/arm/mach-imx/imx21.c
+++ b/arch/arm/mach-imx/imx21.c
@@ -13,7 +13,15 @@
#include <common.h>
#include <init.h>
+#include <io.h>
#include <mach/imx-regs.h>
+#include <mach/weim.h>
+
+void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
+{
+ writel(upper, MX21_EIM_BASE_ADDR + cs * 8);
+ writel(lower, MX21_EIM_BASE_ADDR + 4 + cs * 8);
+}
int imx_silicon_revision(void)
{
diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h
index 6f2000b..9952b8b 100644
--- a/arch/arm/mach-imx/include/mach/imx21-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx21-regs.h
@@ -108,22 +108,6 @@
#define SDRST __REG(MX21_X_MEMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */
#define SDMISC __REG(MX21_X_MEMC_BASE_ADDR + 0x14) /* SDRAM Miscellaneous Register */
-
-/* Chip Select Registers */
-#define CS0U __REG(MX21_EIM_BASE_ADDR + 0x00) /* Chip Select 0 Upper Register */
-#define CS0L __REG(MX21_EIM_BASE_ADDR + 0x04) /* Chip Select 0 Lower Register */
-#define CS1U __REG(MX21_EIM_BASE_ADDR + 0x08) /* Chip Select 1 Upper Register */
-#define CS1L __REG(MX21_EIM_BASE_ADDR + 0x0C) /* Chip Select 1 Lower Register */
-#define CS2U __REG(MX21_EIM_BASE_ADDR + 0x10) /* Chip Select 2 Upper Register */
-#define CS2L __REG(MX21_EIM_BASE_ADDR + 0x14) /* Chip Select 2 Lower Register */
-#define CS3U __REG(MX21_EIM_BASE_ADDR + 0x18) /* Chip Select 3 Upper Register */
-#define CS3L __REG(MX21_EIM_BASE_ADDR + 0x1C) /* Chip Select 3 Lower Register */
-#define CS4U __REG(MX21_EIM_BASE_ADDR + 0x20) /* Chip Select 4 Upper Register */
-#define CS4L __REG(MX21_EIM_BASE_ADDR + 0x24) /* Chip Select 4 Lower Register */
-#define CS5U __REG(MX21_EIM_BASE_ADDR + 0x28) /* Chip Select 5 Upper Register */
-#define CS5L __REG(MX21_EIM_BASE_ADDR + 0x2C) /* Chip Select 5 Lower Register */
-#define EIM __REG(MX21_EIM_BASE_ADDR + 0x30) /* EIM Configuration Register */
-
/* PLL registers */
#define CSCR __REG(MX21_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */
#define MPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */
diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h
index a15726f..c9fa301 100644
--- a/arch/arm/mach-imx/include/mach/weim.h
+++ b/arch/arm/mach-imx/include/mach/weim.h
@@ -6,4 +6,6 @@ void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
+void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
+
#endif /* __MACH_WEIM_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 12/14] ARM i.MX31: Add function to setup chipselect
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (10 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 11/14] ARM i.MX21: " Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 13/14] ARM i.MX35: " Sascha Hauer
2012-09-24 10:46 ` [PATCH 14/14] ARM i.MX25: " Sascha Hauer
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm037/pcm037.c | 24 +++++++++---------------
arch/arm/mach-imx/imx31.c | 10 ++++++++++
arch/arm/mach-imx/include/mach/imx31-regs.h | 8 --------
arch/arm/mach-imx/include/mach/weim.h | 3 +++
4 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index a63bd23..1a1688d 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -29,6 +29,7 @@
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <mach/gpio.h>
+#include <mach/weim.h>
#include <io.h>
#include <asm/mmu.h>
#include <partition.h>
@@ -165,21 +166,14 @@ postmmu_initcall(pcm037_mmu_init);
static int imx31_devices_init(void)
{
- __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
- __REG(CSCR_L(0)) = 0x10000d03;
- __REG(CSCR_A(0)) = 0x00720900;
-
- __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
- __REG(CSCR_L(1)) = 0x444a4541;
- __REG(CSCR_A(1)) = 0x44443302;
-
- __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
- __REG(CSCR_L(4)) = 0x22252521;
- __REG(CSCR_A(4)) = 0x22220a00;
-
- __REG(CSCR_U(5)) = 0x0000DCF6; /* CS5: SJA1000 */
- __REG(CSCR_L(5)) = 0x444A0301;
- __REG(CSCR_A(5)) = 0x44443302;
+ /* CS0: Nor Flash */
+ imx31_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
+ /* CS1: Network Controller */
+ imx31_setup_weimcs(1, 0x0000df06, 0x444a4541, 0x44443302);
+ /* CS4: SRAM */
+ imx31_setup_weimcs(4, 0x0000d843, 0x22252521, 0x22220a00);
+ /* CS5: SJA1000 */
+ imx31_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302);
/*
* Up to 32MiB NOR type flash, connected to
diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c
index 60745a7..11d8f49 100644
--- a/arch/arm/mach-imx/imx31.c
+++ b/arch/arm/mach-imx/imx31.c
@@ -14,7 +14,17 @@
#include <common.h>
#include <init.h>
#include <sizes.h>
+#include <io.h>
#include <mach/imx-regs.h>
+#include <mach/weim.h>
+
+void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
+ unsigned additional)
+{
+ writel(upper, MX31_WEIM_BASE_ADDR + (cs * 0x10) + 0x0);
+ writel(lower, MX31_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
+ writel(additional, MX31_WEIM_BASE_ADDR + (cs * 0x10) + 0x8);
+}
static int imx31_init(void)
{
diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h
index e912665..57f65da 100644
--- a/arch/arm/mach-imx/include/mach/imx31-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx31-regs.h
@@ -175,14 +175,6 @@
#include "esdctl.h"
/*
- * Chip Select Registers
- */
-#define WEIM_BASE 0xb8002000
-#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
-#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
-#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
-
-/*
* ???????????
*/
#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h
index c9fa301..40e7b6e 100644
--- a/arch/arm/mach-imx/include/mach/weim.h
+++ b/arch/arm/mach-imx/include/mach/weim.h
@@ -4,6 +4,9 @@
void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
unsigned additional);
+void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
+ unsigned additional);
+
void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 13/14] ARM i.MX35: Add function to setup chipselect
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (11 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 12/14] ARM i.MX31: " Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 10:46 ` [PATCH 14/14] ARM i.MX25: " Sascha Hauer
13 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/freescale-mx35-3-stack/3stack.c | 10 ++++------
arch/arm/boards/guf-cupid/board.c | 6 +++---
arch/arm/boards/pcm043/pcm043.c | 5 ++---
arch/arm/mach-imx/imx35.c | 9 +++++++++
arch/arm/mach-imx/include/mach/imx35-regs.h | 5 -----
arch/arm/mach-imx/include/mach/weim.h | 3 +++
6 files changed, 21 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index 3d4a9cf..9a01424 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -39,6 +39,7 @@
#include <generated/mach-types.h>
#include <mach/gpio.h>
+#include <mach/weim.h>
#include <mach/imx-nand.h>
#include <mach/imx-regs.h>
#include <mach/iomux-mx35.h>
@@ -140,9 +141,7 @@ static int f3s_devices_init(void)
uint32_t reg;
/* CS0: Nor Flash */
- writel(0x0000cf03, CSCR_U(0));
- writel(0x10000d03, CSCR_L(0));
- writel(0x00720900, CSCR_A(0));
+ imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
@@ -278,9 +277,8 @@ static int f3s_core_init(void)
{
u32 reg;
- writel(0x0000D843, CSCR_U(5)); /* CS5: smc9117 */
- writel(0x22252521, CSCR_L(5));
- writel(0x22220A00, CSCR_A(5));
+ /* CS5: smc9117 */
+ imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00);
/* enable clock for I2C1 and FEC */
reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
index 977d71c..933a9cd 100644
--- a/arch/arm/boards/guf-cupid/board.c
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -36,6 +36,7 @@
#include <fec.h>
#include <fb.h>
#include <asm/mmu.h>
+#include <mach/weim.h>
#include <mach/imx-ipu-fb.h>
#include <mach/imx-pll.h>
#include <mach/iomux-mx35.h>
@@ -301,9 +302,8 @@ static int cupid_core_setup(void)
writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */
writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */
- writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */
- writel(0x444A4541, CSCR_L(0));
- writel(0x44443302, CSCR_A(0));
+ /* CS0: NOR Flash */
+ imx35_setup_weimcs(0, 0x0000DCF6, 0x444A4541, 0x44443302);
/*
* M3IF Control Register (M3IFCTL)
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 3b4ec77..09bc96a 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -38,6 +38,7 @@
#include <fb.h>
#include <led.h>
#include <asm/mmu.h>
+#include <mach/weim.h>
#include <mach/imx-ipu-fb.h>
#include <mach/imx-pll.h>
#include <mach/iomux-mx35.h>
@@ -122,9 +123,7 @@ static int imx35_devices_init(void)
uint32_t reg;
/* CS0: Nor Flash */
- writel(0x22C0CF00, CSCR_U(0));
- writel(0x75000D01, CSCR_L(0));
- writel(0x00000900, CSCR_A(0));
+ imx35_setup_weimcs(5, 0x22C0CF00, 0x75000D01, 0x00000900);
led_gpio_register(&led0);
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 2e94f17..2a9f576 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -15,10 +15,19 @@
#include <sizes.h>
#include <init.h>
#include <io.h>
+#include <mach/weim.h>
#include <mach/imx-regs.h>
#include <mach/iim.h>
#include <mach/generic.h>
+void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
+ unsigned additional)
+{
+ writel(upper, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x0);
+ writel(lower, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
+ writel(additional, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x8);
+}
+
int imx_silicon_revision()
{
uint32_t reg;
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 223e629..773b414 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -172,9 +172,4 @@
#define PDR0_AUTO_CON (1 << 0)
#define PDR0_PER_SEL (1 << 26)
-#define WEIM_BASE 0xb8002000
-#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
-#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
-#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
-
#endif /* __ASM_ARCH_MX35_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h
index 40e7b6e..576f87c 100644
--- a/arch/arm/mach-imx/include/mach/weim.h
+++ b/arch/arm/mach-imx/include/mach/weim.h
@@ -7,6 +7,9 @@ void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
unsigned additional);
+void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
+ unsigned additional);
+
void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 14/14] ARM i.MX25: Add function to setup chipselect
2012-09-24 10:46 [PATCH] i.MX register cleanups Sascha Hauer
` (12 preceding siblings ...)
2012-09-24 10:46 ` [PATCH 13/14] ARM i.MX35: " Sascha Hauer
@ 2012-09-24 10:46 ` Sascha Hauer
2012-09-24 12:04 ` Roberto Nibali
13 siblings, 1 reply; 16+ messages in thread
From: Sascha Hauer @ 2012-09-24 10:46 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/imx25.c | 9 +++++++++
arch/arm/mach-imx/include/mach/imx25-regs.h | 6 +-----
arch/arm/mach-imx/include/mach/weim.h | 3 +++
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index 3f44649..32c0412 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -16,8 +16,17 @@
#include <mach/imx-regs.h>
#include <mach/iim.h>
#include <io.h>
+#include <mach/weim.h>
#include <sizes.h>
+void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
+ unsigned additional)
+{
+ writel(upper, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x0);
+ writel(lower, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
+ writel(additional, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x8);
+}
+
/* IIM fuse definitions */
#define IIM_BANK0_BASE (MX25_IIM_BASE_ADDR + 0x800)
#define IIM_BANK1_BASE (MX25_IIM_BASE_ADDR + 0xc00)
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
index 8e7ff85..0bf6e11 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -137,11 +137,7 @@
#define MX25_CSD1_BASE_ADDR 0x90000000
#define MX25_ESDCTL_BASE_ADDR 0xb8001000
-
-#define WEIM_BASE 0xb8002000
-#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
-#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
-#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
+#define MX25_WEIM_BASE_ADDR 0xb8002000
/*
* Watchdog Registers
diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h
index 576f87c..8d572dc 100644
--- a/arch/arm/mach-imx/include/mach/weim.h
+++ b/arch/arm/mach-imx/include/mach/weim.h
@@ -10,6 +10,9 @@ void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
unsigned additional);
+void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
+ unsigned additional);
+
void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 14/14] ARM i.MX25: Add function to setup chipselect
2012-09-24 10:46 ` [PATCH 14/14] ARM i.MX25: " Sascha Hauer
@ 2012-09-24 12:04 ` Roberto Nibali
0 siblings, 0 replies; 16+ messages in thread
From: Roberto Nibali @ 2012-09-24 12:04 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Hi
Great series in general, nice cleanup!
> arch/arm/mach-imx/imx25.c | 9 +++++++++
> arch/arm/mach-imx/include/mach/imx25-regs.h | 6 +-----
> arch/arm/mach-imx/include/mach/weim.h | 3 +++
> 3 files changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
> index 3f44649..32c0412 100644
> --- a/arch/arm/mach-imx/imx25.c
> +++ b/arch/arm/mach-imx/imx25.c
> @@ -16,8 +16,17 @@
> #include <mach/imx-regs.h>
> #include <mach/iim.h>
> #include <io.h>
> +#include <mach/weim.h>
> #include <sizes.h>
>
> +void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
> + unsigned additional)
> +{
> + writel(upper, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x0);
> + writel(lower, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
> + writel(additional, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x8);
> +}
> +
> /* IIM fuse definitions */
> #define IIM_BANK0_BASE (MX25_IIM_BASE_ADDR + 0x800)
> #define IIM_BANK1_BASE (MX25_IIM_BASE_ADDR + 0xc00)
> diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
> index 8e7ff85..0bf6e11 100644
> --- a/arch/arm/mach-imx/include/mach/imx25-regs.h
> +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
> @@ -137,11 +137,7 @@
> #define MX25_CSD1_BASE_ADDR 0x90000000
>
> #define MX25_ESDCTL_BASE_ADDR 0xb8001000
> -
> -#define WEIM_BASE 0xb8002000
> -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
> -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
> -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
> +#define MX25_WEIM_BASE_ADDR 0xb8002000
>
> /*
> * Watchdog Registers
> diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h
> index 576f87c..8d572dc 100644
> --- a/arch/arm/mach-imx/include/mach/weim.h
> +++ b/arch/arm/mach-imx/include/mach/weim.h
> @@ -10,6 +10,9 @@ void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
> void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
> unsigned additional);
>
> +void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
> + unsigned additional);
> +
> void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
>
> void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
This allows me to drop my ugly version of the WEIMCS setup from June
based on imx27. Now, if only I got barebox to recognize the NOR on my
platform :).
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h
b/arch/arm/mach-imx/include/mach/imx25-regs.h
index 73307c4..8225832 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -72,6 +72,7 @@
#define CCM_LTR1 0x44
#define CCM_LTR2 0x48
#define CCM_LTR3 0x4c
+#define CCM_MCR 0x64
#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
@@ -107,6 +108,22 @@
#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
+/* Chip Select Registers */
+#define IMX_WEIM_BASE WEIM_BASE
+#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip
Select x Upper Register */
+#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip
Select x Lower Register */
+#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip
Select x Addition Register */
+#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */
+
+#ifndef __ASSEMBLY__
+static inline void imx25_setup_weimcs(size_t cs, unsigned upper,
unsigned lower, unsigned addional)
+{
+ CSxU(cs) = upper;
+ CSxL(cs) = lower;
+ CSxA(cs) = addional;
+}
+#endif /* __ASSEMBLY__ */
+
/*
* Definitions for the clocksource driver
*
Cheers
Roberto
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^ permalink raw reply [flat|nested] 16+ messages in thread