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Fri, 04 Apr 2025 00:39:54 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Alexander Shiyan Date: Fri, 4 Apr 2025 10:39:42 +0300 X-Gm-Features: AQ5f1JpYixq4iX-zjPoIPkLULxOcjQqV57qFTOeiVOiRndQkLpjfJq-OTAudm10 Message-ID: To: Sascha Hauer Cc: Barebox List Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250404_003955_733631_29DDC23B X-CRM114-Status: GOOD ( 22.58 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.9 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: RK3588 CPLL question X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Hello. Yes, this is the best option, but it is not possible yet. Any change in CPL= L frequency causes the system to freeze. I am still trying to figure this out= . Thanks! =D0=BF=D1=82, 4 =D0=B0=D0=BF=D1=80. 2025=E2=80=AF=D0=B3. =D0=B2 10:29, Sasc= ha Hauer : > > On Thu, Apr 03, 2025 at 05:20:33PM +0300, Alexander Shiyan wrote: > > I found this hack: > > https://github.com/u-boot/u-boot/blob/master/drivers/clk/rockchip/clk_r= k3588.c#L1933 > > Let's do the same then. > > It would be nicer to have the CPLL setting in the assigned-clock-rates > property. That should be done in the upstream dtsi though, overwriting > the assigned-clock-rates in the barebox dtsi would mean we would have to > copy the many existing settings and hope they don't change upstream. > > Sascha > > > > > =D1=87=D1=82, 3 =D0=B0=D0=BF=D1=80. 2025=E2=80=AF=D0=B3. =D0=B2 17:08, = Sascha Hauer : > > > > > > On Thu, Apr 03, 2025 at 05:01:05PM +0300, Alexander Shiyan wrote: > > > > Thanks Sascha! > > > > > > > > So something is wrong here. > > > > At least the GMAC0/1 interfaces end up with the wrong frequency. > > > > I have another image with u-boot and Rockchip kernel where CPLL > > > > is 1.5GHz and network is ok. > > > > > > The only place where the PLL rates are configured in barebox is via > > > assigned-clock-rates in the clock controller node. PLL_CPLL doesn't s= how > > > up there, so I would assume it is just left to the default whatever t= hat > > > is. > > > > > > You could chainload barebox from U-Boot and see what the CPLL rate is > > > then. > > > > > > Sascha > > > > > > -- > > > Pengutronix e.K. | = | > > > Steuerwalder Str. 21 | http://www.pengutronix.d= e/ | > > > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0= | > > > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5= 555 | > > > > -- > Pengutronix e.K. | = | > Steuerwalder Str. 21 | http://www.pengutronix.de/ = | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 = | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 = |