[PATCH 1/2] ARM: dts: rockchip: Set initial CPU frequencies for RK3588

[PATCH 1/2] ARM: dts: rockchip: Set initial CPU frequencies for RK3588

[Alexander Shiyan]

During system boot, the cpufreq driver reports unlisted initial frequencies:
cpufreq: cpufreq_policy_online: CPU0: Running at unlisted initial frequency: 900000 kHz, changing to: 1200000 kHz
cpufreq: cpufreq_policy_online: CPU4: Running at unlisted initial frequency: 816000 kHz, changing to: 1200000 kHz
cpufreq: cpufreq_policy_online: CPU6: Running at unlisted initial frequency: 816000 kHz, changing to: 1200000 kHz

Add assigned-clock-rates to the SCMI clock controller node in the device
tree to establish proper initial frequencies.
This ensures all CPU cores boot at valid frequencies that match the
cpufreq policy, eliminating the warning messages and unnecessary
frequency changes during initialization.

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 arch/arm/dts/rk3588.dtsi | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
index 667dd0c5a8..416700cf0e 100644
--- a/arch/arm/dts/rk3588.dtsi
+++ b/arch/arm/dts/rk3588.dtsi
@@ -8,7 +8,12 @@ dmc: memory-controller {
 };
 
 &scmi_clk {
-	assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,
-			  <&scmi_clk SCMI_CLK_CPUB23>;
-	assigned-clock-rates = <816000000>, <816000000>;
+	assigned-clocks =
+		<&scmi_clk SCMI_CLK_CPUL>,
+		<&scmi_clk SCMI_CLK_CPUB01>,
+		<&scmi_clk SCMI_CLK_CPUB23>;
+	assigned-clock-rates =
+		<1200000000>,
+		<1200000000>,
+		<1200000000>;
 };
-- 
2.38.2

[PATCH 2/2] ARM: dts: rockchip: Set CPLL frequency for RK3588

[Alexander Shiyan]

Explicitly configure CPLL frequency to 1500 MHz to ensure system
stability and reliable operation.
The change aligns with Rockchip's recommended practices for clock
configuration in embedded systems using RK3588 SoCs.
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 arch/arm/dts/rk3588.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
index 416700cf0e..42d692a9bd 100644
--- a/arch/arm/dts/rk3588.dtsi
+++ b/arch/arm/dts/rk3588.dtsi
@@ -1,6 +1,9 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 
 / {
+	assigned-clocks = <&cru PLL_CPLL>;
+	assigned-clock-rates = <1500000000>;
+
 	dmc: memory-controller {
 		compatible = "rockchip,rk3588-dmc";
 		rockchip,pmu = <&pmu1grf>;
-- 
2.38.2

Re: [PATCH 1/2] ARM: dts: rockchip: Set initial CPU frequencies for RK3588

[Sascha Hauer]

On Mon, 29 Sep 2025 16:58:56 +0300, Alexander Shiyan wrote:
> During system boot, the cpufreq driver reports unlisted initial frequencies:
> cpufreq: cpufreq_policy_online: CPU0: Running at unlisted initial frequency: 900000 kHz, changing to: 1200000 kHz
> cpufreq: cpufreq_policy_online: CPU4: Running at unlisted initial frequency: 816000 kHz, changing to: 1200000 kHz
> cpufreq: cpufreq_policy_online: CPU6: Running at unlisted initial frequency: 816000 kHz, changing to: 1200000 kHz
> 
> Add assigned-clock-rates to the SCMI clock controller node in the device
> tree to establish proper initial frequencies.
> This ensures all CPU cores boot at valid frequencies that match the
> cpufreq policy, eliminating the warning messages and unnecessary
> frequency changes during initialization.
> 
> [...]

Applied, thanks!

[1/2] ARM: dts: rockchip: Set initial CPU frequencies for RK3588
      https://git.pengutronix.de/cgit/barebox/commit/?id=c5a8ecc95eb9 (link may not be stable)
[2/2] ARM: dts: rockchip: Set CPLL frequency for RK3588
      https://git.pengutronix.de/cgit/barebox/commit/?id=e5ca5163ac08 (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>

Re: [PATCH 2/2] ARM: dts: rockchip: Set CPLL frequency for RK3588

[Michael Tretter]

Hi Alexander,

On Mon, 29 Sep 2025 16:58:57 +0300, Alexander Shiyan wrote:
> Explicitly configure CPLL frequency to 1500 MHz to ensure system
> stability and reliable operation.
> The change aligns with Rockchip's recommended practices for clock
> configuration in embedded systems using RK3588 SoCs.

This change breaks eMMC operation in barebox on ROCK 5T boards. I get
the following alert during barebox boot:

	ALERT: rk3568-dwcmshc-sdhci fe2e0000.mmc@fe2e0000.of: DMA wait timed out. Resetting, but recovery unlikely
	WARNING: mmc0: Card's startup fails with -110

I fumbled a bit with the clocks, especially the aclk_emmc, but no
improvement so far.

Michael

> Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
> ---
>  arch/arm/dts/rk3588.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
> index 416700cf0e..42d692a9bd 100644
> --- a/arch/arm/dts/rk3588.dtsi
> +++ b/arch/arm/dts/rk3588.dtsi
> @@ -1,6 +1,9 @@
>  // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>  
>  / {
> +	assigned-clocks = <&cru PLL_CPLL>;
> +	assigned-clock-rates = <1500000000>;
> +
>  	dmc: memory-controller {
>  		compatible = "rockchip,rk3588-dmc";
>  		rockchip,pmu = <&pmu1grf>;

Re: [PATCH 2/2] ARM: dts: rockchip: Set CPLL frequency for RK3588

[Alexander Shiyan]

Hello Michael.

Here is my frequency dump with a working eMMC chip.
Can you compare with your CLK values?

barebox@Diasom DS-RK3588-BTB-EVB:/ clk_dump -v cclk_emmc
xin24m (rate 24000000, enable_count: 15, enabled)
    pll_gpll (rate 1188000000, enable_count: 1, enabled)
        gpll (rate 1188000000, enable_count: 13, always enabled)
        `---- possible parents: xin24m pll_gpll xin32k
            cclk_emmc (rate 51652174, enable_count: 1, enabled)
            `---- possible parents: gpll cpll xin24m
barebox@Diasom DS-RK3588-BTB-EVB:/ clk_dump -v hclk_emmc
xin24m (rate 24000000, enable_count: 15, enabled)
    pll_gpll (rate 1188000000, enable_count: 1, enabled)
        gpll (rate 1188000000, enable_count: 13, always enabled)
        `---- possible parents: xin24m pll_gpll xin32k
            clk_200m_src (rate 198000000, enable_count: 12, enabled)
            `---- possible parents: gpll cpll
                hclk_nvm_root (rate 198000000, enable_count: 1, enabled)
                `---- possible parents: clk_200m_src clk_100m_src
clk_50m_src xin24m
                    hclk_nvm (rate 198000000, enable_count: 2, enabled)
                        hclk_emmc (rate 198000000, enable_count: 1, enabled)
barebox@Diasom DS-RK3588-BTB-EVB:/ clk_dump -v aclk_emmc
xin24m (rate 24000000, enable_count: 15, enabled)
    pll_cpll (rate 1500000000, enable_count: 1, enabled)
        cpll (rate 1500000000, enable_count: 18, always enabled)
        `---- possible parents: xin24m pll_cpll xin32k
            aclk_nvm_root (rate 300000000, enable_count: 2, enabled)
            `---- possible parents: gpll cpll
                aclk_emmc (rate 300000000, enable_count: 1, enabled)
barebox@Diasom DS-RK3588-BTB-EVB:/ clk_dump -v bclk_emmc
xin24m (rate 24000000, enable_count: 15, enabled)
    pll_cpll (rate 1500000000, enable_count: 1, enabled)
        cpll (rate 1500000000, enable_count: 18, always enabled)
        `---- possible parents: xin24m pll_cpll xin32k
            bclk_emmc (rate 187500000, enable_count: 1, enabled)
            `---- possible parents: gpll cpll
barebox@Diasom DS-RK3588-BTB-EVB:/ clk_dump -v tmclk_emmc
xin24m (rate 24000000, enable_count: 15, enabled)
    tmclk_emmc (rate 24000000, enable_count: 1, enabled)

ср, 1 окт. 2025 г. в 17:06, Michael Tretter <m.tretter@pengutronix.de>:
>
> Hi Alexander,
>
> On Mon, 29 Sep 2025 16:58:57 +0300, Alexander Shiyan wrote:
> > Explicitly configure CPLL frequency to 1500 MHz to ensure system
> > stability and reliable operation.
> > The change aligns with Rockchip's recommended practices for clock
> > configuration in embedded systems using RK3588 SoCs.
>
> This change breaks eMMC operation in barebox on ROCK 5T boards. I get
> the following alert during barebox boot:
>
>         ALERT: rk3568-dwcmshc-sdhci fe2e0000.mmc@fe2e0000.of: DMA wait timed out. Resetting, but recovery unlikely
>         WARNING: mmc0: Card's startup fails with -110
>
> I fumbled a bit with the clocks, especially the aclk_emmc, but no
> improvement so far.
>
> Michael
>
> > Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
> > ---
> >  arch/arm/dts/rk3588.dtsi | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
> > index 416700cf0e..42d692a9bd 100644
> > --- a/arch/arm/dts/rk3588.dtsi
> > +++ b/arch/arm/dts/rk3588.dtsi
> > @@ -1,6 +1,9 @@
> >  // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >
> >  / {
> > +     assigned-clocks = <&cru PLL_CPLL>;
> > +     assigned-clock-rates = <1500000000>;
> > +
> >       dmc: memory-controller {
> >               compatible = "rockchip,rk3588-dmc";
> >               rockchip,pmu = <&pmu1grf>;