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Mon, 06 Oct 2025 04:50:45 -0700 (PDT) MIME-Version: 1.0 References: <20250929135857.965181-1-eagle.alexander923@gmail.com> <20250929135857.965181-2-eagle.alexander923@gmail.com> In-Reply-To: From: Alexander Shiyan Date: Mon, 6 Oct 2025 14:50:33 +0300 X-Gm-Features: AS18NWAIvGxbV6j8_cnYgkS-Dlb749X-cDZy5FjDQS7sFoIyJtVBXK_ok9sTv8g Message-ID: To: Michael Tretter Cc: barebox@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251006_045046_981612_9E3B5B51 X-CRM114-Status: GOOD ( 17.79 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-3.8 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH 2/2] ARM: dts: rockchip: Set CPLL frequency for RK3588 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Hello Michael. Here is my frequency dump with a working eMMC chip. Can you compare with your CLK values? barebox@Diasom DS-RK3588-BTB-EVB:/ clk_dump -v cclk_emmc xin24m (rate 24000000, enable_count: 15, enabled) pll_gpll (rate 1188000000, enable_count: 1, enabled) gpll (rate 1188000000, enable_count: 13, always enabled) `---- possible parents: xin24m pll_gpll xin32k cclk_emmc (rate 51652174, enable_count: 1, enabled) `---- possible parents: gpll cpll xin24m barebox@Diasom DS-RK3588-BTB-EVB:/ clk_dump -v hclk_emmc xin24m (rate 24000000, enable_count: 15, enabled) pll_gpll (rate 1188000000, enable_count: 1, enabled) gpll (rate 1188000000, enable_count: 13, always enabled) `---- possible parents: xin24m pll_gpll xin32k clk_200m_src (rate 198000000, enable_count: 12, enabled) `---- possible parents: gpll cpll hclk_nvm_root (rate 198000000, enable_count: 1, enabled) `---- possible parents: clk_200m_src clk_100m_src clk_50m_src xin24m hclk_nvm (rate 198000000, enable_count: 2, enabled) hclk_emmc (rate 198000000, enable_count: 1, enabled= ) barebox@Diasom DS-RK3588-BTB-EVB:/ clk_dump -v aclk_emmc xin24m (rate 24000000, enable_count: 15, enabled) pll_cpll (rate 1500000000, enable_count: 1, enabled) cpll (rate 1500000000, enable_count: 18, always enabled) `---- possible parents: xin24m pll_cpll xin32k aclk_nvm_root (rate 300000000, enable_count: 2, enabled) `---- possible parents: gpll cpll aclk_emmc (rate 300000000, enable_count: 1, enabled) barebox@Diasom DS-RK3588-BTB-EVB:/ clk_dump -v bclk_emmc xin24m (rate 24000000, enable_count: 15, enabled) pll_cpll (rate 1500000000, enable_count: 1, enabled) cpll (rate 1500000000, enable_count: 18, always enabled) `---- possible parents: xin24m pll_cpll xin32k bclk_emmc (rate 187500000, enable_count: 1, enabled) `---- possible parents: gpll cpll barebox@Diasom DS-RK3588-BTB-EVB:/ clk_dump -v tmclk_emmc xin24m (rate 24000000, enable_count: 15, enabled) tmclk_emmc (rate 24000000, enable_count: 1, enabled) =D1=81=D1=80, 1 =D0=BE=D0=BA=D1=82. 2025=E2=80=AF=D0=B3. =D0=B2 17:06, Mich= ael Tretter : > > Hi Alexander, > > On Mon, 29 Sep 2025 16:58:57 +0300, Alexander Shiyan wrote: > > Explicitly configure CPLL frequency to 1500 MHz to ensure system > > stability and reliable operation. > > The change aligns with Rockchip's recommended practices for clock > > configuration in embedded systems using RK3588 SoCs. > > This change breaks eMMC operation in barebox on ROCK 5T boards. I get > the following alert during barebox boot: > > ALERT: rk3568-dwcmshc-sdhci fe2e0000.mmc@fe2e0000.of: DMA wait ti= med out. Resetting, but recovery unlikely > WARNING: mmc0: Card's startup fails with -110 > > I fumbled a bit with the clocks, especially the aclk_emmc, but no > improvement so far. > > Michael > > > Signed-off-by: Alexander Shiyan > > --- > > arch/arm/dts/rk3588.dtsi | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi > > index 416700cf0e..42d692a9bd 100644 > > --- a/arch/arm/dts/rk3588.dtsi > > +++ b/arch/arm/dts/rk3588.dtsi > > @@ -1,6 +1,9 @@ > > // SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > > > / { > > + assigned-clocks =3D <&cru PLL_CPLL>; > > + assigned-clock-rates =3D <1500000000>; > > + > > dmc: memory-controller { > > compatible =3D "rockchip,rk3588-dmc"; > > rockchip,pmu =3D <&pmu1grf>;