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From: Alexander Shiyan <eagle.alexander923@gmail.com>
To: Michael Tretter <m.tretter@pengutronix.de>
Cc: Barebox List <barebox@lists.infradead.org>
Subject: Re: RK3588 CPLL question
Date: Mon, 29 Sep 2025 16:01:29 +0300	[thread overview]
Message-ID: <CAP1tNvTr=P2r5vm5jEyXavfnLP2J3Q1t0tVB92HJ5XuoDBjkzg@mail.gmail.com> (raw)
In-Reply-To: <aNo6GD3kw4l3g_Ks@pengutronix.de>

Hello.

> On Wed, 24 Sep 2025 16:05:02 +0300, Alexander Shiyan wrote:
> > There's still no successful result with properly configuring the CPLL
> > for the RK3588.
> > Without it, kernel startup becomes pointless, as important frequencies
> > for network
> > interfaces, and likely some others, remain half the speed required for
> > system operation.
> > The CPLL in U-Boot is programmed for a frequency of 1500 MHz, and it
> > works there,
> > but in barebox these actions do not bring success.
...
> > I don't know what else to try...
> > Has anyone had any successful experience running a barebox for RK3588
> > with working network interfaces?
>
> I have barebox running with working network interfaces on a Radxa ROCK
> 5T board. I'm not familiar with the clock tree, yet, but on my system,
> the CPLL is also set to 750 MHz and child clocks seem to be running at
> half their rate.

I think REFCLKO25M_ETHx_OUT is not used there.



      reply	other threads:[~2025-09-29 13:02 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-03 13:43 Alexander Shiyan
2025-04-03 13:54 ` Sascha Hauer
2025-04-03 14:01   ` Alexander Shiyan
2025-04-03 14:08     ` Sascha Hauer
2025-04-03 14:20       ` Alexander Shiyan
2025-04-04  7:29         ` Sascha Hauer
2025-04-04  7:39           ` Alexander Shiyan
2025-04-07 12:31           ` Alexander Shiyan
2025-09-24 13:05             ` Alexander Shiyan
2025-09-29  7:49               ` Michael Tretter
2025-09-29 13:01                 ` Alexander Shiyan [this message]

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