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From: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>
To: Stefan Kerkmann <s.kerkmann@pengutronix.de>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	BAREBOX <barebox@lists.infradead.org>
Subject: RE: [PATCH 1/3] arm: mach-imx: tzasc: lock id_swap_bypass bit
Date: Mon, 26 Feb 2024 16:38:11 +0000	[thread overview]
Message-ID: <DB9PR06MB73887450E933B09F554E0FEAA65A2@DB9PR06MB7388.eurprd06.prod.outlook.com> (raw)
In-Reply-To: <20240226-v2024-02-0-topic-imx8m-n-p-tzac-v1-1-2df2430da984@pengutronix.de>


> -----Original Message-----
> From: Stefan Kerkmann <s.kerkmann@pengutronix.de>
> Sent: Monday, February 26, 2024 3:40 PM
> To: Sascha Hauer <s.hauer@pengutronix.de>; BAREBOX <barebox@lists.infradead.org>
> Cc: Stefan Kerkmann <s.kerkmann@pengutronix.de>; ZHIZHIKIN Andrey
> <andrey.zhizhikin@leica-geosystems.com>
> Subject: [PATCH 1/3] arm: mach-imx: tzasc: lock id_swap_bypass bit
> 
> 
> This commit ports U-Boot commit 1289ff7bd7e4 ("imx8m: lock
> id_swap_bypass bit in tzc380 enable") to barebox. This is the original
> commit message:
> 
> > According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock
> > bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in
> > order to avoid AXI bus errors when GPU is enabled on the platform.
> > TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable
> > derivatives, but is missing a lock settings to be applied.
> >
> > Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have
> > it implemented.
> >
> > Since we're here, provide also names to bits from TRM instead of using
> > BIT() macro in the code.
> 
> Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>

> ---
>  arch/arm/mach-imx/tzasc.c | 42 ++++++++++++++++++++++++++++++++----------
>  1 file changed, 32 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/tzasc.c b/arch/arm/mach-imx/tzasc.c
> index 9c71108c99..1f8d7426c1 100644
> --- a/arch/arm/mach-imx/tzasc.c
> +++ b/arch/arm/mach-imx/tzasc.c
> @@ -5,37 +5,59 @@
>  #include <mach/imx/imx8m-regs.h>
>  #include <io.h>
> 
> -#define GPR_TZASC_EN           BIT(0)
> -#define GPR_TZASC_SWAP_ID      BIT(1)
> -#define GPR_TZASC_EN_LOCK      BIT(16)
> +#define GPR_TZASC_EN                                   BIT(0)
> +#define GPR_TZASC_ID_SWAP_BYPASS               BIT(1)
> +#define GPR_TZASC_EN_LOCK                              BIT(16)
> +#define GPR_TZASC_ID_SWAP_BYPASS_LOCK  BIT(17)
> 
> -static void enable_tzc380(bool bypass_id_swap)
> +#define MX8M_TZASC_REGION_ATTRIBUTES_0         (MX8M_TZASC_BASE_ADDR + 0x108)
> +#define MX8M_TZASC_REGION_ATTRIBUTES_0_SP      GENMASK(31, 28)
> +
> +static void enable_tzc380(bool bypass_id_swap, bool bypass_id_swap_lock)
>  {
>         u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR);
> 
>         /* Enable TZASC and lock setting */
>         setbits_le32(&gpr[10], GPR_TZASC_EN);
>         setbits_le32(&gpr[10], GPR_TZASC_EN_LOCK);
> +
> +       /*
> +        * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
> +        * order to avoid AXI Bus errors when GPU is in use
> +        */
>         if (bypass_id_swap)
> -               setbits_le32(&gpr[10], BIT(1));
> +               setbits_le32(&gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
> +
> +       /*
> +        * imx8mn and imx8mp implements the lock bit for
> +        * TZASC_ID_SWAP_BYPASS, enable it to lock settings
> +        */
> +       if (bypass_id_swap_lock)
> +               setbits_le32(&gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
> +
>         /*
>          * set Region 0 attribute to allow secure and non-secure
>          * read/write permission. Found some masters like usb dwc3
>          * controllers can't work with secure memory.
>          */
> -       writel(0xf0000000, MX8M_TZASC_BASE_ADDR + 0x108);
> +       writel(MX8M_TZASC_REGION_ATTRIBUTES_0_SP,
> +                  MX8M_TZASC_REGION_ATTRIBUTES_0);
>  }
> 
>  void imx8mq_tzc380_init(void)
>  {
> -       enable_tzc380(false);
> +       enable_tzc380(false, false);
>  }
> 
> -void imx8mn_tzc380_init(void) __alias(imx8mm_tzc380_init);
> -void imx8mp_tzc380_init(void) __alias(imx8mm_tzc380_init);
>  void imx8mm_tzc380_init(void)
>  {
> -       enable_tzc380(true);
> +       enable_tzc380(true, false);
> +}
> +
> +void imx8mn_tzc380_init(void) __alias(imx8mp_tzc380_init);
> +void imx8mp_tzc380_init(void)
> +{
> +       enable_tzc380(true, true);
>  }
> 
>  bool tzc380_is_enabled(void)
> 
> --
> 2.39.2


  parent reply	other threads:[~2024-02-26 16:39 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-26 14:40 [PATCH 0/3] arm: mach-imx: tzasc: port " Stefan Kerkmann
2024-02-26 14:40 ` [PATCH 1/3] arm: mach-imx: tzasc: " Stefan Kerkmann
2024-02-26 16:02   ` Ahmad Fatoum
2024-02-26 16:38   ` ZHIZHIKIN Andrey [this message]
2024-02-26 14:40 ` [PATCH 2/3] arm: mach-imx: set cpu type in pbl Stefan Kerkmann
2024-02-26 16:15   ` Ahmad Fatoum
2024-02-26 14:40 ` [PATCH 3/3] arm: mach-imx: tzasc: convert to cpu_is_mx8xyz macros Stefan Kerkmann
2024-02-26 16:10   ` Ahmad Fatoum
2024-02-27  8:44   ` Sascha Hauer
2024-02-28  8:46     ` Stefan Kerkmann
2024-02-28  9:06       ` Ahmad Fatoum
2024-02-28 11:05       ` Sascha Hauer
2024-02-28 13:17         ` Stefan Kerkmann

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