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X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260702_083453_557563_FD5DBD37 X-CRM114-Status: GOOD ( 15.76 ) X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "desiato.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Hi Johannes, On 2026-06-16 14:49, Johannes Schneider wrote: > The BL32 fw-external blob is loaded into DRAM by the PBL and then > SHA-256-verified inside get_builtin_firmware_ext(). The verify runs > in PBL phase [...] Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Rspamd-Queue-Id: 7E1BB200F84 X-Spamd-Result: default: False [-4.61 / 15.00]; BAYES_HAM(-3.00)[99.99%]; MISSING_MIME_VERSION(2.00)[]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; RCVD_IN_DNSWL_MED(-0.40)[2607:7c80:54:3::133:from,2001:8b0:10b:1:d65d:64ff:fe57:4e05:received]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309]; R_SPF_ALLOW(-0.20)[+mx:c]; MAILLIST(-0.20)[mailman]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; FORGED_RECIPIENTS(0.00)[m:johannes.schneider@leica-geosystems.com,m:barebox@lists.infradead.org,s:lore@pengutronix.de]; RCVD_COUNT_THREE(0.00)[4]; DKIM_MIXED(0.00)[]; RECEIVED_HELO_LOCALHOST(0.00)[]; DMARC_NA(0.00)[saschahauer.de]; FORGED_SENDER(0.00)[sascha@saschahauer.de,barebox-bounces@lists.infradead.org]; TO_DN_SOME(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; FORWARDED(0.00)[barebox@bombadil.infradead.org]; RCVD_TLS_LAST(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; R_DKIM_REJECT(0.00)[infradead.org:s=desiato.20200630,ku-gbr.de:s=x]; NEURAL_HAM(-0.00)[-1.000]; MID_RHS_MATCH_FROM(0.00)[]; FORGED_SENDER_FORWARDING(0.00)[]; FROM_HAS_DN(0.00)[]; FROM_NEQ_ENVFROM(0.00)[sascha@saschahauer.de,barebox-bounces@lists.infradead.org]; TAGGED_FROM(0.00)[lore=pengutronix.de]; FORGED_RECIPIENTS_FORWARDING(0.00)[]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; DKIM_TRACE(0.00)[lists.infradead.org:+,infradead.org:-,ku-gbr.de:-]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCPT_COUNT_THREE(0.00)[3]; MISSING_XM_UA(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Action: no action X-Stat-Signature: czdy3q9eor5ieoaeeym4ifqsczb55qdz X-Rspamd-Server: mx1 Hi Johannes, On 2026-06-16 14:49, Johannes Schneider wrote: > The BL32 fw-external blob is loaded into DRAM by the PBL and then > SHA-256-verified inside get_builtin_firmware_ext(). The verify runs > in PBL phase 1 with the MMU off and D-cache cold, walking ~720 KiB > through uncached DRAM accesses; on a Cortex-A53 this costs around > 2 s of pre-BL31 wall-clock on every boot. >=20 > The verify is the only thing anchoring the BL32 content to the > signed PBL: HABv4 on i.MX8M only signs and loads what fits in > on-chip SRAM (=3D the PBL), and BL31/BL32 reach DRAM via PBL-driven > copies, so skipping the SHA-256 would be a security regression. >=20 > Turn on MMU + D-cache once the DRAM is populated and right before > the SHA-256 verify + BL31/BL32 memcpy run, and drop the MMU again > right before the BL31 entry (BL31 expects MMU off). Mirrors the > Rockchip handling in commits f2ae1a4a85 ("ARM: rockchip: atf: > enable MMU in PBL") and a0ef3a1b5c ("ARM: rockchip: atf: pass > correct memsize to mmu_early_enable()"). >=20 > Measured on i.MX8MM and i.MX8MP (Cortex-A53, ~720 KiB BL32 blob): > the BL32 verify drops from ~2 s to ~300 ms (generic-C SHA-256 in > both cases, the difference is the D-cache state) and the BL31 > early-init also benefits from the warm cache (~200 ms saved). >=20 > Assisted-by: Claude:claude-opus-4-7 > Signed-off-by: Johannes Schneider > --- > --- a/arch/arm/mach-imx/atf.c > +++ b/arch/arm/mach-imx/atf.c > @@ -20,6 +20,7 @@ > #include > #include > #include > +#include > =20 > static void imx_adjust_optee_memory(void **bl32, void **bl32_image, size= _t *bl32_size) > { > @@ -187,6 +188,9 @@ > "r" (tfa_dest - 16) : > "cc"); > =20 > + /* BL31 expects MMU off. */ > + mmu_disable(); > + > /* > * If enabled the bl_params are passed via x0 to the TF-A, except for > * the i.MX8MQ which doesn't support bl_params yet. > @@ -284,6 +288,12 @@ > imx8m_setup_snvs(); > imx8mm_load_bl33(bl33); > =20 > + /* Cache DRAM for the BL32 verify + BL31/BL32 memcpy that follow. */ > + mmu_early_enable(MX8M_DDR_CSD1_BASE_ADDR, > + imx8m_barebox_earlymem_size(32), > + MX8M_DDR_CSD1_BASE_ADDR + > + imx8m_barebox_earlymem_size(32) - OPTEE_SIZE); mmu_early_enable() only takes two arguments. Please add a new imx8m_mmu_early_enable() function usable for all i.MX8M to enable the MMU. We already have this snippet elsewhere: endmem =3D MX8M_DDR_CSD1_BASE_ADDR; if (cpu_is_mx8mn()) endmem +=3D imx8m_barebox_earlymem_size(16); else endmem +=3D imx8m_barebox_earlymem_size(32); Which could help implementing this function. Sascha