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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8459.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d606f0b4-a715-48d8-dd2d-08dce11a88bb X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2024 06:38:45.8640 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: iy3zTUFskHoH2l+VfJlVPS/uhg+ENS0B2wEsCDi+5pXI3KGHRXxmTq5C08X3DHnDWbr07I18iD8nE/p6T3RnBg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB8289 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240929_233859_544715_549FCD96 X-CRM114-Status: GOOD ( 16.55 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.8 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: RE: i.MX8/9: question about unused DDR PHY trained CSR board array X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Hi Ahmad, > Subject: i.MX8/9: question about unused DDR PHY trained CSR board > array >=20 > Hello Peng, >=20 > Looking at the DDR setup code for i.MX8M and i.MX9 that you had > contributed, I am wondering about struct > dram_cfg_param::ddrphy_trained_csr and the global > ddrphy_trained_csr array. >=20 > struct dram_cfg_param::ddrphy_trained_csr is presumably generated > by the i.MX DDR tool and it seems populated by all the i.MX8M/9 > boards in U-Boot. >=20 > This struct member is wholly unused though and instead a global > ddrphy_trained_csr is used. >=20 > What I wonder about is whether it's possible for the DDR tool to > generate a different ddrphy_trained_csr than the default: >=20 > 1) If yes, we should drop the global ddrphy_trained_csr and actually > use > the board-specific array >=20 > 2) If not, we should drop the board-specific array and perhaps ask for > the DDR tool to be changed >=20 > I initially assumed 1) and because all boards supported by barebox had > a board-specific ddrphy_trained_csr that's identical to the global > ddrphy_trained_csr, I dropped the unused array[1][2]. >=20 > I now have the DDR settings for an i.MX9 LPDDR4 board in front of me > that has different contents for struct > dram_cfg_param::ddrphy_trained_csr than the default. >=20 > I will inquire how that came about, but in parallel I wanted to ask you i= f > this is supposed to happen and to alert you to this issue. Thanks for raising this issue. I think board specific csr should be used. I will check with DDR TOOL owners on this. >=20 > The way things are, this is either a bug or a missed space saving > opportunity for U-Boot. Thanks, Peng.