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From: John Watts To: Sascha Hauer Cc: barebox@lists.infradead.org Message-ID: References: <20230126185643.104049-1-contact@jookia.org> <20230130102727.GQ13319@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230130102727.GQ13319@pengutronix.de> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230130_024322_645604_7C38A623 X-CRM114-Status: GOOD ( 15.29 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH] I2C: i.MX: early: Use internal udelay X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) On Mon, Jan 30, 2023 at 11:27:27AM +0100, Sascha Hauer wrote: > This takes around 5 times too long on a i.MX8MM and around 50 times too > long on a i.MX6Q. This was measured under a regular barebox on the > shell. In an early environment with MMU disabled it takes 730 times too > long. Yikes! I'm glad I broke this in to its own patch then. :) I did copy this code from these boards: arch/arm/boards/cm-fx6/lowlevel.c arch/arm/boards/skov-imx6/lowlevel.c arch/arm/boards/technexion-wandboard/lowlevel.c arch/arm/mach-imx/xload-gpmi-nand.c arch/arm/mach-imx/imx6-mmdc.c (uses 1000 loops) Maybe it's time for an i.MX6-wide early udelay? Though this code might break if its timing is already wrong. > Maybe we could do this: > > static void __udelay(void *base, int us) > { > int i; > > for (i = 0; i < us * 4; i++) > readb(base); > } > > The time spent for a register read depends on the bus clock which > doesn't change that much between the different SoCs. This seems like a better solution if you've tested it, I'm not too sure how to check this. Would I just then specify the controller as the base? Though the actual goal of the code is to wait for the controller to bestable. Maybe there's a better way than a delay? > > Sascha John.