* RK3588 CPLL question @ 2025-04-03 13:43 Alexander Shiyan 2025-04-03 13:54 ` Sascha Hauer 0 siblings, 1 reply; 7+ messages in thread From: Alexander Shiyan @ 2025-04-03 13:43 UTC (permalink / raw) To: Barebox List Hello All. Who has a board equipped with a RK3588 CPU? I need to check the cpll frequency. Now on my system (by clk_dump) this is 750 MHz, although it should be 1.5 GHz, otherwise all other frequencies are divided by 2, which is critical for network interfaces, for example... Can anyone test this? Thanks! ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: RK3588 CPLL question 2025-04-03 13:43 RK3588 CPLL question Alexander Shiyan @ 2025-04-03 13:54 ` Sascha Hauer 2025-04-03 14:01 ` Alexander Shiyan 0 siblings, 1 reply; 7+ messages in thread From: Sascha Hauer @ 2025-04-03 13:54 UTC (permalink / raw) To: Alexander Shiyan; +Cc: Barebox List Hi Alexander, On Thu, Apr 03, 2025 at 04:43:19PM +0300, Alexander Shiyan wrote: > Hello All. > > Who has a board equipped with a RK3588 CPU? > I need to check the cpll frequency. Now on my system (by clk_dump) > this is 750 MHz, > although it should be 1.5 GHz, otherwise all other frequencies are divided by 2, > which is critical for network interfaces, for example... > Can anyone test this? It shows 750MHz on my board as well. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: RK3588 CPLL question 2025-04-03 13:54 ` Sascha Hauer @ 2025-04-03 14:01 ` Alexander Shiyan 2025-04-03 14:08 ` Sascha Hauer 0 siblings, 1 reply; 7+ messages in thread From: Alexander Shiyan @ 2025-04-03 14:01 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List Thanks Sascha! So something is wrong here. At least the GMAC0/1 interfaces end up with the wrong frequency. I have another image with u-boot and Rockchip kernel where CPLL is 1.5GHz and network is ok. At this time I have not an idea... чт, 3 апр. 2025 г. в 16:54, Sascha Hauer <s.hauer@pengutronix.de>: > > Hi Alexander, > > On Thu, Apr 03, 2025 at 04:43:19PM +0300, Alexander Shiyan wrote: > > Hello All. > > > > Who has a board equipped with a RK3588 CPU? > > I need to check the cpll frequency. Now on my system (by clk_dump) > > this is 750 MHz, > > although it should be 1.5 GHz, otherwise all other frequencies are divided by 2, > > which is critical for network interfaces, for example... > > Can anyone test this? > > It shows 750MHz on my board as well. > > Sascha > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: RK3588 CPLL question 2025-04-03 14:01 ` Alexander Shiyan @ 2025-04-03 14:08 ` Sascha Hauer 2025-04-03 14:20 ` Alexander Shiyan 0 siblings, 1 reply; 7+ messages in thread From: Sascha Hauer @ 2025-04-03 14:08 UTC (permalink / raw) To: Alexander Shiyan; +Cc: Barebox List On Thu, Apr 03, 2025 at 05:01:05PM +0300, Alexander Shiyan wrote: > Thanks Sascha! > > So something is wrong here. > At least the GMAC0/1 interfaces end up with the wrong frequency. > I have another image with u-boot and Rockchip kernel where CPLL > is 1.5GHz and network is ok. The only place where the PLL rates are configured in barebox is via assigned-clock-rates in the clock controller node. PLL_CPLL doesn't show up there, so I would assume it is just left to the default whatever that is. You could chainload barebox from U-Boot and see what the CPLL rate is then. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: RK3588 CPLL question 2025-04-03 14:08 ` Sascha Hauer @ 2025-04-03 14:20 ` Alexander Shiyan 2025-04-04 7:29 ` Sascha Hauer 0 siblings, 1 reply; 7+ messages in thread From: Alexander Shiyan @ 2025-04-03 14:20 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List I found this hack: https://github.com/u-boot/u-boot/blob/master/drivers/clk/rockchip/clk_rk3588.c#L1933 чт, 3 апр. 2025 г. в 17:08, Sascha Hauer <s.hauer@pengutronix.de>: > > On Thu, Apr 03, 2025 at 05:01:05PM +0300, Alexander Shiyan wrote: > > Thanks Sascha! > > > > So something is wrong here. > > At least the GMAC0/1 interfaces end up with the wrong frequency. > > I have another image with u-boot and Rockchip kernel where CPLL > > is 1.5GHz and network is ok. > > The only place where the PLL rates are configured in barebox is via > assigned-clock-rates in the clock controller node. PLL_CPLL doesn't show > up there, so I would assume it is just left to the default whatever that > is. > > You could chainload barebox from U-Boot and see what the CPLL rate is > then. > > Sascha > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: RK3588 CPLL question 2025-04-03 14:20 ` Alexander Shiyan @ 2025-04-04 7:29 ` Sascha Hauer 2025-04-04 7:39 ` Alexander Shiyan 0 siblings, 1 reply; 7+ messages in thread From: Sascha Hauer @ 2025-04-04 7:29 UTC (permalink / raw) To: Alexander Shiyan; +Cc: Barebox List On Thu, Apr 03, 2025 at 05:20:33PM +0300, Alexander Shiyan wrote: > I found this hack: > https://github.com/u-boot/u-boot/blob/master/drivers/clk/rockchip/clk_rk3588.c#L1933 Let's do the same then. It would be nicer to have the CPLL setting in the assigned-clock-rates property. That should be done in the upstream dtsi though, overwriting the assigned-clock-rates in the barebox dtsi would mean we would have to copy the many existing settings and hope they don't change upstream. Sascha > > чт, 3 апр. 2025 г. в 17:08, Sascha Hauer <s.hauer@pengutronix.de>: > > > > On Thu, Apr 03, 2025 at 05:01:05PM +0300, Alexander Shiyan wrote: > > > Thanks Sascha! > > > > > > So something is wrong here. > > > At least the GMAC0/1 interfaces end up with the wrong frequency. > > > I have another image with u-boot and Rockchip kernel where CPLL > > > is 1.5GHz and network is ok. > > > > The only place where the PLL rates are configured in barebox is via > > assigned-clock-rates in the clock controller node. PLL_CPLL doesn't show > > up there, so I would assume it is just left to the default whatever that > > is. > > > > You could chainload barebox from U-Boot and see what the CPLL rate is > > then. > > > > Sascha > > > > -- > > Pengutronix e.K. | | > > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: RK3588 CPLL question 2025-04-04 7:29 ` Sascha Hauer @ 2025-04-04 7:39 ` Alexander Shiyan 0 siblings, 0 replies; 7+ messages in thread From: Alexander Shiyan @ 2025-04-04 7:39 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List Hello. Yes, this is the best option, but it is not possible yet. Any change in CPLL frequency causes the system to freeze. I am still trying to figure this out. Thanks! пт, 4 апр. 2025 г. в 10:29, Sascha Hauer <s.hauer@pengutronix.de>: > > On Thu, Apr 03, 2025 at 05:20:33PM +0300, Alexander Shiyan wrote: > > I found this hack: > > https://github.com/u-boot/u-boot/blob/master/drivers/clk/rockchip/clk_rk3588.c#L1933 > > Let's do the same then. > > It would be nicer to have the CPLL setting in the assigned-clock-rates > property. That should be done in the upstream dtsi though, overwriting > the assigned-clock-rates in the barebox dtsi would mean we would have to > copy the many existing settings and hope they don't change upstream. > > Sascha > > > > > чт, 3 апр. 2025 г. в 17:08, Sascha Hauer <s.hauer@pengutronix.de>: > > > > > > On Thu, Apr 03, 2025 at 05:01:05PM +0300, Alexander Shiyan wrote: > > > > Thanks Sascha! > > > > > > > > So something is wrong here. > > > > At least the GMAC0/1 interfaces end up with the wrong frequency. > > > > I have another image with u-boot and Rockchip kernel where CPLL > > > > is 1.5GHz and network is ok. > > > > > > The only place where the PLL rates are configured in barebox is via > > > assigned-clock-rates in the clock controller node. PLL_CPLL doesn't show > > > up there, so I would assume it is just left to the default whatever that > > > is. > > > > > > You could chainload barebox from U-Boot and see what the CPLL rate is > > > then. > > > > > > Sascha > > > > > > -- > > > Pengutronix e.K. | | > > > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > > > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > > > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > > > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-04-04 7:40 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2025-04-03 13:43 RK3588 CPLL question Alexander Shiyan 2025-04-03 13:54 ` Sascha Hauer 2025-04-03 14:01 ` Alexander Shiyan 2025-04-03 14:08 ` Sascha Hauer 2025-04-03 14:20 ` Alexander Shiyan 2025-04-04 7:29 ` Sascha Hauer 2025-04-04 7:39 ` Alexander Shiyan
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