From: Sascha Hauer <s.hauer@pengutronix.de>
To: Alexander Shiyan <eagle.alexander923@gmail.com>
Cc: Barebox List <barebox@lists.infradead.org>
Subject: Re: RK3588 CPLL question
Date: Thu, 3 Apr 2025 16:08:44 +0200 [thread overview]
Message-ID: <Z-6WbLbIkVS_wvLj@pengutronix.de> (raw)
In-Reply-To: <CAP1tNvR6mxe8gMSb05U20GdGqaO4N9zq-7so74+fm0DJ0iopVA@mail.gmail.com>
On Thu, Apr 03, 2025 at 05:01:05PM +0300, Alexander Shiyan wrote:
> Thanks Sascha!
>
> So something is wrong here.
> At least the GMAC0/1 interfaces end up with the wrong frequency.
> I have another image with u-boot and Rockchip kernel where CPLL
> is 1.5GHz and network is ok.
The only place where the PLL rates are configured in barebox is via
assigned-clock-rates in the clock controller node. PLL_CPLL doesn't show
up there, so I would assume it is just left to the default whatever that
is.
You could chainload barebox from U-Boot and see what the CPLL rate is
then.
Sascha
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next prev parent reply other threads:[~2025-04-03 14:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-03 13:43 Alexander Shiyan
2025-04-03 13:54 ` Sascha Hauer
2025-04-03 14:01 ` Alexander Shiyan
2025-04-03 14:08 ` Sascha Hauer [this message]
2025-04-03 14:20 ` Alexander Shiyan
2025-04-04 7:29 ` Sascha Hauer
2025-04-04 7:39 ` Alexander Shiyan
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