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Fri, 10 Jan 2025 16:16:38 +0100 (CET) Date: Fri, 10 Jan 2025 16:16:33 +0100 From: Konstantin Kletschke To: Lucas Stach Message-ID: References: <9c00ffd1332ba38dffc26b0b8967f8327d72e4a0.camel@lynxeye.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <9c00ffd1332ba38dffc26b0b8967f8327d72e4a0.camel@lynxeye.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250110_151753_906758_B257233C X-CRM114-Status: GOOD ( 13.24 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: barebox@lists.infradead.org Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-3.9 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,RCVD_IN_SBL_CSS,SPF_HELO_NONE, SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: =?iso-8859-1?B?W1BBVENIXaBBUk0=?= =?iso-8859-1?Q?=3A?= beaglebone: add delay in lowlevel.c X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Hi Lucas, this is an interesting idea and I did poke around a bit. On Wed, Jan 08, 2025 at 04:46:22PM +0100, Lucas Stach wrote: > It would be interesting to know if any of the configured PLLs go out of > lock again during the time your delay loop runs. I.e. check if any of > CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_PER or > CM_IDLEST_DPLL_MPU contain a value other than 0x1. I inserted this into the delay loop: static void __udelay(int us) { volatile int i; for (i = 0; i < us; i++) { (__raw_readl(CM_IDLEST_DPLL_MPU) != 0x1) ? putc_ll('m') : (void)0; (__raw_readl(CM_IDLEST_DPLL_CORE) != 0x1) ? putc_ll('c') : (void)0; (__raw_readl(CM_IDLEST_DPLL_PER) != 0x1) ? putc_ll('p') : (void)0; (__raw_readl(CM_IDLEST_DPLL_DDR) != 0x1) ? putc_ll('d') : (void)0; } } but none was triggered. Additionaly I tried this instead of the above before entering the delay loop in beaglebone_sram_init(void): while(__raw_readl(CM_IDLEST_DPLL_DDR) != 0x0); //while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x0); //while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x0); //while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x0); __udelay(3000); When I suspect the bit being stable I expect to be being trapped so I booted with a version without this, replaced it with the trap and rebooted, I did this 4 times for each DDR, CORE, PER and MPU. If the bit toggles back to zero I would exit the while, delay and boot normal. So if trapped == no bit toggle. Either the putc_ll inserted into the loop did not appear nor the while trap was left in any case so I suspect this bit is stable at 0x1 for each type of PLL. Kind Regards Konsti -- INSIDE M2M GmbH Konstantin Kletschke Berenbosteler Straße 76 B 30823 Garbsen Telefon: +49 (0) 5137 90950136 Mobil: +49 (0) 151 15256238 Fax: +49 (0) 5137 9095010 konstantin.kletschke@inside-m2m.de http://www.inside-m2m.de Geschäftsführung: Michael Emmert, Derek Uhlig HRB: 111204, AG Hannover