Barebox for Zedboard

Barebox for Zedboard

[Michael Graichen]

Hey,

i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC.
I have seen that Barebox has an defconfig for the zynq
so i tried

export ARCH=arm
export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf-
export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH
make zynq_defconfig
make -j`nproc`

which compiles me the image

barebox-flash-image -> images/barebox-avnet-zedboard.img

when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool

dev$ bootgen -image bootimage.bif -o i BOOT.bin

and .bif file was

dev$ cat bootimage.bif
//arch = zynq; split = false; format = BIN
the_ROM_image:
{
     [bootloader]FSBL.elf
     design_1_wrapper.bit
     u-boot.elf
}


that i copied onto an SD-Card and powed up the board. 

But since i want to use Barebox how do i produce the BOOT.bin file? 
and how is the programming of the FPGA Logic done?

Best Regards 
Michael


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Re: Barebox for Zedboard

[Lucas Stach]

Hi Michael,

Am Donnerstag, den 19.03.2020, 10:38 +0000 schrieb Michael Graichen:
> Hey,
> 
> i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC.
> I have seen that Barebox has an defconfig for the zynq
> so i tried
> 
> export ARCH=arm
> export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf-
> export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH
> make zynq_defconfig
> make -j`nproc`
> 
> which compiles me the image
> 
> barebox-flash-image -> images/barebox-avnet-zedboard.img
> 
> when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool
> 
> dev$ bootgen -image bootimage.bif -o i BOOT.bin
> 
> and .bif file was
> 
> dev$ cat bootimage.bif
> //arch = zynq; split = false; format = BIN
> the_ROM_image:
> {
>      [bootloader]FSBL.elf
>      design_1_wrapper.bit
>      u-boot.elf
> }
> 
> 
> that i copied onto an SD-Card and powed up the board. 
> 
> But since i want to use Barebox how do i produce the BOOT.bin file? 

The barebox-avnet-zedboard.img already is the BOOT.bin image, just copy
it to the SD card with this name and you are done.

> and how is the programming of the FPGA Logic done?

Barebox currently doesn't support loading the FPGA bitstream. We are
still lacking a driver for the DevC PCAP interface. Zynq support in
Barebox is only a spare time (and thus toy) project at this time. It
works okay for booting Linux on the PS part of the system, but almost
fully lacks support for the PL part.

That said I wouldn't mind helping with getting the missing bits added
by reviewing/testing patches. :)

Regards,
Lucas


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AW: Barebox for Zedboard

[Michael Graichen]

________________________________________
Von: Lucas Stach <l.stach@pengutronix.de>
Gesendet: Donnerstag, 19. März 2020 11:53
An: Michael Graichen; barebox@lists.infradead.org
Betreff: Re: Barebox for Zedboard

Hi Michael,

Am Donnerstag, den 19.03.2020, 10:38 +0000 schrieb Michael Graichen:
> Hey,
>
> i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC.
> I have seen that Barebox has an defconfig for the zynq
> so i tried
>
> export ARCH=arm
> export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf-
> export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH
> make zynq_defconfig
> make -j`nproc`
>
> which compiles me the image
>
> barebox-flash-image -> images/barebox-avnet-zedboard.img
>
> when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool
>
> dev$ bootgen -image bootimage.bif -o i BOOT.bin
>
> and .bif file was
>
> dev$ cat bootimage.bif
> //arch = zynq; split = false; format = BIN
> the_ROM_image:
> {
>      [bootloader]FSBL.elf
>      design_1_wrapper.bit
>      u-boot.elf
> }
>
>
> that i copied onto an SD-Card and powed up the board.
>
> But since i want to use Barebox how do i produce the BOOT.bin file?

The barebox-avnet-zedboard.img already is the BOOT.bin image, just copy
it to the SD card with this name and you are done.

> and how is the programming of the FPGA Logic done?

Barebox currently doesn't support loading the FPGA bitstream. We are
still lacking a driver for the DevC PCAP interface. Zynq support in
Barebox is only a spare time (and thus toy) project at this time. It
works okay for booting Linux on the PS part of the system, but almost
fully lacks support for the PL part.

That said I wouldn't mind helping with getting the missing bits added
by reviewing/testing patches. :)

Regards,
Lucas

Hey Lucas,

thanks for your reply.

for some reason i had to comment out everything that is in arch/arm/boards/avnet-zedboard/zedboard.zynqcfg besides the last line

wm 32 0xffffffff 0x00000000

to get a working Bootloader.

https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf tells me that these values are suposed to be set by the BootROM and 0xffffffff signals the end of the list but unfortunatly the boot process hangs here when the unlock value is written. So i decided to leave this list empty.

Has anybody seen a similar behaviour?

Best regards
Michael
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AW: Barebox for Zedboard

[Michael Graichen]

________________________________________
Von: Lucas Stach <l.stach@pengutronix.de>
Gesendet: Donnerstag, 19. März 2020 11:53
An: Michael Graichen; barebox@lists.infradead.org
Betreff: Re: Barebox for Zedboard

Hi Michael,

Am Donnerstag, den 19.03.2020, 10:38 +0000 schrieb Michael Graichen:
> Hey,
>
> i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC.
> I have seen that Barebox has an defconfig for the zynq
> so i tried
>
> export ARCH=arm
> export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf-
> export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH
> make zynq_defconfig
> make -j`nproc`
>
> which compiles me the image
>
> barebox-flash-image -> images/barebox-avnet-zedboard.img
>
> when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool
>
> dev$ bootgen -image bootimage.bif -o i BOOT.bin
>
> and .bif file was
>
> dev$ cat bootimage.bif
> //arch = zynq; split = false; format = BIN
> the_ROM_image:
> {
>      [bootloader]FSBL.elf
>      design_1_wrapper.bit
>      u-boot.elf
> }
>
>
> that i copied onto an SD-Card and powed up the board.
>
> But since i want to use Barebox how do i produce the BOOT.bin file?

The barebox-avnet-zedboard.img already is the BOOT.bin image, just copy
it to the SD card with this name and you are done.

> and how is the programming of the FPGA Logic done?

Barebox currently doesn't support loading the FPGA bitstream. We are
still lacking a driver for the DevC PCAP interface. Zynq support in
Barebox is only a spare time (and thus toy) project at this time. It
works okay for booting Linux on the PS part of the system, but almost
fully lacks support for the PL part.

That said I wouldn't mind helping with getting the missing bits added
by reviewing/testing patches. :)

Regards,
Lucas

Hey Lucas, 

"That said I wouldn't mind helping with getting the missing bits added
by reviewing/testing patches. :)"

Did you made any attempts to do this?

As far as I can see there are basicly two ways.  
The "Xilinx-Way" by packing everything in Boot.bin.
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841976/Prepare+boot+image
and the "Linux-Way"
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager
using the FPGA manager 
https://elixir.bootlin.com/linux/latest/source/drivers/fpga/zynq-fpga.c

Best regards
Michael


 





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Re: Barebox for Zedboard

[Johannes Roith]

Am Mon, Mar 23, 2020 at 03:18:22PM +0000 schrieb Michael Graichen:
Hi Michael, hi Lucas,
> 
> ________________________________________
> Von: Lucas Stach <l.stach@pengutronix.de>
> Gesendet: Donnerstag, 19. März 2020 11:53
> An: Michael Graichen; barebox@lists.infradead.org
> Betreff: Re: Barebox for Zedboard
> 
> Hi Michael,
> 
> Am Donnerstag, den 19.03.2020, 10:38 +0000 schrieb Michael Graichen:
> > Hey,
> >
> > i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC.
> > I have seen that Barebox has an defconfig for the zynq
> > so i tried
> >
> > export ARCH=arm
> > export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf-
> > export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH
> > make zynq_defconfig
> > make -j`nproc`
> >
> > which compiles me the image
> >
> > barebox-flash-image -> images/barebox-avnet-zedboard.img
> >
> > when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool
> >
> > dev$ bootgen -image bootimage.bif -o i BOOT.bin
> >
> > and .bif file was
> >
> > dev$ cat bootimage.bif
> > //arch = zynq; split = false; format = BIN
> > the_ROM_image:
> > {
> >      [bootloader]FSBL.elf
> >      design_1_wrapper.bit
> >      u-boot.elf
> > }
> >
> >
> > that i copied onto an SD-Card and powed up the board.
> >
> > But since i want to use Barebox how do i produce the BOOT.bin file?
> 
> The barebox-avnet-zedboard.img already is the BOOT.bin image, just copy
> it to the SD card with this name and you are done.
> 
> > and how is the programming of the FPGA Logic done?

Michael, did you implement something here? In the latest barebox version
I can't find anything related to FPGA loading. But if you have developed
something and you could share it, it would be interesting for me and 
highly appreciated.

> 
> Barebox currently doesn't support loading the FPGA bitstream. We are
> still lacking a driver for the DevC PCAP interface. Zynq support in
> Barebox is only a spare time (and thus toy) project at this time. It
> works okay for booting Linux on the PS part of the system, but almost
> fully lacks support for the PL part.

I would like to try bringing PL support to barebox, but I need a bit of
guidance. In the Linux kernel there are drivers available for the ZYNQ
FPGA and there is the FPGA manager. As barebox "reuses" Linux drivers
maybe that would be the way to go.

I would love to have one barebox command available to load a bitstream
to the PL. For doing so I would need to implement a fpgamgr-lib where I
provide the interfaces used by the Linux FPGA drivers. The drivers also
need to be modified a bit. Then finally I can implement the command.

Am I missing something? Do you have any advice or sample code I could
take a look at or use for orientation? Any comments are welcome.

The big advantage of using such an approach would be support for similar
devices (e.g. the UltraScale+ ZYNQMP devices) could be added easily by
porting the Linux drivers to barebox.

> 
> That said I wouldn't mind helping with getting the missing bits added
> by reviewing/testing patches. :)
> 
> Regards,
> Lucas
> 
> Hey Lucas, 
> 
> "That said I wouldn't mind helping with getting the missing bits added
> by reviewing/testing patches. :)"
> 
> Did you made any attempts to do this?
> 
> As far as I can see there are basicly two ways.  
> The "Xilinx-Way" by packing everything in Boot.bin.
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841976/Prepare+boot+image
> and the "Linux-Way"
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager
> using the FPGA manager 
> https://elixir.bootlin.com/linux/latest/source/drivers/fpga/zynq-fpga.c
> 
> Best regards
> Michael
> 
> 
>  
> 
> 
> 
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

Best regards,
Johannes

Re: Barebox for Zedboard

[Ahmad Fatoum]

Hello Johannes,

On 16.05.25 21:03, Johannes Roith wrote:
> The big advantage of using such an approach would be support for similar
> devices (e.g. the UltraScale+ ZYNQMP devices) could be added easily by
> porting the Linux drivers to barebox.

I can't comment on the Zynq, but for ZynqMP, there is already a FPGA manager
driver in drivers/firmware/zynqmp-fpga.c. FPGA programming is also supported
for Altera SoCFPGA and are exposed over the firmware API.

Loading OF overlays can already load firmware that way.

Cheers,
Ahmad

>> That said I wouldn't mind helping with getting the missing bits added
>> by reviewing/testing patches. :)
>>
>> Regards,
>> Lucas
>>
>> Hey Lucas, 
>>
>> "That said I wouldn't mind helping with getting the missing bits added
>> by reviewing/testing patches. :)"
>>
>> Did you made any attempts to do this?
>>
>> As far as I can see there are basicly two ways.  
>> The "Xilinx-Way" by packing everything in Boot.bin.
>> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841976/Prepare+boot+image
>> and the "Linux-Way"
>> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager
>> using the FPGA manager 
>> https://elixir.bootlin.com/linux/latest/source/drivers/fpga/zynq-fpga.c
>>
>> Best regards
>> Michael
>>
>>
>>  
>>
>>
>>
>>
>>
>> _______________________________________________
>> barebox mailing list
>> barebox@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/barebox
> 
> Best regards,
> Johannes
> 
> 


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: Barebox for Zedboard

[Johannes Roith]

Hello Ahmad,

Am Fri, May 16, 2025 at 09:28:03PM +0200 schrieb Ahmad Fatoum:
> Hello Johannes,
> 
> On 16.05.25 21:03, Johannes Roith wrote:
> > The big advantage of using such an approach would be support for similar
> > devices (e.g. the UltraScale+ ZYNQMP devices) could be added easily by
> > porting the Linux drivers to barebox.
> 
> I can't comment on the Zynq, but for ZynqMP, there is already a FPGA manager
> driver in drivers/firmware/zynqmp-fpga.c. FPGA programming is also supported
> for Altera SoCFPGA and are exposed over the firmware API.

That's exactly what I was looking for. For the ZYNQ it is not
implemented yet, but I could use the ZYNQMP as a reference. I also saw
there is the firmwareload command available to load the bitstream from
commandline

> 
> Loading OF overlays can already load firmware that way.

Could you give me an example for an OF overlay to load a firmware? Do I
have to place the firmware at a specific path like with Linux FPGA
manager or can I specify the path in the overlay?

Thanks and best regards,
Johannes

> 
> Cheers,
> Ahmad
> 
> >> That said I wouldn't mind helping with getting the missing bits added
> >> by reviewing/testing patches. :)
> >>
> >> Regards,
> >> Lucas
> >>
> >> Hey Lucas, 
> >>
> >> "That said I wouldn't mind helping with getting the missing bits added
> >> by reviewing/testing patches. :)"
> >>
> >> Did you made any attempts to do this?
> >>
> >> As far as I can see there are basicly two ways.  
> >> The "Xilinx-Way" by packing everything in Boot.bin.
> >> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841976/Prepare+boot+image
> >> and the "Linux-Way"
> >> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager
> >> using the FPGA manager 
> >> https://elixir.bootlin.com/linux/latest/source/drivers/fpga/zynq-fpga.c
> >>
> >> Best regards
> >> Michael
> >>
> >>
> >>  
> >>
> >>
> >>
> >>
> >>
> >> _______________________________________________
> >> barebox mailing list
> >> barebox@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/barebox
> > 
> > Best regards,
> > Johannes
> > 
> > 
> 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: Barebox for Zedboard

[Ahmad Fatoum]

Hi,

Cc'ing Michael, who had implemented that feature.

On 18.05.25 19:06, Johannes Roith wrote:
> Am Fri, May 16, 2025 at 09:28:03PM +0200 schrieb Ahmad Fatoum:
>> Loading OF overlays can already load firmware that way.
> 
> Could you give me an example for an OF overlay to load a firmware?

Should look the same as in Linux (with overlay patches applied).

Michael, do you happen to have an example to share?

> Do I
> have to place the firmware at a specific path like with Linux FPGA
> manager or can I specify the path in the overlay?

Relative file paths are looked up according to $global.firmware.path,
which is initialized to /env/firmware by default.

You can add extra paths there and if you are using bootloader spec,
/lib/firmware on the partition containing the entries is temporarily
prepended to the search path.

The symbols in question are firmware_(set|get)_searchpath.

Cheers,
Ahmad

> 
> Thanks and best regards,
> Johannes
> 
>>
>> Cheers,
>> Ahmad
>>
>>>> That said I wouldn't mind helping with getting the missing bits added
>>>> by reviewing/testing patches. :)
>>>>
>>>> Regards,
>>>> Lucas
>>>>
>>>> Hey Lucas, 
>>>>
>>>> "That said I wouldn't mind helping with getting the missing bits added
>>>> by reviewing/testing patches. :)"
>>>>
>>>> Did you made any attempts to do this?
>>>>
>>>> As far as I can see there are basicly two ways.  
>>>> The "Xilinx-Way" by packing everything in Boot.bin.
>>>> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841976/Prepare+boot+image
>>>> and the "Linux-Way"
>>>> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager
>>>> using the FPGA manager 
>>>> https://elixir.bootlin.com/linux/latest/source/drivers/fpga/zynq-fpga.c
>>>>
>>>> Best regards
>>>> Michael
>>>>
>>>>
>>>>  
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> _______________________________________________
>>>> barebox mailing list
>>>> barebox@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/barebox
>>>
>>> Best regards,
>>> Johannes
>>>
>>>
>>
>>
>> -- 
>> Pengutronix e.K.                           |                             |
>> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
>> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
>> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

AW: Barebox for Zedboard

[Michael Graichen]

> Von: barebox <barebox-bounces@lists.infradead.org> im Auftrag von Johannes Roith <johannes@gnu-linux.rocks>
> Gesendet: Sonntag, 18. Mai 2025 19:06
> An: Ahmad Fatoum
> Cc: barebox@lists.infradead.org
> Betreff: Re: Barebox for Zedboard
>
> Hello Ahmad,
>
> Am Fri, May 16, 2025 at 09:28:03PM +0200 schrieb Ahmad Fatoum:
> > Hello Johannes,
> >
> > On 16.05.25 21:03, Johannes Roith wrote:
> > > The big advantage of using such an approach would be support for similar
> > devices (e.g. the UltraScale+ ZYNQMP devices) could be added easily by
> > porting the Linux drivers to barebox.
> >
> > I can't comment on the Zynq, but for ZynqMP, there is already a FPGA manager
> > driver in drivers/firmware/zynqmp-fpga.c. FPGA programming is also supported
> > for Altera SoCFPGA and are exposed over the firmware API.
> 
> That's exactly what I was looking for. For the ZYNQ it is not
> implemented yet, but I could use the ZYNQMP as a reference. I also saw
> there is the firmwareload command available to load the bitstream from
> commandline
> 
> >
> > Loading OF overlays can already load firmware that way.
> 
> Could you give me an example for an OF overlay to load a firmware? Do I
> have to place the firmware at a specific path like with Linux FPGA
> manager or can I specify the path in the overlay?
> 
> Thanks and best regards,
> Johannes


Dear Johannes et al.

i'am using

	amba_pl: amba_pl {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges ;
		zynq_layer_axi_dma_0: dma@40400000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_s2mm_aclk";
			clocks = <&clkc 15>, <&clkc 15>, <&clkc 17>;
			compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a";
			interrupt-names = "s2mm_introut";
			interrupt-parent = <&intc>;
			interrupts = <0 29 4>;
			reg = <0x40400000 0x10000>;
			xlnx,addrwidth = <0x20>;
			xlnx,include-sg;
			xlnx,sg-length-width = <0x10>;
			dma-channel@40400030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x1>;
				interrupts = <0 29 4>;
				xlnx,datawidth = <0x40>;
				xlnx,device-id = <0x0>;
				xlnx,include-dre ;
			};
		};
	};

	smartcam-v4l2@43C00000 {
		compatible = "wipo,smartcam-v4l2-1.0";
		interrupt-names = "smartcam-v4l2-interrupt";
		interrupt-parent = <&intc>;
		interrupts = <0 30 4>;
		reg = <0x43C00000 0x1000>;
		dmas = <&zynq_layer_axi_dma_0 1>;
		dma-names = "axidma1";
		headboard-power-gpios = <&gpio0 46 1>;
		status = "okay";
	};

for a PS<->PL DMA channel and 

	messagechannel@43C10000 {
		compatible = "wipo,messagechannel-1.0";
		interrupt-names = "messagechannel-interrupt";
		interrupt-parent = <&intc>;
		interrupts = <0 31 4>;
		reg = <0x43C10000 0x1000>;
		status = "okay";
	};

for an PS<->PL FIFO.
But this is not used within barebox in my case. It's only there because barebox passes it's devicetree to the Linux Kernel. I only do the programming of the FPGA in barebox within my init script by

firmwareload -t zynq-fpga-manager /mnt/boot/design_1_wrapper.bit

I will send the latest version of my zynq-fpga-manager to the mailing list soon. 
Please feel free to pick it up and finish my work since i did not do it since 2020.

Best Regards, 
Michael






> >
> > Cheers,
> > Ahmad
> >
> > >> That said I wouldn't mind helping with getting the missing bits added
> > >> by reviewing/testing patches. :)
> > >>
> > >> Regards,
> >> Lucas
> >>
> >> Hey Lucas,
> >>
> >> "That said I wouldn't mind helping with getting the missing bits added
> >> by reviewing/testing patches. :)"
> >>
> >> Did you made any attempts to do this?
> >>
> >> As far as I can see there are basicly two ways.
> >> The "Xilinx-Way" by packing everything in Boot.bin.
> >> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841976/Prepare+boot+image
> >> and the "Linux-Way"
> >> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager
> >> using the FPGA manager
> >> https://elixir.bootlin.com/linux/latest/source/drivers/fpga/zynq-fpga.c
> >>
> >> Best regards
> >> Michael
> >>
> >>
> >>
> >>
> >>
> >>
> >>
> >>
> >> _______________________________________________
> >> barebox mailing list
> >> barebox@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/barebox
> >
> > Best regards,
> > Johannes
> >
> >
>
>
> --
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: Barebox for Zedboard

[Johannes Roith]

Am Mon, May 19, 2025 at 06:50:23AM +0000 schrieb Michael Graichen:
> 
> Dear Johannes et al.
> 
> i'am using
> 
> 
> for an PS<->PL FIFO.
> But this is not used within barebox in my case. It's only there because barebox passes it's devicetree to the Linux Kernel. I only do the programming of the FPGA in barebox within my init script by
> 
> firmwareload -t zynq-fpga-manager /mnt/boot/design_1_wrapper.bit
> 
> I will send the latest version of my zynq-fpga-manager to the mailing list soon. 
> Please feel free to pick it up and finish my work since i did not do it since 2020.
> 
> Best Regards, 
> Michael
> 
> 
Dear Michael,

thanks for sharing. The patch worked on my board just fine after
increasing the timeouts a little bit :)

If you don't mind I can take care of the patches and incoperate the
feedback from the barebox maintainer and try to bring them upstream.

Best regards,
Johannes

Re: Barebox for Zedboard

[Ahmad Fatoum]

Hi,

On 19.05.25 20:41, Johannes Roith wrote:
> Am Mon, May 19, 2025 at 06:50:23AM +0000 schrieb Michael Graichen:
>>
>> Dear Johannes et al.
>>
>> i'am using
>>
>>
>> for an PS<->PL FIFO.
>> But this is not used within barebox in my case. It's only there because barebox passes it's devicetree to the Linux Kernel. I only do the programming of the FPGA in barebox within my init script by
>>
>> firmwareload -t zynq-fpga-manager /mnt/boot/design_1_wrapper.bit
>>
>> I will send the latest version of my zynq-fpga-manager to the mailing list soon. 
>> Please feel free to pick it up and finish my work since i did not do it since 2020.

Thanks for sharing, Michael!

Cheers,
Ahmad

>>
>> Best Regards, 
>> Michael
>>
>>
> Dear Michael,
> 
> thanks for sharing. The patch worked on my board just fine after
> increasing the timeouts a little bit :)
> 
> If you don't mind I can take care of the patches and incoperate the
> feedback from the barebox maintainer and try to bring them upstream.
> 
> Best regards,
> Johannes
> 


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: Barebox for Zedboard

[Michael Tretter]

On Mon, 19 May 2025 06:55:52 +0200, Ahmad Fatoum wrote:
> On 18.05.25 19:06, Johannes Roith wrote:
> > Am Fri, May 16, 2025 at 09:28:03PM +0200 schrieb Ahmad Fatoum:
> >> Loading OF overlays can already load firmware that way.
> > 
> > Could you give me an example for an OF overlay to load a firmware?
> 
> Should look the same as in Linux (with overlay patches applied).
> 
> Michael, do you happen to have an example to share?

The overlay looks the same as in Linux and documented in
fpga-region.yaml.

For example, if your device tree contains a node with a fpga-region for
the fpga named fpga_full and the fpga-mgr property has a phandle to the
node of the FPGA Manager, the following overlay should instruct the FPGA
Manager to load the bitstream.bit firmware into the FPGA.

	/dts-v1/;
	/plugin/;
	&fpga_full {
		firmware-name = "bitstream.bin";
	};

In the overlay you should also describe the gateware implemented in the
bitstream. This allows Linux to detect what's actually implemented in
the bitstream and probe the proper drivers.

Michael