[PATCH] arm: crypto: add a check for crypto extensions support.

[PATCH] arm: crypto: add a check for crypto extensions support.

[chalianis1]

From: Chali Anis <chalianis1@gmail.com>

In some configuration the CPU may raise an exception bacause of an
unknown instruction if it does not support Crypto Extensions for
example in some BCM281X (RPi3B in my case) when running barebox
as an EFI Payload, where the EFI stops with a synchronous execption
See bellow:
Synchronous Exception at 0x0000000037BFF548
SP 0x0000000037F798C0 ELR 0x0000000037BFF548
SPSR 0x20000209 FPSR 0x00000000
ESR 0x02000000 FAR 0x14F64325185430BF
ESR : EC 0x00 IL 0x1 ISS 0x00000000

Signed-off-by: Chali Anis <chalianis1@gmail.com>
---
 arch/arm/crypto/sha1-ce-glue.c | 6 ++++++
 arch/arm/crypto/sha2-ce-glue.c | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/crypto/sha1-ce-glue.c b/arch/arm/crypto/sha1-ce-glue.c
index 5b49237573fa..3c5213774429 100644
--- a/arch/arm/crypto/sha1-ce-glue.c
+++ b/arch/arm/crypto/sha1-ce-glue.c
@@ -88,6 +88,12 @@ static struct digest_algo m = {
 
 static int sha1_ce_mod_init(void)
 {
+	uint64_t isar0;
+
+	asm volatile("mrs %0, ID_AA64ISAR0_EL1" : "=r"(isar0));
+	if (!(isar0 & 0xF00))
+		return -EOPNOTSUPP;
+
 	return digest_algo_register(&m);
 }
 coredevice_initcall(sha1_ce_mod_init);
diff --git a/arch/arm/crypto/sha2-ce-glue.c b/arch/arm/crypto/sha2-ce-glue.c
index 88cbc7993dac..f7bd818259ec 100644
--- a/arch/arm/crypto/sha2-ce-glue.c
+++ b/arch/arm/crypto/sha2-ce-glue.c
@@ -116,6 +116,12 @@ static struct digest_algo sha256 = {
 
 static int sha256_ce_digest_register(void)
 {
+	uint64_t isar0;
+
+	asm volatile("mrs %0, ID_AA64ISAR0_EL1" : "=r"(isar0));
+	if (!(isar0 & 0xF000))
+		return -EOPNOTSUPP;
+
 	return digest_algo_register(&sha256);
 }
 coredevice_initcall(sha256_ce_digest_register);
-- 
2.34.1

Re: [PATCH] arm: crypto: add a check for crypto extensions support.

[Sascha Hauer]

Hi,

On Wed, Aug 27, 2025 at 02:06:06AM -0400, chalianis1@gmail.com wrote:
> From: Chali Anis <chalianis1@gmail.com>
> 
> In some configuration the CPU may raise an exception bacause of an
> unknown instruction if it does not support Crypto Extensions for
> example in some BCM281X (RPi3B in my case) when running barebox
> as an EFI Payload, where the EFI stops with a synchronous execption
> See bellow:
> Synchronous Exception at 0x0000000037BFF548
> SP 0x0000000037F798C0 ELR 0x0000000037BFF548
> SPSR 0x20000209 FPSR 0x00000000
> ESR 0x02000000 FAR 0x14F64325185430BF
> ESR : EC 0x00 IL 0x1 ISS 0x00000000
> 
> Signed-off-by: Chali Anis <chalianis1@gmail.com>
> ---
>  arch/arm/crypto/sha1-ce-glue.c | 6 ++++++
>  arch/arm/crypto/sha2-ce-glue.c | 6 ++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/arch/arm/crypto/sha1-ce-glue.c b/arch/arm/crypto/sha1-ce-glue.c
> index 5b49237573fa..3c5213774429 100644
> --- a/arch/arm/crypto/sha1-ce-glue.c
> +++ b/arch/arm/crypto/sha1-ce-glue.c
> @@ -88,6 +88,12 @@ static struct digest_algo m = {
>  
>  static int sha1_ce_mod_init(void)
>  {
> +	uint64_t isar0;
> +
> +	asm volatile("mrs %0, ID_AA64ISAR0_EL1" : "=r"(isar0));

You could use read_sysreg():

#include <asm/sysreg.h>

	isar0 = read_sysreg(ID_AA64ISAR0_EL1);

> +	if (!(isar0 & 0xF00))
> +		return -EOPNOTSUPP;

defines for this bitmask would be cool. I just looked at the kernel and
it seems a bit overkill for barebox, but maybe something like

#define ID_AA64ISAR0_EL1_SHA1_MASK	GENMASK(11, 8)
#define ID_AA64ISAR0_EL1_SHA2_MASK	GENMASK(15, 12)

in asm/sysreg.h would do it as a start.

Sascha

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