Re: [PATCH v4 22/22] riscv: add ELF segment-based memory protection with MMU

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

Hello Sascha,

On 1/14/26 1:14 PM, Sascha Hauer wrote:
> 🤖 Generated with [Claude Code](https://claude.com/claude-code)
> 
> Co-Authored-By: Claude Sonnet 4.5 <noreply@anthropic.com>

Same comment as previous patch.

> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/riscv/Kconfig           |  17 +++
>  arch/riscv/boot/uncompress.c |  33 ++--
>  arch/riscv/cpu/Makefile      |   1 +
>  arch/riscv/cpu/mmu.c         | 354 +++++++++++++++++++++++++++++++++++++++++++
>  arch/riscv/cpu/mmu.h         | 120 +++++++++++++++
>  arch/riscv/include/asm/asm.h |   3 +-
>  arch/riscv/include/asm/mmu.h |  36 +++++
>  7 files changed, 553 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index d9794354f4ed2e8bf7276e03b968c566002c2ec6..99562c7df8927e11d4de448ad486e49dd5a0d0fd 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -129,4 +129,21 @@ config RISCV_MULTI_MODE
>  config RISCV_SBI
>  	def_bool RISCV_S_MODE
>  
> +config MMU
> +	bool "MMU-based memory protection"
> +	default y if RISCV_S_MODE

I am not familiar with MMU handling on RISC-V and while it is without
question a nice thing to have, I don't feel confident of taking Claude's
word for it that this is good enough to be the default.

Can you add a new generated defconfig (search for merge_into_defconfig)
that enable mmu in virt32_mmu_defconfig and rv64i_mmu_defconfig and hold
off making this the default for now, until someone had the chance to
look at this properly?

I believe Stefan may be a candidate for that. :)

>  	ret = elf_load_inplace(&elf);
> -	if (ret) {
> -		pr_err("Failed to relocate ELF: %d\n", ret);
> -		hang();

Nitpick: fixing code introduced in the same series earlier.

Cheer,
Ahmad

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