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Mon, 13 Apr 2026 09:27:48 +0200 Received: from sha by pty.whiteo.stw.pengutronix.de with local (Exim 4.98.2) (envelope-from ) id 1wCBi0-00000007Q7e-2Hot; Mon, 13 Apr 2026 09:27:48 +0200 Date: Mon, 13 Apr 2026 09:27:48 +0200 From: Sascha Hauer To: Michael Tretter Cc: Ahmad Fatoum , BAREBOX , Steffen Trumtrar Message-ID: References: <20260409-socfpga-iossm-v1-v2-0-09effab91bc1@pengutronix.de> <20260409-socfpga-iossm-v1-v2-4-09effab91bc1@pengutronix.de> <39a08f69-3461-48da-a890-0e3b879bb40a@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-Accept-Language: de,en X-Accept-Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260413_082757_400337_EB5A35F0 X-CRM114-Status: GOOD ( 36.40 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.1 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH v2 04/10] arm: socfpga: iossm: store size in bytes X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) On Fri, Apr 10, 2026 at 02:06:32PM +0200, Michael Tretter wrote: > On Fri, 10 Apr 2026 10:37:09 +0200, Ahmad Fatoum wrote: > > On 4/10/26 10:31 AM, Michael Tretter wrote: > > > On Fri, 10 Apr 2026 10:13:41 +0200, Ahmad Fatoum wrote: > > >> On 4/9/26 3:52 PM, Michael Tretter wrote: > > >>> The mem_width_info is the memory size in gigabits. Convert it to bytes > > >>> before storing it for each bank to have a more convenient format and > > >>> simplify the conversion when reading the value. > > >>> > > >>> Signed-off-by: Michael Tretter > > >>> --- > > >>> Changes in v2: > > >>> > > >>> - Change memory_size in io96b_mb_ctrl to phys_size_t to prevent overflow > > >> > > >> Thanks for addressing the concern. I looked it over and there's still a > > >> chance for overflow. > > >> > > >>> diff --git a/arch/arm/mach-socfpga/iossm_mailbox.c b/arch/arm/mach-socfpga/iossm_mailbox.c > > >>> index 9299fee71e0b..042ea4a99e5c 100644 > > >>> --- a/arch/arm/mach-socfpga/iossm_mailbox.c > > >>> +++ b/arch/arm/mach-socfpga/iossm_mailbox.c > > >>> @@ -9,6 +9,7 @@ > > >>> #include > > >>> #include > > >>> #include > > >>> +#include > > >>> #include "iossm_mailbox.h" > > >>> #include > > >>> #include > > >>> @@ -404,21 +405,25 @@ int io96b_get_mem_width_info(struct io96b_info *io96b_ctrl) > > >>> struct io96b_mb_resp usr_resp; > > >>> struct io96b_mb_ctrl *mb_ctrl; > > >>> int i, j; > > >>> - u16 memory_size; > > >>> - u16 total_memory_size = 0; > > >>> + phys_size_t memory_size; > > >>> + u32 mem_width_info; > > >>> + phys_size_t total_memory_size = 0; > > >>> > > >>> /* Get all memory interface(s) total memory size on all instance(s) */ > > >>> for (i = 0; i < io96b_ctrl->num_instance; i++) { > > >>> mb_ctrl = &io96b_ctrl->io96b[i].mb_ctrl; > > >>> memory_size = 0; > > >>> + > > >>> for (j = 0; j < mb_ctrl->num_mem_interface; j++) { > > >>> io96b_mb_req_no_param(io96b_ctrl->io96b[i].io96b_csr_addr, > > >>> mb_ctrl->ip_type[j], > > >>> mb_ctrl->ip_instance_id[j], > > >>> CMD_GET_MEM_INFO, GET_MEM_WIDTH_INFO, &usr_resp); > > >>> + mem_width_info = usr_resp.cmd_resp_data[1] & GENMASK(7, 0); > > >> > > >> I assume this is the RAM memory width in bytes, e.g. 2 or 4 bytes, but > > >> the mask allows it to be up to 255. > > > > > > mem_width_info is in Giga bits. > > > > Uh, is memory width here not the number of bits transferred per clock > > cycle..? > > Maybe I'm confused, but I understand that it's not the bits transferred > per clock cycle (the memory bus interface width), but information about > the memory geometry under the assumption of a memory depth of 1 Giga > bits. My understanding could be wrong, though. > > > > > > > > >> > > >>> > > >>> - memory_size = memory_size + > > >>> - (usr_resp.cmd_resp_data[1] & GENMASK(7, 0)); > > >>> + mb_ctrl->memory_size[j] = mem_width_info * (SZ_1G / SZ_8); > > >> > > >> SZ_4G / (SZ_1G / 8) = 32 > > >> > > >> So the maximum value permitted in mem_width_info without overflowing is > > >> 31, but the code accepts up to 255. As all types on the left hand side > > >> are 32-bit only. > > > > > > This driver is only available on Agilex5, which is arm64 and selects > > > PHYS_ADDR_T_64BIT. Thus, phys_size_t has 64 bits and doesn't result in > > > an overflow. > > > > Sorry, left-right confusion. The right had size is all 32-bit integers, > > so they may wrap around and are truncated before assignment to the > > 64-bit left hand side. > > Ah, indeed. I'll add the necessary cast to the right hand side. Added a cast to phys_size_t to the right hand side while applying. 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