From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Sascha Hauer <s.hauer@pengutronix.de>,
BAREBOX <barebox@lists.infradead.org>
Subject: Re: [PATCH v2 4/6] ARM: MMU: map text segment ro and data segments execute never
Date: Wed, 18 Jun 2025 10:13:52 +0200 [thread overview]
Message-ID: <aec47b1f-c022-4490-ab57-3fc6689ebc6b@pengutronix.de> (raw)
In-Reply-To: <20250617-mmu-xn-ro-v2-4-3c7aa9046b67@pengutronix.de>
On 6/17/25 16:28, Sascha Hauer wrote:
> With this all segments in the DRAM except the text segment are mapped
> execute-never so that only the barebox code can actually be executed.
> Also map the readonly data segment readonly so that it can't be
> modified.
>
> The mapping is only implemented in barebox proper. The PBL still maps
> the whole DRAM rwx.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> +config ARM_MMU_PERMISSIONS
> + bool "Map with extended RO/X permissions"
> + default y
> + help
> + Enable this option to map readonly sections as readonly, executable
> + sections as readonly/executable and the remainder of the SDRAM as
> + read/write/non-executable.
> + Traditionally barebox maps the whole SDRAM as read/write/execute.
> + You get this behaviour by disabling this option which is meant as
> + a debugging facility. It can go away once the extended permission
> + settings are proved to work reliable.
> +
> config ARM_SEMIHOSTING
> bool "enable ARM semihosting support"
> select SEMIHOSTING
> diff --git a/arch/arm/cpu/lowlevel_32.S b/arch/arm/cpu/lowlevel_32.S
> index 960a92b78c0adaf815948517ba917ae85ae65e27..5d524faf9cff9a8b545044169b8255279dd8ab0b 100644
> --- a/arch/arm/cpu/lowlevel_32.S
> +++ b/arch/arm/cpu/lowlevel_32.S
> @@ -70,6 +70,7 @@ THUMB( orr r12, r12, #PSR_T_BIT )
> orr r12, r12, #CR_U
> bic r12, r12, #CR_A
> #else
> + orr r12, r12, #CR_S
FTR, because I looked it up: CR_S was deprecated for ARMv6, but before
that, it was the system protection bit and is a prerequisite for access
permission. So this change looks fine.
>From ARMv5 ARM at:
https://developer.arm.com/documentation/ddi0100/i/?lang=en
> @@ -627,11 +666,7 @@ void mmu_early_enable(unsigned long membase, unsigned long memsize, unsigned lon
>
> set_ttbr(ttb);
>
> - /* For the XN bit to take effect, we can't be using DOMAIN_MANAGER. */
> - if (cpu_architecture() >= CPU_ARCH_ARMv7)
> - set_domain(DOMAIN_CLIENT);
> - else
> - set_domain(DOMAIN_MANAGER);
> + set_domain(DOMAIN_CLIENT);
Good. I had added this check ultimately out of laziness.
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next prev parent reply other threads:[~2025-06-18 8:19 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-17 14:28 [PATCH v2 0/6] ARM: Map sections RO/XN Sascha Hauer
2025-06-17 14:28 ` [PATCH v2 1/6] ARM: pass barebox base to mmu_early_enable() Sascha Hauer
2025-06-17 14:28 ` [PATCH v2 2/6] ARM: mmu: move ARCH_MAP_WRITECOMBINE to header Sascha Hauer
2025-06-17 14:28 ` [PATCH v2 3/6] ARM: MMU: map memory for barebox proper pagewise Sascha Hauer
2025-06-17 14:28 ` [PATCH v2 4/6] ARM: MMU: map text segment ro and data segments execute never Sascha Hauer
2025-06-18 8:13 ` Ahmad Fatoum [this message]
2025-06-17 14:28 ` [PATCH v2 5/6] ARM: MMU64: map memory for barebox proper pagewise Sascha Hauer
2025-06-18 8:32 ` Ahmad Fatoum
2025-06-17 14:28 ` [PATCH v2 6/6] ARM: MMU64: map text segment ro and data segments execute never Sascha Hauer
2025-06-18 8:33 ` Ahmad Fatoum
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