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Tue, 18 Aug 2026 08:44:36 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with UTF8SMTP id 5A479418D0; Tue, 18 Aug 2026 08:44:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with UTF8SMTPSA id A817F1F00A3A; Tue, 18 Aug 2026 08:44:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787042675; bh=fLIxoLO5aO5ZsK/WAoCEXUmM++XUZBcfnXcvYgTTjTU=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=At6dMv18yzGpmnCvQrDi6gNv2r61YctrTyO3TKadjHj5snvb9etNfkoG6gzJCCvtb 5bWrGAD3sjLTJeCtgDcy7LvUEpdbxJlPUdxcwEbLLciuH2ideGyhL/8gkIn91+JBHV BGJ9uK6BXxMHHyiohJuV8TIRwWqZaogacPPI6u/Fkkq3aADJldsFeEp1XREJSc6tZa DDVUOopyHIUAxdrqZO13MLpoC/1Ls9SSBGLzFLcsiTGxFNJrRqpnzfSl8l6ER9UA8z nbUy7Zncs6H3xLY6d+aqhvdiXaz350YdEFxDXXxbBbw5Z/F9d06iMTbf/iqLZjDMEH sa8DA7zq/W1IA== Date: Tue, 18 Aug 2026 10:44:32 +0200 From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= To: Sascha Hauer , Luca Lauro Cc: Luca Lauro via B4 Relay , "open list:BAREBOX" Subject: Re: [PATCH v4 01/14] ARM: mvebu: add Netgear RN102 support Message-ID: References: <20260813-rn102-rn104-series-v4-1-f932ac63efa0@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; 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MIME_TRACE(0.00)[0:+,1:+,2:~]; RECEIVED_HELO_LOCALHOST(0.00)[]; RCVD_COUNT_THREE(0.00)[4]; ARC_NA(0.00)[]; FROM_HAS_DN(0.00)[]; FREEMAIL_TO(0.00)[pengutronix.de,gmail.com]; FORWARDED(0.00)[barebox@lists.infradead.org]; FORGED_SENDER(0.00)[ukleinek@kernel.org,barebox-bounces@lists.infradead.org]; TO_DN_ALL(0.00)[]; TAGGED_FROM(0.00)[lore=pengutronix.de]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; TAGGED_RCPT(0.00)[famlauro93l.gmail.com]; NEURAL_HAM(-0.00)[-1.000]; RCVD_TLS_LAST(0.00)[]; MISSING_XM_UA(0.00)[]; DKIM_TRACE(0.00)[lists.infradead.org:+,kernel.org:+]; RCPT_COUNT_THREE(0.00)[4]; FROM_NEQ_ENVFROM(0.00)[ukleinek@kernel.org,barebox-bounces@lists.infradead.org]; FORGED_SENDER_FORWARDING(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Queue-Id: 1BFBC201D0B --dsmnold6nv2o4ger Content-Type: text/plain; protected-headers=v1; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v4 01/14] ARM: mvebu: add Netgear RN102 support MIME-Version: 1.0 Hello, oh, it seems I have to work out again how to get access to the serial of my RN104. Great there are some efforts for that machine. @Luca, somewhat related, my RN104 runs Debian and since quite some time I see issues in the network driver with overruns corrupting transfers. Do you see these, too? On Mon, Aug 17, 2026 at 07:51:28AM +0000, Sascha Hauer wrote: > On 2026-08-13 17:26, Luca Lauro via B4 Relay wrote: > > + filetype_kwbimage_v1); > > + > > + return 0; > > +} > > + > > +static const struct of_device_id rn102_of_match[] =3D { > > + { .compatible =3D "netgear,rn102" }, >=20 > How is the driver probed? The string "netgear,rn102" is in no dts. > Unless I am missing something this should be "netgear,readynas-102". >=20 > Same for the rn104 patch. >=20 > > +/* > > + * NOTE: > > + * armada_370_xp_barebox_entry() cannot be used here because the > > + * upstream SDRAM size detection for Armada 370-XP misinterprets > > + * the DDR_SIZE_CSn registers on this board and reports an incorrect > > + * memory size (256MB instead of 512MB on RN102). > > + * > > + * Until the generic detection code is fixed, we compute the SDRAM > > + * size manually using the DDR_SIZE_CSn values. > > + */ > > +static unsigned long armada_370_xp_memory_find(void) > > +{ > > + unsigned long mem_size =3D 0; > > + > > + for (int cs =3D 0; cs < 4; cs++) { > > + u32 ctrl =3D readl(ARMADA_370_XP_SDRAM_BASE + DDR_SIZE_CSn(cs)); > > + > > + /* Skip non-enabled CS */ > > + if ((ctrl & DDR_SIZE_ENABLED) !=3D DDR_SIZE_ENABLED) > > + continue; > > + > > + mem_size +=3D (ctrl | ~DDR_SIZE_MASK) + 1; > > + } > > + > > + return mem_size; > > +} >=20 > The only difference I can spot here between this function and the > existing variant in arch/arm/mach-mvebu/common.c is: >=20 > #define DDR_SIZE_MASK 0xff000000 >=20 > whereas the common.c variant uses: >=20 > #define ARMADA_370_XP_DDR_SIZE_MASK 0xffff0000 Apart from the different value, the latter name is the better one B-) > The latter goes down to this: >=20 > > commit 7351b6b5c59c7a280787998006f39a5cd3a2f18b > > Author: Uwe Kleine-K=F6nig > > Date: Tue Jun 13 00:37:49 2017 +0200 > > > > ARM: mvebu: fix size mask for RAM window > > =20 > > The size field in the window control register occupies bits 31:16. = So > > adapt ARMADA_370_XP_DDR_SIZE_MASK accordingly. This fixes detection= of > > RAM chips smaller than 32 MiB and so probably doesn't affect any > > supported machine. > > =20 > > Signed-off-by: Uwe Kleine-K=F6nig > > Signed-off-by: Sascha Hauer > > > > diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c > > index 06bfb72615..fa971da11e 100644 > > --- a/arch/arm/mach-mvebu/common.c > > +++ b/arch/arm/mach-mvebu/common.c > > @@ -47,7 +47,7 @@ > > #define ARMADA_370_XP_SDRAM_BASE (IOMEM(MVEBU_REMAP_INT_REG_BASE= ) + 0x20000) > > #define ARMADA_370_XP_DDR_SIZE_CSn(n) (0x184 + ((n) * 0x8)) > > #define ARMADA_370_XP_DDR_SIZE_ENABLED BIT(0) > > -#define ARMADA_370_XP_DDR_SIZE_MASK 0xff000000 > > +#define ARMADA_370_XP_DDR_SIZE_MASK 0xffff0000 > >=20 > > /* > > * Marvell MVEBU SoC id and revision can be read from any PCIe >=20 > @Uwe, Where did you get that information from. Could it be that we > should just revert this one given that it seems to be untested on your > side? 0xffff0000 is in line with https://datasheet.datasheetarchive.com/originals/crawler/marvell.com/002fa4= 41a27967d992f905776d519926.pdf (page 630). So I'd expect that 0xffff0000 is correct, but I don't care much. Best regards Uwe --dsmnold6nv2o4ger Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEP4GsaTp6HlmJrf7Tj4D7WH0S/k4FAmqEG20ACgkQj4D7WH0S /k5lEQgAlIBMza6mU6NYAAzzoEp/mp9bb4eirAqx7HBO6IHhLnSqxZurkS1dWzDL XQHXBvFloyHnpTLicsGWmMk/ZrhfDbQDxVO1S697nzgXy2SN/d+40Ml3VZ+CniB3 /GcEDLwIyc2aqyZT0HAFQWQ3OgDoTfagG4gmsOHXGhEF30WwkjXVGeaOO7f9Ofiz Z2qawPSdjAoTzZ/ROL5/RfTOZzy9K5gw0I58euLzFBocTI5VqxVKX7VZbb2P3zW9 gXV4UQ4UFSrKl/q5Y40cxECR6zZx3qycfrUqF/UJaW0PGPiNqQAQ/HuZixy7AwLd WrtH9ivElXRdbrOCrYzrzFBj8fRd5A== =Dx0p -----END PGP SIGNATURE----- --dsmnold6nv2o4ger--