Hallo Sascha,

On Wed, Aug 19, 2026 at 07:16:43AM +0000, Sascha Hauer wrote:
> On 2026-08-18 10:44, Uwe Kleine-König wrote:
> > >
> > > The only difference I can spot here between this function and the
> > > existing variant in arch/arm/mach-mvebu/common.c is:
> > > 
> > > #define  DDR_SIZE_MASK                       0xff000000
> > > 
> > > whereas the common.c variant uses:
> > > 
> > > #define ARMADA_370_XP_DDR_SIZE_MASK     0xffff0000
> > 
> > Apart from the different value, the latter name is the better one B-)
> > 
> > > The latter goes down to this:
> > > 
> > > > commit 7351b6b5c59c7a280787998006f39a5cd3a2f18b
> > > > Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> > > > Date:   Tue Jun 13 00:37:49 2017 +0200
> > > >
> > > >     ARM: mvebu: fix size mask for RAM window
> > > >    
> > > >     The size field in the window control register occupies bits 31:16. So
> > > >     adapt ARMADA_370_XP_DDR_SIZE_MASK accordingly. This fixes detection of
> > > >     RAM chips smaller than 32 MiB and so probably doesn't affect any
> > > >     supported machine.
> > > >    
> > > >     Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> > > >     Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > >
> > > > diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
> > > > index 06bfb72615..fa971da11e 100644
> > > > --- a/arch/arm/mach-mvebu/common.c
> > > > +++ b/arch/arm/mach-mvebu/common.c
> > > > @@ -47,7 +47,7 @@
> > > >  #define ARMADA_370_XP_SDRAM_BASE       (IOMEM(MVEBU_REMAP_INT_REG_BASE) + 0x20000)
> > > >  #define ARMADA_370_XP_DDR_SIZE_CSn(n)  (0x184 + ((n) * 0x8))
> > > >  #define ARMADA_370_XP_DDR_SIZE_ENABLED BIT(0)
> > > > -#define ARMADA_370_XP_DDR_SIZE_MASK    0xff000000
> > > > +#define ARMADA_370_XP_DDR_SIZE_MASK    0xffff0000
> > > > 
> > > >  /*
> > > >   * Marvell MVEBU SoC id and revision can be read from any PCIe
> > > 
> > > @Uwe, Where did you get that information from. Could it be that we
> > > should just revert this one given that it seems to be untested on your
> > > side?
> > 
> > 0xffff0000 is in line with
> > https://datasheet.datasheetarchive.com/originals/crawler/marvell.com/002fa441a27967d992f905776d519926.pdf
> > (page 630). So I'd expect that 0xffff0000 is correct, but I don't care
> > much.
> 
> Page 630 describes the register at offset 0x20000. I think the correct
> page to look at is 626 which describes 0x20184 aka ARMADA_370_XP_DDR_SIZE_CSn(0).
> 
> That one has the window size in the upper 8 bit. Looks like we should
> just revert 7351b6b5c59c. @Luca, does the SDRAM size detection work for
> you with that patch reverted?

Oh, indeed, you're right. Then I guess I did the same mistake already
back in 2017.

I would expect from my 2017 self that he tested that change, and given
that the bits he got wrong are documented to read as 1 I think the
impact isn't relevant as long as a size > 32 MiB is configured. (That's
not an argument to not revert 7351b6b5c59c7a280787998006f39a5cd3a2f18b,
only wondering about this bug being relevant for Luca.)

Take my ack when you do the revert. (I'm not spelling it out here to not
confuse b4 that will probably assign it to the patch mentioned in the
Subject.)

Best regards
Uwe