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Content preview: On Wed, 07 Oct 2026 12:55:53 +0200, Michael Tretter wrote: > Make the QSPI flash available in the PBL to be able to read a second > stage boot loader from flash. > > Signed-off-by: Michael Tretter List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Spamd-Result: default: False [-60.41 / 15.00]; RECEIVED_AUTHENTICATED_BY_MX1(-50.00)[]; BAYES_HAM(-3.00)[100.00%]; ARC_ALLOW_TRUSTED(-2.00)[pengutronix.de:s=20260414:i=1]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; ARC_ALLOW(-1.00)[pengutronix.de:s=20260414:i=1]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; R_SPF_ALLOW(-0.20)[+mx:c]; RCVD_IN_DNSWL_MED(-0.20)[2607:7c80:54:3::133:from]; MAILLIST(-0.20)[mailman]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,pengutronix.de:s=20260414]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RCVD_COUNT_THREE(0.00)[4]; RECEIVED_HELO_LOCALHOST(0.00)[]; RCPT_COUNT_TWO(0.00)[2]; DMARC_NA(0.00)[pengutronix.de]; FORWARDED(0.00)[barebox@lists.infradead.org]; FORGED_SENDER(0.00)[m.tretter@pengutronix.de,barebox-bounces@lists.infradead.org]; MIME_TRACE(0.00)[0:+]; RCVD_TLS_LAST(0.00)[]; MISSING_XM_UA(0.00)[]; TAGGED_FROM(0.00)[lore=pengutronix.de]; FORGED_SENDER_FORWARDING(0.00)[]; NEURAL_HAM(-0.00)[-1.000]; FROM_NEQ_ENVFROM(0.00)[m.tretter@pengutronix.de,barebox-bounces@lists.infradead.org]; FROM_HAS_DN(0.00)[]; TO_DN_ALL(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; RCVD_VIA_SMTP_AUTH(0.00)[]; DKIM_TRACE(0.00)[lists.infradead.org:+,pengutronix.de:+]; ARC_SIGNED(0.00)[pengutronix.de:s=20260414:i=2]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Action: no action X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: 7F4A3201E26 X-Stat-Signature: r3dpoaig371u9d9raerici741mxb7bjm On Wed, 07 Oct 2026 12:55:53 +0200, Michael Tretter wrote: > Make the QSPI flash available in the PBL to be able to read a second > stage boot loader from flash. > > Signed-off-by: Michael Tretter > --- > arch/arm/mach-socfpga/atf.c | 34 +++++++++++++++++++++++++++------- > 1 file changed, 27 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/mach-socfpga/atf.c b/arch/arm/mach-socfpga/atf.c > index 6d036d20d4b6..a59a73d1c31f 100644 > --- a/arch/arm/mach-socfpga/atf.c > +++ b/arch/arm/mach-socfpga/atf.c > @@ -13,29 +13,46 @@ > #include > > #include > +#include > > -static void socfpga_agilex5_qspi_init(void) > +static struct pbl_bio *socfpga_agilex5_qspi_init(struct pbl_bio *bio) > { > + void __iomem *iobase = IOMEM(SOCFPGA_HPS2SDM_QSPI_REGS); > + void __iomem *ahb_base = IOMEM(SOCFPGA_HPS2SDM_QSPI_DATA); > + struct cadence_qspi_platform_data pdata = { > + .is_decoded_cs = 0, > + .fifo_depth = 128, > + }; > unsigned long master_ref_clk = 0; > int ret; > > ret = socfpga_mailbox_s10_init(); > if (ret) { > pr_warn("Failed to init s10 mailbox: %d\n", ret); > - return; > + return PTR_ERR(-ENODEV); This should have been return ERR_PTR(-ENODEV); Michael > } > > ret = socfpga_mailbox_s10_qspi_open(&master_ref_clk); > if (ret) { > pr_warn("Failed to request QSPI access: %d\n", ret); > - return; > + return ERR_PTR(-ENODEV); > } > > + /* > + * Failing to store the reference clock may result in an unavailable > + * QSPI flash later, but is not fatal. > + */ > ret = socfpga_agilex5_write_qspi_refclk(master_ref_clk); > - if (ret) { > + if (ret) > pr_warn("Failed to store reference clock: %d\n", ret); > - return; > + > + ret = cqspi_bio_init(bio, iobase, ahb_base, master_ref_clk, &pdata); > + if (ret) { > + pr_warn("failed to initialize bio for qspi\n"); > + return ERR_PTR(-ENODEV); > } > + > + return bio; > } > > static int agilex5_load_bl33_piggy(void *bl33) > @@ -92,6 +109,7 @@ static void __noreturn agilex5_start_image_via_tfa(void *bl33) > static void agilex5_el3_init(void) > { > void *bl33 = (void *)AGILEX5_ATF_BL33_BASE_ADDR; > + struct pbl_bio tmp, *bio; > int ret; > > agilex5_initialize_security_policies(); > @@ -101,9 +119,11 @@ static void agilex5_el3_init(void) > if (ret) > panic("DDR initialization failed\n"); > > - socfpga_agilex5_qspi_init(); > + bio = socfpga_agilex5_qspi_init(&tmp); > + if (IS_ERR_OR_NULL(bio)) > + bio = NULL; > > - agilex5_load_bl33(NULL, bl33); > + agilex5_load_bl33(bio, bl33); > > agilex5_start_image_via_tfa(bl33); > } > > -- > 2.47.3 >