Re: [PATCH v2 12/14] nvmem: rockchip-otp: Add RK3562 support

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

On 1/30/26 06:17, Sohaib Mohamed wrote:
> Add RK3562 OTP support using rk3562-specific data configuration.
> 
> Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com>

Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

> ---
>  drivers/nvmem/rockchip-otp.c | 89 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 89 insertions(+)
> 
> diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c
> index 33b242c5bc..d2145bba52 100644
> --- a/drivers/nvmem/rockchip-otp.c
> +++ b/drivers/nvmem/rockchip-otp.c
> @@ -51,6 +51,21 @@
>  
>  #define OTPC_TIMEOUT			10000
>  
> +#define RK3562_NBYTES			2
> +
> +/* RK3588 Register */
> +#define RK3582_OTPC_AUTO_CTRL	0x04
> +#define RK3582_OTPC_AUTO_EN		0x08
> +#define RK3582_OTPC_INT_ST		0x84
> +#define RK3582_OTPC_DOUT0		0x20
> +#define RK3582_NO_SECURE_OFFSET	0x300
> +#define RK3582_NBYTES			4
> +#define RK3582_BURST_NUM		1
> +#define RK3582_BURST_SHIFT		8
> +#define RK3582_ADDR_SHIFT		16
> +#define RK3582_AUTO_EN			BIT(0)
> +#define RK3582_RD_DONE			BIT(1)
> +
>  #define RK3568_NBYTES			2
>  
>  /* RK3588 Register */
> @@ -183,6 +198,65 @@ static int px30_otp_read(void *context, unsigned int offset,
>  	return ret;
>  }
>  
> +static int rk3562_otp_read(void *context, unsigned int offset, void *val,
> +			   size_t bytes)
> +{
> +	struct rockchip_otp *otp = context;
> +	unsigned int addr_start, addr_end, addr_offset, addr_len;
> +	u32 out_value;
> +	u8 *buf;
> +	int ret = 0, i = 0;
> +
> +	addr_start = rounddown(offset, RK3562_NBYTES) / RK3562_NBYTES;
> +	addr_end = roundup(offset + bytes, RK3562_NBYTES) / RK3562_NBYTES;
> +	addr_offset = offset % RK3562_NBYTES;
> +	addr_len = addr_end - addr_start;
> +
> +	buf = kzalloc(array3_size(addr_len, RK3562_NBYTES, sizeof(*buf)),
> +		      GFP_KERNEL);
> +	if (!buf)
> +		return -ENOMEM;
> +
> +	ret = rockchip_otp_reset(otp);
> +	if (ret) {
> +		dev_err(otp->dev, "failed to reset otp phy\n");
> +		goto out;
> +	}
> +
> +	ret = rockchip_otp_ecc_enable(otp, false);
> +	if (ret < 0) {
> +		dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
> +		goto out;
> +	}
> +
> +	writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
> +	udelay(5);
> +	while (addr_len--) {
> +		writel(addr_start++ | OTPC_USER_ADDR_MASK,
> +		       otp->base + OTPC_USER_ADDR);
> +		writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
> +		       otp->base + OTPC_USER_ENABLE);
> +		ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE);
> +		if (ret < 0) {
> +			dev_err(otp->dev, "timeout during read setup\n");
> +			goto read_end;
> +		}
> +		out_value = readl(otp->base + OTPC_USER_Q);
> +		memcpy(&buf[i], &out_value, RK3562_NBYTES);
> +		i += RK3562_NBYTES;
> +	}
> +
> +	memcpy(val, buf + addr_offset, bytes);
> +
> +read_end:
> +	writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
> +out:
> +	kfree(buf);
> +
> +	return ret;
> +}
> +
> +
>  static int rk3568_otp_read(void *context, unsigned int offset, void *val,
>  			   size_t bytes)
>  {
> @@ -328,6 +402,17 @@ static const struct rockchip_data px30_data = {
>  	.reg_read = px30_otp_read,
>  };
>  
> +static const char * const rk3562_otp_clocks[] = {
> +	"usr", "sbpi", "apb", "phy",
> +};
> +
> +static const struct rockchip_data rk3562_data = {
> +	.size = 0x80,
> +	.clks = rk3562_otp_clocks,
> +	.num_clks = ARRAY_SIZE(rk3562_otp_clocks),
> +	.reg_read = rk3562_otp_read,
> +};
> +
>  static const char * const rk3568_otp_clocks[] = {
>  	"usr", "sbpi", "apb", "phy",
>  };
> @@ -366,6 +451,10 @@ static __maybe_unused const struct of_device_id rockchip_otp_match[] = {
>  		.compatible = "rockchip,rk3308-otp",
>  		.data = &px30_data,
>  	},
> +	{
> +		.compatible = "rockchip,rk3562-otp",
> +		.data = &rk3562_data,
> +	},
>  	{
>  		.compatible = "rockchip,rk3568-otp",
>  		.data = &rk3568_data,
> 


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