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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Sascha Hauer <s.hauer@pengutronix.de>, barebox@lists.infradead.org
Subject: Re: [PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent
Date: Thu, 11 Jan 2024 15:15:35 +0100	[thread overview]
Message-ID: <c09e8b3d-539e-4890-878d-ec699df00fb4@pengutronix.de> (raw)
In-Reply-To: <170498227339.3258338.12191952900235410621.b4-ty@pengutronix.de>

Hello Sascha,

On 11.01.24 15:11, Sascha Hauer wrote:
> 
> On Wed, 10 Jan 2024 17:01:02 +0100, Ahmad Fatoum wrote:
>> Upstream DT changed /soc of NXP Layerscape LS1046A to be dma-coherent.
>> This means that:
>>
>>  1) Linux v6.1 expects bootloader to configure DMA masters to snoop
>>     caches
>>  2) bootloader needs to skip cache maintenance when talking to DMA
>>     master when it has set snoop bits
>>
>> [...]
> 
> Applied, thanks!
> 
> [01/11] dma: rename OF_DMA_DEFAULT_COHERENT to ARCH_DMA_DEFAULT_COHERENT
>         commit: 6012c3867777e9e6d6b14d0117f8b37e2b860642

Does the commit hash mean it was applied to master? If it's also for next,
it may be confusing, because these commit hashes aren't stable.

(I don't mind this series going into master though. It fixes a bug after
 all).

Thanks,
Ahmad

> [02/11] dma: select ARCH_DMA_DEFAULT_COHERENT for x86 and sandbox
>         commit: a16e16575ae797e33f1a499b5f6e28f6cf6c3527
> [03/11] dma: introduce CONFIG_OF_DMA_COHERENCY
>         commit: 62753977d4231a160e4fb3bd3fe585e151792eb4
> [04/11] RISC-V: StarFive: J7100: set /soc/dma-noncoherent
>         commit: 4c42bc96da90c88b2dcb2b24bb56aad1f9119f9f
> [05/11] ARM: dts: layerscape: add header for barebox DT overrides
>         commit: 224bbd61d5744b19963f8d0335ef5f355eed9850
> [06/11] ARM: dts: layerscape: mark ls1046a SoC DMA incoherent in DT
>         commit: 5961dae8f9d11c918522c035889045f6f65bca91
> [07/11] of: populate new device_d::dma_coherent attribute
>         commit: 804a07a7bb573334b6eeb4049c92f28421f2a00a
> [08/11] dma: fix dma_sync when not all device DMA is equally coherent
>         commit: f856171ad6bfd067729350d9604622f8cf09ba07
> [09/11] dma: align barebox DMA coherency setting with kernel's
>         commit: de265d926a92462b836749d2633faef2631b459c
> [10/11] ARM: layerscape: configure all DMA masters to be cache-coherent
>         commit: 475a399049ce30c40c86bf9e51cfa993f5ce573d
> [11/11] ARM: layerscape: enable DWC3 snooping on ls1046a
>         commit: f1f215dbef3a49754e03078f61258bd5e06286f7
> 
> Best regards,

-- 
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  reply	other threads:[~2024-01-11 14:16 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-10 16:01 Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 01/11] dma: rename OF_DMA_DEFAULT_COHERENT to ARCH_DMA_DEFAULT_COHERENT Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 02/11] dma: select ARCH_DMA_DEFAULT_COHERENT for x86 and sandbox Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 03/11] dma: introduce CONFIG_OF_DMA_COHERENCY Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 04/11] RISC-V: StarFive: J7100: set /soc/dma-noncoherent Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 05/11] ARM: dts: layerscape: add header for barebox DT overrides Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 06/11] ARM: dts: layerscape: mark ls1046a SoC DMA incoherent in DT Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 07/11] of: populate new device_d::dma_coherent attribute Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 08/11] dma: fix dma_sync when not all device DMA is equally coherent Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 09/11] dma: align barebox DMA coherency setting with kernel's Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 10/11] ARM: layerscape: configure all DMA masters to be cache-coherent Ahmad Fatoum
2024-01-10 16:01 ` [PATCH v2 11/11] ARM: layerscape: enable DWC3 snooping on ls1046a Ahmad Fatoum
2024-01-11 14:11 ` [PATCH v2 00/11] ARM64: layerscape: make LS1046 DMA coherent Sascha Hauer
2024-01-11 14:15   ` Ahmad Fatoum [this message]
2024-01-11 14:44     ` Sascha Hauer

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