Re: reset / watchdog on an imx7d soc

[Lucas Stach <l.stach@pengutronix.de>]

Hi Giorgio,

Am Donnerstag, den 02.07.2020, 17:28 +0200 schrieb Giorgio Dal Molin:
[...]
> barebox does something similar to trigger the wdog but afterwards also calls
> mdelay() and a printf() before falling in the endless loop:
> 
> static void imx21_soc_reset(struct imx_wd *priv)
> {
> ...
> 	imxwd_write(priv, IMX21_WDOG_WCR, val);
> 
> 	/* Two additional writes due to errata ERR004346 */
> 	imxwd_write(priv, IMX21_WDOG_WCR, val);
> 	imxwd_write(priv, IMX21_WDOG_WCR, val);
> 

I'm not sure if the i.MX7 needs the same double write. Just in case,
can you add a dummy read to the IMX21_WDOG_WCR register after the
writes to make sure the writes actually get flushed to the device
before the delay?

Regards,
Lucas

> ...
> 
> 	mdelay(1000);
> 
> 	hang(); // <== this also calls printf() before for(;;);
> 
> 
> What I've found is that if I put the endless loop right at the end of
> imx21_soc_reset(), after the imxwd_write's, then the reboot process becomes
> reliable.
> 
> (The changes in the DCD with the addition of the write:
> 
> wm 32 0x30391000 0x00000003
> 
> at the beginning, before the write:
> 
> wm 32 0x30391000 0x00000002
> 
> are also essential, only the delay between the two seems to be not a big deal).
> 
> giorgio
> 
> > > giorgio
> > > 
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