* [PATCH 1/9] ARM: Layerscape: TQMLS1046a: Update DDR timings
2024-10-21 7:21 [PATCH 0/9] ARM: Layerscape: LS1046a: switch to TF-A Sascha Hauer
@ 2024-10-21 7:21 ` Sascha Hauer
2024-10-21 7:21 ` [PATCH 2/9] ARM: Layerscape: TQMLS1046a: add support for 8GiB variant Sascha Hauer
` (7 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 7:21 UTC (permalink / raw)
To: open list:BAREBOX
Update DDR timings from TQ U-Boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/tqmls1046a/lowlevel.c | 54 +++++++++++++++++------------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 2551a18ec6..6d25b5cda8 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -38,43 +38,43 @@ static struct fsl_ddr_controller ddrc[] = {
.cs[3].config = 0x00000000,
.cs[3].config_2 = 0x00000000,
.timing_cfg_3 = 0x020F1100,
- .timing_cfg_0 = 0x77660008,
- .timing_cfg_1 = 0xF1FCC265,
- .timing_cfg_2 = 0x0059415E,
- .ddr_sdram_cfg = 0x65000000,
+ .timing_cfg_0 = 0xF7660008,
+ .timing_cfg_1 = 0xF1FC4178,
+ .timing_cfg_2 = 0x00590160,
+ .ddr_sdram_cfg = 0x65000008,
.ddr_sdram_cfg_2 = 0x00401150,
- .ddr_sdram_cfg_3 = 0x00000000,
- .ddr_sdram_mode = 0x03010625,
+ .ddr_sdram_cfg_3 = 0x40000000,
+ .ddr_sdram_mode = 0x01030631,
.ddr_sdram_mode_2 = 0x00100200,
- .ddr_sdram_mode_3 = 0x00010625,
- .ddr_sdram_mode_4 = 0x00100200,
- .ddr_sdram_mode_5 = 0x00010625,
- .ddr_sdram_mode_6 = 0x00100200,
- .ddr_sdram_mode_7 = 0x00010625,
- .ddr_sdram_mode_8 = 0x00100200,
+ .ddr_sdram_mode_3 = 0x00000000,
+ .ddr_sdram_mode_4 = 0x00000000,
+ .ddr_sdram_mode_5 = 0x00000000,
+ .ddr_sdram_mode_6 = 0x00000000,
+ .ddr_sdram_mode_7 = 0x00000000,
+ .ddr_sdram_mode_8 = 0x00000000,
.ddr_sdram_mode_9 = 0x00000500,
- .ddr_sdram_mode_10 = 0x04400000,
- .ddr_sdram_mode_11 = 0x00000400,
- .ddr_sdram_mode_12 = 0x04400000,
- .ddr_sdram_mode_13 = 0x00000400,
- .ddr_sdram_mode_14 = 0x04400000,
- .ddr_sdram_mode_15 = 0x00000400,
- .ddr_sdram_mode_16 = 0x04400000,
- .ddr_sdram_interval = 0x0F3C0000,
+ .ddr_sdram_mode_10 = 0x08800000,
+ .ddr_sdram_mode_11 = 0x00000000,
+ .ddr_sdram_mode_12 = 0x00000000,
+ .ddr_sdram_mode_13 = 0x00000000,
+ .ddr_sdram_mode_14 = 0x00000000,
+ .ddr_sdram_mode_15 = 0x00000000,
+ .ddr_sdram_mode_16 = 0x00000000,
+ .ddr_sdram_interval = 0x0F3C079E,
.ddr_data_init = 0xDEADBEEF,
- .ddr_sdram_clk_cntl = 0x02000000,
+ .ddr_sdram_clk_cntl = 0x03000000,
.ddr_init_addr = 0x00000000,
.ddr_init_ext_addr = 0x00000000,
- .timing_cfg_4 = 0x00224002,
- .timing_cfg_5 = 0x04401400,
+ .timing_cfg_4 = 0x00220002,
+ .timing_cfg_5 = 0x00000000,
.timing_cfg_6 = 0x00000000,
.timing_cfg_7 = 0x25500000,
- .timing_cfg_8 = 0x03335A00,
+ .timing_cfg_8 = 0x05447A00,
.timing_cfg_9 = 0x00000000,
.ddr_zq_cntl = 0x8A090705,
- .ddr_wrlvl_cntl = 0x86550609,
- .ddr_wrlvl_cntl_2 = 0x09080806,
- .ddr_wrlvl_cntl_3 = 0x06040409,
+ .ddr_wrlvl_cntl = 0x8605070A,
+ .ddr_wrlvl_cntl_2 = 0x0A080807,
+ .ddr_wrlvl_cntl_3 = 0x0706060A,
.ddr_sr_cntr = 0x00000000,
.ddr_sdram_rcw_1 = 0x00000000,
.ddr_sdram_rcw_2 = 0x00000000,
--
2.39.5
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 2/9] ARM: Layerscape: TQMLS1046a: add support for 8GiB variant
2024-10-21 7:21 [PATCH 0/9] ARM: Layerscape: LS1046a: switch to TF-A Sascha Hauer
2024-10-21 7:21 ` [PATCH 1/9] ARM: Layerscape: TQMLS1046a: Update DDR timings Sascha Hauer
@ 2024-10-21 7:21 ` Sascha Hauer
2024-10-21 9:06 ` Ahmad Fatoum
2024-10-21 7:21 ` [PATCH 3/9] ARM: Layerscape: ls1046ardb: remove unused variable Sascha Hauer
` (6 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 7:21 UTC (permalink / raw)
To: open list:BAREBOX
The tqmls1046a also has a 8GiB DDR variant. This patch adds support for
this variant as an additional image with suffix _8g in the name.
The 8GiB boards use two different types of DDR chips which can be
distinguished by reading the EEPROM. There is one regular version which
has the string "TQMLS1046A-P2.0201" is the EEPROM. The other one is
possibly only used for Arkona and has the string "TQMLS1046A-CA.0202"
in the EEPROM. There might be other possible strings we are currently
not aware of, we fall back to the P2 variant in this case.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/tqmls1046a/board.c | 32 ++++-
arch/arm/boards/tqmls1046a/lowlevel.c | 237 +++++++++++++++++++++++++++++++++-
arch/arm/boards/tqmls1046a/start.S | 5 +
images/Makefile.layerscape | 14 +-
include/mach/layerscape/layerscape.h | 1 +
5 files changed, 277 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c
index 36bcae6bc0..df49d0f780 100644
--- a/arch/arm/boards/tqmls1046a/board.c
+++ b/arch/arm/boards/tqmls1046a/board.c
@@ -13,22 +13,38 @@
#include <mach/layerscape/bbu.h>
#include <mach/layerscape/layerscape.h>
-static int tqmls1046a_mem_init(void)
+static void ls1046a_add_memory(void)
{
+ u32 cs0_bnds;
+ unsigned long long memsize, lower, upper;
int ret;
- if (!of_machine_is_compatible("tq,ls1046a-tqmls1046a"))
- return 0;
+ cs0_bnds = in_be32(LS1046A_DDRC_BASE);
+ switch (cs0_bnds) {
+ case 0x1ff:
+ memsize = SZ_8G;
+ break;
+ case 0x7f:
+ memsize = SZ_2G;
+ break;
+ default:
+ pr_err("Unexpected cs0_bnds: 0x%08x\n", cs0_bnds);
+ memsize = SZ_2G;
+ break;
+ }
+
+ lower = min_t(unsigned long long, memsize, SZ_2G);
+ arm_add_mem_device("ram0", 0x80000000, lower);
- arm_add_mem_device("ram0", 0x80000000, SZ_2G);
+ if (memsize > lower) {
+ upper = memsize - lower;
+ arm_add_mem_device("ram1", 0x880000000, upper);
+ }
ret = ls1046a_ppa_init(0x100000000 - SZ_64M, SZ_64M);
if (ret)
pr_err("Failed to initialize PPA firmware: %s\n", strerror(-ret));
-
- return 0;
}
-mem_initcall(tqmls1046a_mem_init);
static int tqmls1046a_postcore_init(void)
{
@@ -39,6 +55,8 @@ static int tqmls1046a_postcore_init(void)
if (!of_machine_is_compatible("tq,ls1046a-tqmls1046a"))
return 0;
+ ls1046a_add_memory();
+
defaultenv_append_directory(defaultenv_tqmls1046a);
/* Configure iomux for i2c4 */
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 6d25b5cda8..9f471d001e 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -13,7 +13,7 @@
#include <mach/layerscape/xload.h>
#include <mach/layerscape/layerscape.h>
-static struct fsl_ddr_controller ddrc[] = {
+static struct fsl_ddr_controller tqmls1046a_ddrc[] = {
{
.memctl_opts.ddrtype = SDRAM_TYPE_DDR4,
.base = IOMEM(LSCH2_DDR_ADDR),
@@ -90,11 +90,222 @@ static struct fsl_ddr_controller ddrc[] = {
},
};
+static struct fsl_ddr_controller tqmls1046a_ddrc_8g[] = {
+ {
+ .memctl_opts.ddrtype = SDRAM_TYPE_DDR4,
+ .base = IOMEM(LSCH2_DDR_ADDR),
+ .ddr_freq = LS1046A_DDR_FREQ,
+ .erratum_A008511 = 1,
+ .erratum_A009803 = 1,
+ .erratum_A010165 = 1,
+ .erratum_A009801 = 1,
+ .erratum_A009942 = 1,
+ .chip_selects_per_ctrl = 4,
+ .fsl_ddr_config_reg = {
+ .cs[0].bnds = 0x000001FF,
+ .cs[0].config = 0x80010422,
+ .cs[0].config_2 = 0x00000000,
+ .cs[1].bnds = 0x00000000,
+ .cs[1].config = 0x00000000,
+ .cs[1].config_2 = 0x00000000,
+ .cs[2].bnds = 0x00000000,
+ .cs[2].config = 0x00000000,
+ .cs[2].config_2 = 0x00000000,
+ .cs[3].bnds = 0x00000000,
+ .cs[3].config = 0x00000000,
+ .cs[3].config_2 = 0x00000000,
+ .timing_cfg_3 = 0x020F1100,
+ .timing_cfg_0 = 0xF7660008,
+ .timing_cfg_1 = 0xF1FCC178,
+ .timing_cfg_2 = 0x00590160,
+ .ddr_sdram_cfg = 0x65000008,
+ .ddr_sdram_cfg_2 = 0x00401150,
+ .ddr_sdram_cfg_3 = 0x40000000,
+ .ddr_sdram_mode = 0x01030631,
+ .ddr_sdram_mode_2 = 0x00100200,
+ .ddr_sdram_mode_3 = 0x00000000,
+ .ddr_sdram_mode_4 = 0x00000000,
+ .ddr_sdram_mode_5 = 0x00000000,
+ .ddr_sdram_mode_6 = 0x00000000,
+ .ddr_sdram_mode_7 = 0x00000000,
+ .ddr_sdram_mode_8 = 0x00000000,
+ .ddr_sdram_mode_9 = 0x00000500,
+ .ddr_sdram_mode_10 = 0x08800000,
+ .ddr_sdram_mode_11 = 0x00000000,
+ .ddr_sdram_mode_12 = 0x00000000,
+ .ddr_sdram_mode_13 = 0x00000000,
+ .ddr_sdram_mode_14 = 0x00000000,
+ .ddr_sdram_mode_15 = 0x00000000,
+ .ddr_sdram_mode_16 = 0x00000000,
+ .ddr_sdram_interval = 0x0F3C079E,
+ .ddr_data_init = 0xDEADBEEF,
+ .ddr_sdram_clk_cntl = 0x03000000,
+ .ddr_init_addr = 0x00000000,
+ .ddr_init_ext_addr = 0x00000000,
+ .timing_cfg_4 = 0x00220002,
+ .timing_cfg_5 = 0x00000000,
+ .timing_cfg_6 = 0x00000000,
+ .timing_cfg_7 = 0x25500000,
+ .timing_cfg_8 = 0x05447A00,
+ .timing_cfg_9 = 0x00000000,
+ .ddr_zq_cntl = 0x8A090705,
+ .ddr_wrlvl_cntl = 0x8605070A,
+ .ddr_wrlvl_cntl_2 = 0x0A080807,
+ .ddr_wrlvl_cntl_3 = 0x0706060A,
+ .ddr_sr_cntr = 0x00000000,
+ .ddr_sdram_rcw_1 = 0x00000000,
+ .ddr_sdram_rcw_2 = 0x00000000,
+ .ddr_sdram_rcw_3 = 0x00000000,
+ .ddr_cdr1 = 0x80080000,
+ .ddr_cdr2 = 0x000000C0,
+ .dq_map_0 = 0x00000000,
+ .dq_map_1 = 0x00000000,
+ .dq_map_2 = 0x00000000,
+ .dq_map_3 = 0x00000000,
+ .debug[28] = 0x00700046,
+ },
+ },
+};
+
+static struct fsl_ddr_controller tqmls1046a_ddrc_8g_ca[] = {
+ {
+ .memctl_opts.ddrtype = SDRAM_TYPE_DDR4,
+ .base = IOMEM(LSCH2_DDR_ADDR),
+ .ddr_freq = LS1046A_DDR_FREQ,
+ .erratum_A008511 = 1,
+ .erratum_A009803 = 1,
+ .erratum_A010165 = 1,
+ .erratum_A009801 = 1,
+ .erratum_A009942 = 1,
+ .chip_selects_per_ctrl = 4,
+ .fsl_ddr_config_reg = {
+ .cs[0].bnds = 0x000001FF,
+ .cs[0].config = 0x80010422,
+ .cs[0].config = 0x80010512,
+ .cs[0].config_2 = 0x00000000,
+ .cs[1].bnds = 0x00000000,
+ .cs[1].config = 0x00000000,
+ .cs[1].config_2 = 0x00000000,
+ .cs[2].bnds = 0x00000000,
+ .cs[2].config = 0x00000000,
+ .cs[2].config_2 = 0x00000000,
+ .cs[3].bnds = 0x00000000,
+ .cs[3].config = 0x00000000,
+ .cs[3].config_2 = 0x00000000,
+ .timing_cfg_3 = 0x12551100,
+ .timing_cfg_0 = 0xA0660008,
+ .timing_cfg_1 = 0x060E6278,
+ .timing_cfg_2 = 0x0058625E,
+ .ddr_sdram_cfg = 0x65200008,
+ .ddr_sdram_cfg_2 = 0x00401070,
+ .ddr_sdram_cfg_3 = 0x40000000,
+ .ddr_sdram_mode = 0x05030635,
+ .ddr_sdram_mode_2 = 0x00100000,
+ .ddr_sdram_mode_3 = 0x00000000,
+ .ddr_sdram_mode_4 = 0x00000000,
+ .ddr_sdram_mode_5 = 0x00000000,
+ .ddr_sdram_mode_6 = 0x00000000,
+ .ddr_sdram_mode_7 = 0x00000000,
+ .ddr_sdram_mode_8 = 0x00000000,
+ .ddr_sdram_mode_9 = 0x00000701,
+ .ddr_sdram_mode_10 = 0x08800000,
+ .ddr_sdram_mode_11 = 0x00000000,
+ .ddr_sdram_mode_12 = 0x00000000,
+ .ddr_sdram_mode_13 = 0x00000000,
+ .ddr_sdram_mode_14 = 0x00000000,
+ .ddr_sdram_mode_15 = 0x00000000,
+ .ddr_sdram_mode_16 = 0x00000000,
+ .ddr_sdram_interval = 0x0F3C079E,
+ .ddr_data_init = 0xDEADBEEF,
+ .ddr_sdram_clk_cntl = 0x02400000,
+ .ddr_init_addr = 0x00000000,
+ .ddr_init_ext_addr = 0x00000000,
+ .timing_cfg_4 = 0x00224502,
+ .timing_cfg_5 = 0x06401400,
+ .timing_cfg_6 = 0x00000000,
+ .timing_cfg_7 = 0x25540000,
+ .timing_cfg_8 = 0x06445A00,
+ .timing_cfg_9 = 0x00000000,
+ .ddr_zq_cntl = 0x8A090705,
+ .ddr_wrlvl_cntl = 0x86750608,
+ .ddr_wrlvl_cntl_2 = 0x07070605,
+ .ddr_wrlvl_cntl_3 = 0x05040407,
+ .ddr_sr_cntr = 0x00000000,
+ .ddr_sdram_rcw_1 = 0x00000000,
+ .ddr_sdram_rcw_2 = 0x00000000,
+ .ddr_sdram_rcw_3 = 0x00000000,
+ .ddr_cdr1 = 0x80080000,
+ .ddr_cdr2 = 0x00000080,
+ .dq_map_0 = 0x06106104,
+ .dq_map_1 = 0x84184184,
+ .dq_map_2 = 0x06106104,
+ .dq_map_3 = 0x84184000,
+ .debug[28] = 0x00700046,
+ },
+ },
+};
+
+#define TQ_VARIANT_LEN 18
+#define TQ_VARIANT_TQMLS1046A_P2 0
+#define TQ_VARIANT_TQMLS1046A_CA 1
+
+static int tqmls1046a_get_variant(void)
+{
+ struct pbl_i2c *i2c;
+ unsigned char buf[TQ_VARIANT_LEN + 1] = { 0 };
+ uint8_t pos = 0x40;
+ int ret;
+ int variant = TQ_VARIANT_TQMLS1046A_P2;
+ struct i2c_msg msg[] = {
+ {
+ .addr = 0x50,
+ .len = 1,
+ .buf = &pos,
+ }, {
+ .addr = 0x50,
+ .len = TQ_VARIANT_LEN,
+ .flags = I2C_M_RD,
+ .buf = (void *)&buf,
+ }
+ };
+
+ i2c = ls1046_i2c_init(IOMEM(LSCH2_I2C1_BASE_ADDR));
+
+ ret = pbl_i2c_xfer(i2c, msg, ARRAY_SIZE(msg));
+ if (ret != ARRAY_SIZE(msg)) {
+ pr_err("I2C EEPROM read failed: %d\n", ret);
+ goto out;
+ }
+
+ if (buf[0] == 0xff) {
+ pr_err("Erased EEPROM detected\n");
+ goto out;
+ }
+
+ pr_debug("Board Variant: %s\n", buf);
+
+ if (!strcmp(buf, "TQMLS1046A-CA.0202")) {
+ variant = TQ_VARIANT_TQMLS1046A_CA;
+ goto out;
+ }
+
+ if (!strcmp(buf, "TQMLS1046A-P2.0201")) {
+ variant = TQ_VARIANT_TQMLS1046A_P2;
+ goto out;
+ }
+
+ pr_err("Unknown board variant, using default\n");
+
+out:
+ return variant;
+}
+
extern char __dtb_z_fsl_ls1046a_tqmls1046a_mbls10xxa_start[];
-static noinline __noreturn void tqmls1046a_r_entry(void)
+static noinline __noreturn void tqmls1046a_r_entry(bool is_8g)
{
unsigned long membase = LS1046A_DDR_SDRAM_BASE;
+ int board_variant = 0;
if (get_pc() >= membase)
barebox_arm_entry(membase, 0x80000000 - SZ_64M,
@@ -108,7 +319,15 @@ static noinline __noreturn void tqmls1046a_r_entry(void)
udelay(500);
putc_ll('>');
- fsl_ddr_set_memctl_regs(&ddrc[0], 0, false);
+ if (is_8g) {
+ board_variant = tqmls1046a_get_variant();
+ if (board_variant == TQ_VARIANT_TQMLS1046A_CA)
+ fsl_ddr_set_memctl_regs(&tqmls1046a_ddrc_8g_ca[0], 0, false);
+ else
+ fsl_ddr_set_memctl_regs(&tqmls1046a_ddrc_8g[0], 0, false);
+ } else {
+ fsl_ddr_set_memctl_regs(&tqmls1046a_ddrc[0], 0, false);
+ }
ls1046a_errata_post_ddr();
@@ -126,5 +345,15 @@ __noreturn void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned lo
relocate_to_current_adr();
setup_c();
- tqmls1046a_r_entry();
+ tqmls1046a_r_entry(false);
+}
+
+void tqmls1046a_8g_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+
+__noreturn void tqmls1046a_8g_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+{
+ relocate_to_current_adr();
+ setup_c();
+
+ tqmls1046a_r_entry(true);
}
diff --git a/arch/arm/boards/tqmls1046a/start.S b/arch/arm/boards/tqmls1046a/start.S
index 12b785af54..84c4626880 100644
--- a/arch/arm/boards/tqmls1046a/start.S
+++ b/arch/arm/boards/tqmls1046a/start.S
@@ -10,3 +10,8 @@ ENTRY_PROC(start_tqmls1046a)
b tqmls1046a_entry
ENTRY_PROC_END(start_tqmls1046a)
+ENTRY_PROC(start_tqmls1046a_8g)
+ mov x3, #STACK_TOP
+ mov sp, x3
+ b tqmls1046a_8g_entry
+ENTRY_PROC_END(start_tqmls1046a_8g)
diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
index 9cb88270d7..cfbe4ca35b 100644
--- a/images/Makefile.layerscape
+++ b/images/Makefile.layerscape
@@ -62,8 +62,20 @@ $(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_pbi.cfg
$(call if_changed,lspbl_spi_image,ls1046a)
+$(obj)/barebox-tqmls1046a-8g-sd.image: $(obj)/start_tqmls1046a_8g.pblb \
+ $(board)/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg \
+ $(board)/tqmls1046a/tqmls1046a_pbi.cfg
+ $(call if_changed,lspbl_image,ls1046a)
+
+$(obj)/barebox-tqmls1046a-8g-qspi.image: $(obj)/start_tqmls1046a_8g.pblb \
+ $(board)/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg \
+ $(board)/tqmls1046a/tqmls1046a_pbi.cfg
+ $(call if_changed,lspbl_spi_image,ls1046a)
+
image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image \
- barebox-tqmls1046a-qspi.image
+ barebox-tqmls1046a-qspi.image \
+ barebox-tqmls1046a-8g-sd.image \
+ barebox-tqmls1046a-8g-qspi.image
pbl-$(CONFIG_MACH_LS1021AIOT) += start_ls1021aiot.pbl
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index bf4a751b92..7f9dc7d8a1 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -7,6 +7,7 @@
#define LS1046A_DDR_SDRAM_BASE 0x80000000
#define LS1046A_DDR_FREQ 2100000000
+#define LS1046A_DDRC_BASE 0x01080000
#define LS1021A_DDR_SDRAM_BASE 0x80000000
#define LS1021A_DDR_FREQ 1600000000
--
2.39.5
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 2/9] ARM: Layerscape: TQMLS1046a: add support for 8GiB variant
2024-10-21 7:21 ` [PATCH 2/9] ARM: Layerscape: TQMLS1046a: add support for 8GiB variant Sascha Hauer
@ 2024-10-21 9:06 ` Ahmad Fatoum
2024-10-21 11:20 ` Sascha Hauer
0 siblings, 1 reply; 21+ messages in thread
From: Ahmad Fatoum @ 2024-10-21 9:06 UTC (permalink / raw)
To: Sascha Hauer, open list:BAREBOX
Hello Sascha,
On 21.10.24 09:21, Sascha Hauer wrote:
> The tqmls1046a also has a 8GiB DDR variant. This patch adds support for
> this variant as an additional image with suffix _8g in the name.
>
> The 8GiB boards use two different types of DDR chips which can be
> distinguished by reading the EEPROM. There is one regular version which
> has the string "TQMLS1046A-P2.0201" is the EEPROM. The other one is
> possibly only used for Arkona and has the string "TQMLS1046A-CA.0202"
> in the EEPROM. There might be other possible strings we are currently
> not aware of, we fall back to the P2 variant in this case.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
[snip]
> -static int tqmls1046a_mem_init(void)
> +static void ls1046a_add_memory(void)
> {
> + u32 cs0_bnds;
> + unsigned long long memsize, lower, upper;
Nitpick: u64
> +ENTRY_PROC(start_tqmls1046a_8g)
> + mov x3, #STACK_TOP
> + mov sp, x3
> + b tqmls1046a_8g_entry
We should be able to migrate these assembly entry points to
use ENTRY_FUNCTION_WITHSTACK.
> +ENTRY_PROC_END(start_tqmls1046a_8g)
> diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
> index 9cb88270d7..cfbe4ca35b 100644
> --- a/images/Makefile.layerscape
> +++ b/images/Makefile.layerscape
> @@ -62,8 +62,20 @@ $(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \
> $(board)/tqmls1046a/tqmls1046a_pbi.cfg
> $(call if_changed,lspbl_spi_image,ls1046a)
>
> +$(obj)/barebox-tqmls1046a-8g-sd.image: $(obj)/start_tqmls1046a_8g.pblb \
> + $(board)/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg \
> + $(board)/tqmls1046a/tqmls1046a_pbi.cfg
There should be a FORCE dependency here, given that if_changed is used.
> + $(call if_changed,lspbl_image,ls1046a)
> +
> +$(obj)/barebox-tqmls1046a-8g-qspi.image: $(obj)/start_tqmls1046a_8g.pblb \
> + $(board)/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg \
> + $(board)/tqmls1046a/tqmls1046a_pbi.cfg
Likewise.
Cheers,
Ahmad
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 2/9] ARM: Layerscape: TQMLS1046a: add support for 8GiB variant
2024-10-21 9:06 ` Ahmad Fatoum
@ 2024-10-21 11:20 ` Sascha Hauer
2024-10-21 11:20 ` Ahmad Fatoum
0 siblings, 1 reply; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 11:20 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: open list:BAREBOX
On Mon, Oct 21, 2024 at 11:06:47AM +0200, Ahmad Fatoum wrote:
> Hello Sascha,
>
> On 21.10.24 09:21, Sascha Hauer wrote:
> > The tqmls1046a also has a 8GiB DDR variant. This patch adds support for
> > this variant as an additional image with suffix _8g in the name.
> >
> > The 8GiB boards use two different types of DDR chips which can be
> > distinguished by reading the EEPROM. There is one regular version which
> > has the string "TQMLS1046A-P2.0201" is the EEPROM. The other one is
> > possibly only used for Arkona and has the string "TQMLS1046A-CA.0202"
> > in the EEPROM. There might be other possible strings we are currently
> > not aware of, we fall back to the P2 variant in this case.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
>
> [snip]
>
> > -static int tqmls1046a_mem_init(void)
> > +static void ls1046a_add_memory(void)
> > {
> > + u32 cs0_bnds;
> > + unsigned long long memsize, lower, upper;
>
> Nitpick: u64
>
> > +ENTRY_PROC(start_tqmls1046a_8g)
> > + mov x3, #STACK_TOP
> > + mov sp, x3
> > + b tqmls1046a_8g_entry
>
> We should be able to migrate these assembly entry points to
> use ENTRY_FUNCTION_WITHSTACK.
We could do here. A few patches further down though when adding TF-A
support the stack address will depend on the exception level which can't
be covered by ENTRY_FUNCTION_WITHSTACK.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 2/9] ARM: Layerscape: TQMLS1046a: add support for 8GiB variant
2024-10-21 11:20 ` Sascha Hauer
@ 2024-10-21 11:20 ` Ahmad Fatoum
0 siblings, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2024-10-21 11:20 UTC (permalink / raw)
To: Sascha Hauer; +Cc: open list:BAREBOX
On 21.10.24 13:20, Sascha Hauer wrote:
> On Mon, Oct 21, 2024 at 11:06:47AM +0200, Ahmad Fatoum wrote:
>> Hello Sascha,
>>
>> On 21.10.24 09:21, Sascha Hauer wrote:
>>> The tqmls1046a also has a 8GiB DDR variant. This patch adds support for
>>> this variant as an additional image with suffix _8g in the name.
>>>
>>> The 8GiB boards use two different types of DDR chips which can be
>>> distinguished by reading the EEPROM. There is one regular version which
>>> has the string "TQMLS1046A-P2.0201" is the EEPROM. The other one is
>>> possibly only used for Arkona and has the string "TQMLS1046A-CA.0202"
>>> in the EEPROM. There might be other possible strings we are currently
>>> not aware of, we fall back to the P2 variant in this case.
>>>
>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>> ---
>>
>> [snip]
>>
>>> -static int tqmls1046a_mem_init(void)
>>> +static void ls1046a_add_memory(void)
>>> {
>>> + u32 cs0_bnds;
>>> + unsigned long long memsize, lower, upper;
>>
>> Nitpick: u64
>>
>>> +ENTRY_PROC(start_tqmls1046a_8g)
>>> + mov x3, #STACK_TOP
>>> + mov sp, x3
>>> + b tqmls1046a_8g_entry
>>
>> We should be able to migrate these assembly entry points to
>> use ENTRY_FUNCTION_WITHSTACK.
>
> We could do here. A few patches further down though when adding TF-A
> support the stack address will depend on the exception level which can't
> be covered by ENTRY_FUNCTION_WITHSTACK.
Alright. never mind then. :-)
Cheers,
Ahmad
>
> Sascha
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 3/9] ARM: Layerscape: ls1046ardb: remove unused variable
2024-10-21 7:21 [PATCH 0/9] ARM: Layerscape: LS1046a: switch to TF-A Sascha Hauer
2024-10-21 7:21 ` [PATCH 1/9] ARM: Layerscape: TQMLS1046a: Update DDR timings Sascha Hauer
2024-10-21 7:21 ` [PATCH 2/9] ARM: Layerscape: TQMLS1046a: add support for 8GiB variant Sascha Hauer
@ 2024-10-21 7:21 ` Sascha Hauer
2024-10-21 7:21 ` [PATCH 4/9] ARM: Layerscape: remove register arguments Sascha Hauer
` (5 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 7:21 UTC (permalink / raw)
To: open list:BAREBOX
memsize is set with the value returned from fsl_ddr_sdram(), then passed
through r0 to the full barebox binary where it is then finally unused.
Just remove the variable. The real memory amount is hardcoded in the
board code anyway.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/ls1046ardb/lowlevel.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c
index c2d3a526bc..9c3f1a8375 100644
--- a/arch/arm/boards/ls1046ardb/lowlevel.c
+++ b/arch/arm/boards/ls1046ardb/lowlevel.c
@@ -184,16 +184,13 @@ static struct fsl_ddr_info ls1046a_info = {
.c = ddrc,
};
-static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize)
+static noinline __noreturn void ls1046ardb_r_entry(void)
{
unsigned long membase = LS1046A_DDR_SDRAM_BASE;
struct pbl_i2c *i2c;
int ret;
if (get_pc() >= membase) {
- if (memsize + membase >= 0x100000000)
- memsize = 0x100000000 - membase;
-
barebox_arm_entry(membase, 0x80000000 - SZ_64M,
__dtb_z_fsl_ls1046a_rdb_start);
}
@@ -209,11 +206,11 @@ static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize)
goto err;
}
- memsize = fsl_ddr_sdram(&ls1046a_info, false);
+ fsl_ddr_sdram(&ls1046a_info, false);
ls1046a_errata_post_ddr();
- ls1046a_esdhc_start_image(memsize, 0, 0);
+ ls1046a_esdhc_start_image(0, 0, 0);
err:
pr_err("Booting failed\n");
@@ -228,5 +225,5 @@ __noreturn void ls1046ardb_entry(unsigned long r0, unsigned long r1, unsigned lo
relocate_to_current_adr();
setup_c();
- ls1046ardb_r_entry(r0);
+ ls1046ardb_r_entry();
}
--
2.39.5
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 4/9] ARM: Layerscape: remove register arguments
2024-10-21 7:21 [PATCH 0/9] ARM: Layerscape: LS1046a: switch to TF-A Sascha Hauer
` (2 preceding siblings ...)
2024-10-21 7:21 ` [PATCH 3/9] ARM: Layerscape: ls1046ardb: remove unused variable Sascha Hauer
@ 2024-10-21 7:21 ` Sascha Hauer
2024-10-21 7:21 ` [PATCH 5/9] ARM: Layerscape: LS1046a: add TF-A support Sascha Hauer
` (4 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 7:21 UTC (permalink / raw)
To: open list:BAREBOX
The various Layerscape xload_start_image functions all take r0, r1 and
r2 arguments. These are all unused in the code, so remove them.
The ls1021aiot board passes the memory size in r0 in one case, but this
is never used, so it's safe to remove that as well.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/ls1021aiot/lowlevel.c | 6 +++---
arch/arm/boards/ls1046ardb/lowlevel.c | 6 +++---
arch/arm/boards/tqmls1046a/lowlevel.c | 10 +++++-----
arch/arm/mach-layerscape/xload-qspi.c | 17 +++++++----------
arch/arm/mach-layerscape/xload.c | 12 +++++-------
drivers/mci/imx-esdhc-pbl.c | 10 ++++------
include/mach/layerscape/xload.h | 14 +++++---------
7 files changed, 32 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boards/ls1021aiot/lowlevel.c b/arch/arm/boards/ls1021aiot/lowlevel.c
index d2d4237c3d..887f0e39db 100644
--- a/arch/arm/boards/ls1021aiot/lowlevel.c
+++ b/arch/arm/boards/ls1021aiot/lowlevel.c
@@ -97,7 +97,7 @@ static noinline __noreturn void ls1021aiot_r_entry(void)
ls1021a_errata_post_ddr();
- ls1021a_xload_start_image(SZ_1G, 0, 0);
+ ls1021a_xload_start_image();
pr_err("Booting failed\n");
@@ -105,10 +105,10 @@ static noinline __noreturn void ls1021aiot_r_entry(void)
;
}
-void ls1021aiot_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+void ls1021aiot_entry(void);
__noreturn void
-ls1021aiot_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+ls1021aiot_entry(void)
{
relocate_to_current_adr();
setup_c();
diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c
index 9c3f1a8375..753fca3272 100644
--- a/arch/arm/boards/ls1046ardb/lowlevel.c
+++ b/arch/arm/boards/ls1046ardb/lowlevel.c
@@ -210,7 +210,7 @@ static noinline __noreturn void ls1046ardb_r_entry(void)
ls1046a_errata_post_ddr();
- ls1046a_esdhc_start_image(0, 0, 0);
+ ls1046a_esdhc_start_image();
err:
pr_err("Booting failed\n");
@@ -218,9 +218,9 @@ static noinline __noreturn void ls1046ardb_r_entry(void)
while (1);
}
-void ls1046ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+void ls1046ardb_entry(void);
-__noreturn void ls1046ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+__noreturn void ls1046ardb_entry(void)
{
relocate_to_current_adr();
setup_c();
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 9f471d001e..6531b22bd1 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -331,16 +331,16 @@ static noinline __noreturn void tqmls1046a_r_entry(bool is_8g)
ls1046a_errata_post_ddr();
- ls1046a_xload_start_image(0, 0, 0);
+ ls1046a_xload_start_image();
pr_err("Booting failed\n");
while (1);
}
-void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+void tqmls1046a_entry(void);
-__noreturn void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+__noreturn void tqmls1046a_entry(void)
{
relocate_to_current_adr();
setup_c();
@@ -348,9 +348,9 @@ __noreturn void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned lo
tqmls1046a_r_entry(false);
}
-void tqmls1046a_8g_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+void tqmls1046a_8g_entry(void);
-__noreturn void tqmls1046a_8g_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+__noreturn void tqmls1046a_8g_entry(void)
{
relocate_to_current_adr();
setup_c();
diff --git a/arch/arm/mach-layerscape/xload-qspi.c b/arch/arm/mach-layerscape/xload-qspi.c
index 608434bf1f..11119840c3 100644
--- a/arch/arm/mach-layerscape/xload-qspi.c
+++ b/arch/arm/mach-layerscape/xload-qspi.c
@@ -19,10 +19,9 @@ struct layerscape_base_addr {
void *qspi_mem_base;
};
-static int layerscape_qspi_start_image(struct layerscape_base_addr *base,
- unsigned long r0, unsigned long r1, unsigned long r2)
+static int layerscape_qspi_start_image(struct layerscape_base_addr *base)
{
- void (*barebox)(unsigned long, unsigned long, unsigned long) = base->membase;
+ void (*barebox)(void) = base->membase;
/* Switch controller into little endian mode */
out_be32(base->qspi_reg_base, 0x000f400c);
@@ -33,15 +32,14 @@ static int layerscape_qspi_start_image(struct layerscape_base_addr *base,
printf("Starting barebox\n");
- barebox(r0, r1, r2);
+ barebox();
printf("failed\n");
return -EIO;
}
-int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2)
+int ls1046a_qspi_start_image(void)
{
struct layerscape_base_addr base;
@@ -49,11 +47,10 @@ int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
base.membase = IOMEM(LS1046A_DDR_SDRAM_BASE);
base.qspi_mem_base = IOMEM(0x40000000);
- return layerscape_qspi_start_image(&base, r0, r1, r2);
+ return layerscape_qspi_start_image(&base);
}
-int ls1021a_qspi_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2)
+int ls1021a_qspi_start_image(void)
{
struct layerscape_base_addr base;
@@ -61,5 +58,5 @@ int ls1021a_qspi_start_image(unsigned long r0, unsigned long r1,
base.membase = IOMEM(LS1021A_DDR_SDRAM_BASE);
base.qspi_mem_base = IOMEM(0x40000000);
- return layerscape_qspi_start_image(&base, r0, r1, r2);
+ return layerscape_qspi_start_image(&base);
}
diff --git a/arch/arm/mach-layerscape/xload.c b/arch/arm/mach-layerscape/xload.c
index 32ff158b1b..9103e8b4bc 100644
--- a/arch/arm/mach-layerscape/xload.c
+++ b/arch/arm/mach-layerscape/xload.c
@@ -5,8 +5,7 @@
#include <mach/layerscape/layerscape.h>
#include <mach/layerscape/xload.h>
-int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2)
+int ls1046a_xload_start_image(void)
{
enum bootsource src;
@@ -14,10 +13,10 @@ int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
switch (src) {
case BOOTSOURCE_SPI_NOR:
- return ls1046a_qspi_start_image(r0, r1, r2);
+ return ls1046a_qspi_start_image();
#if defined(CONFIG_MCI_IMX_ESDHC_PBL)
case BOOTSOURCE_MMC:
- return ls1046a_esdhc_start_image(r0, r1, r2);
+ return ls1046a_esdhc_start_image();
#endif
default:
pr_err("Unknown bootsource\n");
@@ -25,8 +24,7 @@ int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
}
}
-int ls1021a_xload_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2)
+int ls1021a_xload_start_image(void)
{
enum bootsource src;
@@ -34,7 +32,7 @@ int ls1021a_xload_start_image(unsigned long r0, unsigned long r1,
switch (src) {
case BOOTSOURCE_SPI_NOR:
- return ls1021a_qspi_start_image(r0, r1, r2);
+ return ls1021a_qspi_start_image();
default:
pr_err("Unknown bootsource\n");
return -EINVAL;
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index 5b1d9a3cf4..3bf3a7ace6 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -352,7 +352,7 @@ static int layerscape_esdhc_load_image(struct fsl_esdhc_host *host, void *adr, u
* Return: If successful, this function does not return. A negative error
* code is returned when this function fails.
*/
-int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2)
+int ls1046a_esdhc_start_image(void)
{
int ret;
struct esdhc_soc_data data = {
@@ -364,8 +364,7 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
};
void *sdram = (void *)0x80000000;
unsigned long size = ALIGN(barebox_image_size + LS1046A_SD_IMAGE_OFFSET, 512);
- void (*barebox)(unsigned long, unsigned long, unsigned long) =
- (sdram + LS1046A_SD_IMAGE_OFFSET);
+ void (*barebox)(void) = (sdram + LS1046A_SD_IMAGE_OFFSET);
ret = layerscape_esdhc_load_image(&host, sdram, size, (8 << 8) | (3 << 4));
if (ret)
@@ -373,7 +372,7 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
printf("Starting barebox\n");
- barebox(r0, r1, r2);
+ barebox();
return -EINVAL;
}
@@ -393,8 +392,7 @@ static int ls1028a_esdhc_start_image(void __iomem *base, struct dram_regions_inf
void *bl31_image;
struct bl2_to_bl31_params_mem_v2 *params;
unsigned long size = ALIGN(barebox_image_size + LS1046A_SD_IMAGE_OFFSET, 512);
- void (*barebox)(unsigned long, unsigned long, unsigned long) =
- (sdram + LS1046A_SD_IMAGE_OFFSET);
+ void (*barebox)(void) = (sdram + LS1046A_SD_IMAGE_OFFSET);
int ret;
ret = layerscape_esdhc_load_image(&host, sdram, size, 8 << 4);
diff --git a/include/mach/layerscape/xload.h b/include/mach/layerscape/xload.h
index 86327c63e6..64990e2ca1 100644
--- a/include/mach/layerscape/xload.h
+++ b/include/mach/layerscape/xload.h
@@ -5,16 +5,12 @@
struct dram_regions_info;
-int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2);
+int ls1046a_esdhc_start_image(void);
int ls1028a_esdhc1_start_image(struct dram_regions_info *dram_info);
int ls1028a_esdhc2_start_image(struct dram_regions_info *dram_info);
-int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2);
-int ls1021a_qspi_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2);
-int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2);
-int ls1021a_xload_start_image(unsigned long r0, unsigned long r1,
- unsigned long r2);
+int ls1046a_qspi_start_image(void);
+int ls1021a_qspi_start_image(void);
+int ls1046a_xload_start_image(void);
+int ls1021a_xload_start_image(void);
#endif /* __MACH_LAYERSCAPE_XLOAD_H */
--
2.39.5
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 5/9] ARM: Layerscape: LS1046a: add TF-A support
2024-10-21 7:21 [PATCH 0/9] ARM: Layerscape: LS1046a: switch to TF-A Sascha Hauer
` (3 preceding siblings ...)
2024-10-21 7:21 ` [PATCH 4/9] ARM: Layerscape: remove register arguments Sascha Hauer
@ 2024-10-21 7:21 ` Sascha Hauer
2024-10-21 9:12 ` Ahmad Fatoum
2024-10-21 7:21 ` [PATCH 6/9] ARM: Layerscape: LS1046a-rdb: Switch to " Sascha Hauer
` (3 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 7:21 UTC (permalink / raw)
To: open list:BAREBOX
Right now we still use PPA on LS1046a. This has long been deprecated and
replaced with TF-A. Add support for starting the TF-A on LS1046a based
boards as a first step to get rid of PPA.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/ls1046ardb/lowlevel.c | 2 +-
arch/arm/boards/tqmls1046a/lowlevel.c | 2 +-
arch/arm/mach-layerscape/Kconfig | 2 ++
arch/arm/mach-layerscape/Makefile | 1 +
arch/arm/mach-layerscape/tfa.c | 29 +++++++++++++++++++++++++++++
arch/arm/mach-layerscape/xload-qspi.c | 12 ++++++++----
arch/arm/mach-layerscape/xload.c | 6 +++---
drivers/mci/imx-esdhc-pbl.c | 5 ++++-
firmware/Kconfig | 3 +++
firmware/Makefile | 1 +
include/mach/layerscape/xload.h | 8 +++++---
11 files changed, 58 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c
index 753fca3272..bcc95cc59d 100644
--- a/arch/arm/boards/ls1046ardb/lowlevel.c
+++ b/arch/arm/boards/ls1046ardb/lowlevel.c
@@ -210,7 +210,7 @@ static noinline __noreturn void ls1046ardb_r_entry(void)
ls1046a_errata_post_ddr();
- ls1046a_esdhc_start_image();
+ ls1046a_esdhc_start_image(NULL);
err:
pr_err("Booting failed\n");
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 6531b22bd1..5ccafb2d77 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -331,7 +331,7 @@ static noinline __noreturn void tqmls1046a_r_entry(bool is_8g)
ls1046a_errata_post_ddr();
- ls1046a_xload_start_image();
+ ls1046a_xload_start_image(NULL);
pr_err("Booting failed\n");
diff --git a/arch/arm/mach-layerscape/Kconfig b/arch/arm/mach-layerscape/Kconfig
index 5658a63b33..9d15ba0173 100644
--- a/arch/arm/mach-layerscape/Kconfig
+++ b/arch/arm/mach-layerscape/Kconfig
@@ -24,6 +24,7 @@ config ARCH_LS1028
config ARCH_LS1046
bool
select CPU_V8
+ select ARM_ATF
select SYS_SUPPORTS_64BIT_KERNEL
if 64BIT
@@ -47,6 +48,7 @@ config MACH_TQMLS1046A
select MCI_IMX_ESDHC_PBL
select DDR_FSL
select DDR_FSL_DDR4
+ select FIRMWARE_LS1046A_ATF
endif
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index e4bb1b42f2..ee7df5ea19 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -14,3 +14,4 @@ lwl-$(CONFIG_ARCH_LS1021) += lowlevel-ls102xa.o
obj-$(CONFIG_ARCH_LS1021) += restart.o ls102xa_stream_id.o
lwl-$(CONFIG_ARCH_LS1028) += lowlevel-ls1028a.o
+pbl-$(CONFIG_FIRMWARE_LS1046A_ATF) += tfa.o
diff --git a/arch/arm/mach-layerscape/tfa.c b/arch/arm/mach-layerscape/tfa.c
new file mode 100644
index 0000000000..c8a8c8bf1d
--- /dev/null
+++ b/arch/arm/mach-layerscape/tfa.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <firmware.h>
+#include <asm/atf_common.h>
+#include <asm/cache.h>
+#include <mach/layerscape/layerscape.h>
+#include <mach/layerscape/xload.h>
+
+void ls1046_start_tfa(void *barebox, struct dram_regions_info *dram_info)
+{
+ void (*bl31)(void) = (void *)0xfbe00000;
+ size_t bl31_size;
+ void *bl31_image;
+ struct bl2_to_bl31_params_mem_v2 *params;
+
+ get_builtin_firmware_ext(ls1046a_bl31_bin, barebox, &bl31_image, &bl31_size);
+ memcpy(bl31, bl31_image, bl31_size);
+
+ sync_caches_for_execution();
+
+ /* Setup an initial stack for EL2 */
+ asm volatile("msr sp_el2, %0" : : "r" ((unsigned long)barebox - 16) : "cc");
+
+ params = bl2_plat_get_bl31_params_v2(0, (uintptr_t)barebox, 0);
+ params->bl31_ep_info.args.arg3 = (unsigned long)dram_info;
+
+ printf("Starting bl31\n");
+
+ bl31_entry_v2((uintptr_t)bl31, ¶ms->bl_params, NULL);
+}
diff --git a/arch/arm/mach-layerscape/xload-qspi.c b/arch/arm/mach-layerscape/xload-qspi.c
index 11119840c3..fa5b699d4a 100644
--- a/arch/arm/mach-layerscape/xload-qspi.c
+++ b/arch/arm/mach-layerscape/xload-qspi.c
@@ -19,7 +19,8 @@ struct layerscape_base_addr {
void *qspi_mem_base;
};
-static int layerscape_qspi_start_image(struct layerscape_base_addr *base)
+static int layerscape_qspi_start_image(struct layerscape_base_addr *base,
+ struct dram_regions_info *dram_info)
{
void (*barebox)(void) = base->membase;
@@ -28,6 +29,9 @@ static int layerscape_qspi_start_image(struct layerscape_base_addr *base)
memcpy(base->membase, base->qspi_mem_base + BAREBOX_START, barebox_image_size);
+ if (IS_ENABLED(CONFIG_FIRMWARE_LS1046A_ATF))
+ ls1046_start_tfa(base->membase, dram_info);
+
sync_caches_for_execution();
printf("Starting barebox\n");
@@ -39,7 +43,7 @@ static int layerscape_qspi_start_image(struct layerscape_base_addr *base)
return -EIO;
}
-int ls1046a_qspi_start_image(void)
+int ls1046a_qspi_start_image(struct dram_regions_info *dram_info)
{
struct layerscape_base_addr base;
@@ -47,7 +51,7 @@ int ls1046a_qspi_start_image(void)
base.membase = IOMEM(LS1046A_DDR_SDRAM_BASE);
base.qspi_mem_base = IOMEM(0x40000000);
- return layerscape_qspi_start_image(&base);
+ return layerscape_qspi_start_image(&base, dram_info);
}
int ls1021a_qspi_start_image(void)
@@ -58,5 +62,5 @@ int ls1021a_qspi_start_image(void)
base.membase = IOMEM(LS1021A_DDR_SDRAM_BASE);
base.qspi_mem_base = IOMEM(0x40000000);
- return layerscape_qspi_start_image(&base);
+ return layerscape_qspi_start_image(&base, NULL);
}
diff --git a/arch/arm/mach-layerscape/xload.c b/arch/arm/mach-layerscape/xload.c
index 9103e8b4bc..cbdf14344e 100644
--- a/arch/arm/mach-layerscape/xload.c
+++ b/arch/arm/mach-layerscape/xload.c
@@ -5,7 +5,7 @@
#include <mach/layerscape/layerscape.h>
#include <mach/layerscape/xload.h>
-int ls1046a_xload_start_image(void)
+int ls1046a_xload_start_image(struct dram_regions_info *dram_info)
{
enum bootsource src;
@@ -13,10 +13,10 @@ int ls1046a_xload_start_image(void)
switch (src) {
case BOOTSOURCE_SPI_NOR:
- return ls1046a_qspi_start_image();
+ return ls1046a_qspi_start_image(dram_info);
#if defined(CONFIG_MCI_IMX_ESDHC_PBL)
case BOOTSOURCE_MMC:
- return ls1046a_esdhc_start_image();
+ return ls1046a_esdhc_start_image(dram_info);
#endif
default:
pr_err("Unknown bootsource\n");
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index 3bf3a7ace6..0e4b6114fd 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -352,7 +352,7 @@ static int layerscape_esdhc_load_image(struct fsl_esdhc_host *host, void *adr, u
* Return: If successful, this function does not return. A negative error
* code is returned when this function fails.
*/
-int ls1046a_esdhc_start_image(void)
+int ls1046a_esdhc_start_image(struct dram_regions_info *dram_info)
{
int ret;
struct esdhc_soc_data data = {
@@ -370,6 +370,9 @@ int ls1046a_esdhc_start_image(void)
if (ret)
return ret;
+ if (IS_ENABLED(CONFIG_FIRMWARE_LS1046A_ATF))
+ ls1046_start_tfa(barebox, dram_info);
+
printf("Starting barebox\n");
barebox();
diff --git a/firmware/Kconfig b/firmware/Kconfig
index ae7bbdc71e..d068e6d983 100644
--- a/firmware/Kconfig
+++ b/firmware/Kconfig
@@ -98,4 +98,7 @@ config FIRMWARE_CCBV2_OPTEE
config FIRMWARE_LS1028A_ATF
bool
+config FIRMWARE_LS1046A_ATF
+ bool
+
endmenu
diff --git a/firmware/Makefile b/firmware/Makefile
index 7265c55c42..9351e24e86 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -33,6 +33,7 @@ firmware-$(CONFIG_DRIVER_NET_FSL_FMAN) += fsl_fman_ucode_ls1046_r1.0_106_4_18.bi
firmware-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa-ls1046a.bin
fw-external-$(CONFIG_FIRMWARE_LS1028A_ATF) += ls1028a-bl31.bin
+fw-external-$(CONFIG_FIRMWARE_LS1046A_ATF) += ls1046a-bl31.bin
pbl-firmware-$(CONFIG_FIRMWARE_CCBV2_OPTEE) += ccbv2_optee.bin
pbl-firmware-$(CONFIG_FIRMWARE_TQMA6UL_OPTEE) += mba6ul_optee.bin
diff --git a/include/mach/layerscape/xload.h b/include/mach/layerscape/xload.h
index 64990e2ca1..74f095d789 100644
--- a/include/mach/layerscape/xload.h
+++ b/include/mach/layerscape/xload.h
@@ -5,12 +5,14 @@
struct dram_regions_info;
-int ls1046a_esdhc_start_image(void);
+int ls1046a_esdhc_start_image(struct dram_regions_info *dram_info);
int ls1028a_esdhc1_start_image(struct dram_regions_info *dram_info);
int ls1028a_esdhc2_start_image(struct dram_regions_info *dram_info);
-int ls1046a_qspi_start_image(void);
+int ls1046a_qspi_start_image(struct dram_regions_info *dram_info);
int ls1021a_qspi_start_image(void);
-int ls1046a_xload_start_image(void);
+int ls1046a_xload_start_image(struct dram_regions_info *dram_info);
int ls1021a_xload_start_image(void);
+void ls1046_start_tfa(void *barebox, struct dram_regions_info *dram_info);
+
#endif /* __MACH_LAYERSCAPE_XLOAD_H */
--
2.39.5
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 5/9] ARM: Layerscape: LS1046a: add TF-A support
2024-10-21 7:21 ` [PATCH 5/9] ARM: Layerscape: LS1046a: add TF-A support Sascha Hauer
@ 2024-10-21 9:12 ` Ahmad Fatoum
0 siblings, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2024-10-21 9:12 UTC (permalink / raw)
To: Sascha Hauer, open list:BAREBOX
Hello Sascha,
On 21.10.24 09:21, Sascha Hauer wrote:
> Right now we still use PPA on LS1046a. This has long been deprecated and
> replaced with TF-A. Add support for starting the TF-A on LS1046a based
> boards as a first step to get rid of PPA.
> +void ls1046_start_tfa(void *barebox, struct dram_regions_info *dram_info)
> +{
> + void (*bl31)(void) = (void *)0xfbe00000;
> + size_t bl31_size;
> + void *bl31_image;
> + struct bl2_to_bl31_params_mem_v2 *params;
> +
> + get_builtin_firmware_ext(ls1046a_bl31_bin, barebox, &bl31_image, &bl31_size);
> + memcpy(bl31, bl31_image, bl31_size);
> +
> + sync_caches_for_execution();
> +
> + /* Setup an initial stack for EL2 */
> + asm volatile("msr sp_el2, %0" : : "r" ((unsigned long)barebox - 16) : "cc");
The - 16 shouldn't be necessary, see commit 6b3dc4abd884 ("ARM: Cleanup stack offset
cargo cult").
> +
> + params = bl2_plat_get_bl31_params_v2(0, (uintptr_t)barebox, 0);
> + params->bl31_ep_info.args.arg3 = (unsigned long)dram_info;
> +
> + printf("Starting bl31\n");
Make it a pr_debug?
> diff --git a/firmware/Makefile b/firmware/Makefile
> index 7265c55c42..9351e24e86 100644
> --- a/firmware/Makefile
> +++ b/firmware/Makefile
> @@ -33,6 +33,7 @@ firmware-$(CONFIG_DRIVER_NET_FSL_FMAN) += fsl_fman_ucode_ls1046_r1.0_106_4_18.bi
>
> firmware-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa-ls1046a.bin
> fw-external-$(CONFIG_FIRMWARE_LS1028A_ATF) += ls1028a-bl31.bin
> +fw-external-$(CONFIG_FIRMWARE_LS1046A_ATF) += ls1046a-bl31.bin
This should be added to test/generate-dummy-fw.sh.
Documentation also needs to be updated.
Cheers,
Ahmad
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 6/9] ARM: Layerscape: LS1046a-rdb: Switch to TF-A support
2024-10-21 7:21 [PATCH 0/9] ARM: Layerscape: LS1046a: switch to TF-A Sascha Hauer
` (4 preceding siblings ...)
2024-10-21 7:21 ` [PATCH 5/9] ARM: Layerscape: LS1046a: add TF-A support Sascha Hauer
@ 2024-10-21 7:21 ` Sascha Hauer
2024-10-21 7:21 ` [PATCH 7/9] ARM: Layerscape: TQMLS1046a: " Sascha Hauer
` (2 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 7:21 UTC (permalink / raw)
To: open list:BAREBOX
Now that we can start TF-A on LS1046a based boards switch the LS1046ardb
over to use this rather than deprecated PPA.
Unlike the PPA the TF-A needs information about the amount of SDRAM
installed on the board. The LS1046a-rdb has a DDR4 DIMM connector, so
the SDRAM configuration must be runtime detected. The board support has
8GiB hardcoded in other places, so hardcode 8GiB for TF-A as well.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/ls1046ardb/board.c | 6 ------
arch/arm/boards/ls1046ardb/lowlevel.c | 16 +++++++++++++++-
arch/arm/boards/ls1046ardb/start.S | 14 +++++++++++++-
3 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c
index ee70171ca3..507fb0bfe1 100644
--- a/arch/arm/boards/ls1046ardb/board.c
+++ b/arch/arm/boards/ls1046ardb/board.c
@@ -133,18 +133,12 @@ late_initcall(rdb_late_init);
static int rdb_mem_init(void)
{
- int ret;
-
if (!of_machine_is_compatible("fsl,ls1046a-rdb"))
return 0;
arm_add_mem_device("ram0", 0x80000000, 0x80000000);
arm_add_mem_device("ram1", 0x880000000, 3ULL * SZ_2G);
- ret = ls1046a_ppa_init(0x100000000 - SZ_64M, SZ_64M);
- if (ret)
- pr_err("Failed to initialize PPA firmware: %s\n", strerror(-ret));
-
return 0;
}
mem_initcall(rdb_mem_init);
diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c
index bcc95cc59d..7965e84a34 100644
--- a/arch/arm/boards/ls1046ardb/lowlevel.c
+++ b/arch/arm/boards/ls1046ardb/lowlevel.c
@@ -184,6 +184,20 @@ static struct fsl_ddr_info ls1046a_info = {
.c = ddrc,
};
+static struct dram_regions_info dram_info = {
+ .num_dram_regions = 2,
+ .total_dram_size = SZ_8G,
+ .region = {
+ {
+ .addr = SZ_2G,
+ .size = SZ_2G,
+ }, {
+ .addr = SZ_32G + SZ_2G,
+ .size = SZ_4G + SZ_2G,
+ },
+ },
+};
+
static noinline __noreturn void ls1046ardb_r_entry(void)
{
unsigned long membase = LS1046A_DDR_SDRAM_BASE;
@@ -210,7 +224,7 @@ static noinline __noreturn void ls1046ardb_r_entry(void)
ls1046a_errata_post_ddr();
- ls1046a_esdhc_start_image(NULL);
+ ls1046a_esdhc_start_image(&dram_info);
err:
pr_err("Booting failed\n");
diff --git a/arch/arm/boards/ls1046ardb/start.S b/arch/arm/boards/ls1046ardb/start.S
index 466782b278..571fa78163 100644
--- a/arch/arm/boards/ls1046ardb/start.S
+++ b/arch/arm/boards/ls1046ardb/start.S
@@ -1,11 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <linux/linkage.h>
#include <asm/barebox-arm64.h>
+#include <asm/assembler64.h>
-#define STACK_TOP 0x10020000
+/*
+ * OCRAM is occupied by TF-A, so in EL2 and EL1 use a temporary stack in SDRAM
+ */
+#define STACK_TOP 0x10020000
+#define STACK_TOP_TMP_SDRAM 0x90000000
ENTRY_PROC(start_ls1046ardb)
+ switch_el x3, 3f, 2f, 1f
+3:
mov x3, #STACK_TOP
mov sp, x3
b ls1046ardb_entry
+2:
+1:
+ mov x3, STACK_TOP_TMP_SDRAM
+ mov sp, x3
+ b ls1046ardb_entry
ENTRY_PROC_END(start_ls1046ardb)
--
2.39.5
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 7/9] ARM: Layerscape: TQMLS1046a: Switch to TF-A support
2024-10-21 7:21 [PATCH 0/9] ARM: Layerscape: LS1046a: switch to TF-A Sascha Hauer
` (5 preceding siblings ...)
2024-10-21 7:21 ` [PATCH 6/9] ARM: Layerscape: LS1046a-rdb: Switch to " Sascha Hauer
@ 2024-10-21 7:21 ` Sascha Hauer
2024-10-21 7:21 ` [PATCH 8/9] ARM: Layerscape: LS1046a: remove PPA support Sascha Hauer
2024-10-21 7:21 ` [PATCH 9/9] ARM: Layerscape: LS1046a: add PSCI node Sascha Hauer
8 siblings, 0 replies; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 7:21 UTC (permalink / raw)
To: open list:BAREBOX
Now that we can start TF-A on LS1046a based boards switch the TQMLS1046a
over to use this rather than deprecated PPA.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/tqmls1046a/board.c | 8 ++++----
arch/arm/boards/tqmls1046a/lowlevel.c | 32 ++++++++++++++++++++++++++++++--
arch/arm/boards/tqmls1046a/start.S | 14 +++++++++++++-
3 files changed, 47 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c
index df49d0f780..99344e6e95 100644
--- a/arch/arm/boards/tqmls1046a/board.c
+++ b/arch/arm/boards/tqmls1046a/board.c
@@ -15,9 +15,9 @@
static void ls1046a_add_memory(void)
{
+ struct resource *res;
u32 cs0_bnds;
unsigned long long memsize, lower, upper;
- int ret;
cs0_bnds = in_be32(LS1046A_DDRC_BASE);
switch (cs0_bnds) {
@@ -41,9 +41,9 @@ static void ls1046a_add_memory(void)
arm_add_mem_device("ram1", 0x880000000, upper);
}
- ret = ls1046a_ppa_init(0x100000000 - SZ_64M, SZ_64M);
- if (ret)
- pr_err("Failed to initialize PPA firmware: %s\n", strerror(-ret));
+ res = reserve_sdram_region("tfa", 0xfbe00000, 0x4200000);
+
+ of_register_fixup(of_fixup_reserved_memory, res);
}
static int tqmls1046a_postcore_init(void)
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 5ccafb2d77..e139fe19a1 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -300,15 +300,41 @@ static int tqmls1046a_get_variant(void)
return variant;
}
+static struct dram_regions_info dram_info_2g = {
+ .num_dram_regions = 1,
+ .total_dram_size = SZ_2G,
+ .region = {
+ {
+ .addr = SZ_2G,
+ .size = SZ_2G,
+ },
+ },
+};
+
+static struct dram_regions_info dram_info_8g = {
+ .num_dram_regions = 2,
+ .total_dram_size = SZ_8G,
+ .region = {
+ {
+ .addr = SZ_2G,
+ .size = SZ_2G,
+ }, {
+ .addr = SZ_32G + SZ_2G,
+ .size = SZ_4G + SZ_2G,
+ },
+ },
+};
+
extern char __dtb_z_fsl_ls1046a_tqmls1046a_mbls10xxa_start[];
static noinline __noreturn void tqmls1046a_r_entry(bool is_8g)
{
unsigned long membase = LS1046A_DDR_SDRAM_BASE;
int board_variant = 0;
+ struct dram_regions_info *dram_info;
if (get_pc() >= membase)
- barebox_arm_entry(membase, 0x80000000 - SZ_64M,
+ barebox_arm_entry(membase, 0x80000000 - SZ_128M,
__dtb_z_fsl_ls1046a_tqmls1046a_mbls10xxa_start);
arm_cpu_lowlevel_init();
@@ -321,17 +347,19 @@ static noinline __noreturn void tqmls1046a_r_entry(bool is_8g)
if (is_8g) {
board_variant = tqmls1046a_get_variant();
+ dram_info = &dram_info_8g;
if (board_variant == TQ_VARIANT_TQMLS1046A_CA)
fsl_ddr_set_memctl_regs(&tqmls1046a_ddrc_8g_ca[0], 0, false);
else
fsl_ddr_set_memctl_regs(&tqmls1046a_ddrc_8g[0], 0, false);
} else {
+ dram_info = &dram_info_2g;
fsl_ddr_set_memctl_regs(&tqmls1046a_ddrc[0], 0, false);
}
ls1046a_errata_post_ddr();
- ls1046a_xload_start_image(NULL);
+ ls1046a_xload_start_image(dram_info);
pr_err("Booting failed\n");
diff --git a/arch/arm/boards/tqmls1046a/start.S b/arch/arm/boards/tqmls1046a/start.S
index 84c4626880..c812a35768 100644
--- a/arch/arm/boards/tqmls1046a/start.S
+++ b/arch/arm/boards/tqmls1046a/start.S
@@ -1,8 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <linux/linkage.h>
#include <asm/barebox-arm64.h>
+#include <asm/assembler64.h>
-#define STACK_TOP 0x10020000
+/*
+ * OCRAM is occupied by TF-A, so in EL2 and EL1 use a temporary stack in SDRAM
+ */
+#define STACK_TOP 0x10020000
+#define STACK_TOP_TMP_SDRAM 0x90000000
ENTRY_PROC(start_tqmls1046a)
mov x3, #STACK_TOP
@@ -11,7 +16,14 @@ ENTRY_PROC(start_tqmls1046a)
ENTRY_PROC_END(start_tqmls1046a)
ENTRY_PROC(start_tqmls1046a_8g)
+ switch_el x3, 3f, 2f, 1f
+3:
mov x3, #STACK_TOP
mov sp, x3
b tqmls1046a_8g_entry
+2:
+1:
+ mov x3, STACK_TOP_TMP_SDRAM
+ mov sp, x3
+ b tqmls1046a_8g_entry
ENTRY_PROC_END(start_tqmls1046a_8g)
--
2.39.5
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 8/9] ARM: Layerscape: LS1046a: remove PPA support
2024-10-21 7:21 [PATCH 0/9] ARM: Layerscape: LS1046a: switch to TF-A Sascha Hauer
` (6 preceding siblings ...)
2024-10-21 7:21 ` [PATCH 7/9] ARM: Layerscape: TQMLS1046a: " Sascha Hauer
@ 2024-10-21 7:21 ` Sascha Hauer
2024-10-21 8:55 ` Ahmad Fatoum
2024-10-21 7:21 ` [PATCH 9/9] ARM: Layerscape: LS1046a: add PSCI node Sascha Hauer
8 siblings, 1 reply; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 7:21 UTC (permalink / raw)
To: open list:BAREBOX
Both LS1046a boards supported by barebox have been switched to TF-A, so
drop no longer used PPA support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-layerscape/Kconfig | 12 ---
arch/arm/mach-layerscape/Makefile | 1 -
arch/arm/mach-layerscape/ppa-entry.S | 32 --------
arch/arm/mach-layerscape/ppa.c | 147 -----------------------------------
firmware/Makefile | 1 -
include/mach/layerscape/layerscape.h | 10 ---
6 files changed, 203 deletions(-)
diff --git a/arch/arm/mach-layerscape/Kconfig b/arch/arm/mach-layerscape/Kconfig
index 9d15ba0173..415ee93b99 100644
--- a/arch/arm/mach-layerscape/Kconfig
+++ b/arch/arm/mach-layerscape/Kconfig
@@ -2,18 +2,6 @@
if ARCH_LAYERSCAPE
-config ARCH_LAYERSCAPE_PPA
- bool "Include PPA firmware"
- select ARM_PSCI_OF
- select ARM_SMCCC
- select FITIMAGE
- help
- The "Primary Protected Application" (PPA) is a PSCI compliant firmware
- distributed by NXP. It is needed to start the secondary cores on
- Layerscape SoCs. Without it Linux will be started in EL3 and doesn't
- work properly. The precompiled firmware images can be found here:
- https://github.com/NXP/qoriq-ppa-binary
-
config ARCH_LS1028
bool
select CPU_V8
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index ee7df5ea19..10e1c031b9 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_ARCH_LS1046) += icid.o
obj-pbl-y += boot.o soc.o
pbl-y += xload-qspi.o xload.o
pbl-$(CONFIG_ARCH_LS1028) += tzc400.o
-obj-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa.o ppa-entry.o
obj-$(CONFIG_BOOTM) += pblimage.o
lwl-$(CONFIG_ARCH_LS1021) += lowlevel-ls102xa.o
diff --git a/arch/arm/mach-layerscape/ppa-entry.S b/arch/arm/mach-layerscape/ppa-entry.S
deleted file mode 100644
index f5f30b6719..0000000000
--- a/arch/arm/mach-layerscape/ppa-entry.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <linux/linkage.h>
-
-.section .text.ppa_entry
-ENTRY(ppa_entry)
- /*
- * x0: Secure Firmware entry point
- * x1: Exception return address Low
- * x2: Exception return address High
- */
-
- /* Save stack pointer for EL2 */
- mov x3, sp
- msr sp_el2, x3
-
- /* Set exception return address hold pointer */
- adr x4, 1f
- mov x3, x4
- rev w3, w3
- str w3, [x1]
- lsr x3, x4, #32
- rev w3, w3
- str w3, [x2]
-
- /* Call SEC monitor */
- br x0
-
-1:
- mov x0, #0
- ret
-ENDPROC(ppa_entry)
diff --git a/arch/arm/mach-layerscape/ppa.c b/arch/arm/mach-layerscape/ppa.c
deleted file mode 100644
index 99b76b4c30..0000000000
--- a/arch/arm/mach-layerscape/ppa.c
+++ /dev/null
@@ -1,147 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#define pr_fmt(fmt) "ppa: " fmt
-
-#include <common.h>
-#include <init.h>
-#include <mmu.h>
-#include <firmware.h>
-#include <memory.h>
-#include <linux/sizes.h>
-#include <linux/arm-smccc.h>
-#include <asm/mmu.h>
-#include <soc/fsl/immap_lsch2.h>
-#include <asm/system.h>
-#include <image-fit.h>
-#include <asm/psci.h>
-#include <mach/layerscape/layerscape.h>
-#include <asm/cache.h>
-
-int ppa_entry(const void *, u32 *, u32 *);
-
-#define SEC_JR3_OFFSET 0x40000
-
-static int of_psci_do_fixup(struct device_node *root, void *unused)
-{
- unsigned long psci_version;
- struct device_node *np;
- struct arm_smccc_res res = {};
-
- arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
- psci_version = res.a0;
-
- for_each_compatible_node_from(np, root, NULL, "fsl,sec-v4.0-job-ring") {
- const void *reg;
- int na = of_n_addr_cells(np);
- u64 offset;
-
- reg = of_get_property(np, "reg", NULL);
- if (!reg)
- continue;
-
- offset = of_read_number(reg, na);
- if (offset != SEC_JR3_OFFSET)
- continue;
-
- of_delete_node(np);
- break;
- }
-
- return of_psci_fixup(root, psci_version, "smc");
-}
-
-static int ppa_init(void *ppa, size_t ppa_size, void *sec_firmware_addr)
-{
- int ret;
- u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
- struct ccsr_scfg __iomem *scfg = (void *)(LSCH2_SCFG_ADDR);
- struct fit_handle *fit;
- void *conf;
- const void *buf;
- unsigned long firmware_size;
-
- boot_loc_ptr_l = &scfg->scratchrw[1];
- boot_loc_ptr_h = &scfg->scratchrw[0];
-
- fit = fit_open_buf(ppa, ppa_size, false, BOOTM_VERIFY_AVAILABLE);
- if (IS_ERR(fit)) {
- pr_err("Cannot open ppa FIT image: %pe\n", fit);
- return PTR_ERR(fit);
- }
-
- conf = fit_open_configuration(fit, NULL);
- if (IS_ERR(conf)) {
- pr_err("Cannot open default config in ppa FIT image: %pe\n", conf);
- ret = PTR_ERR(conf);
- goto err;
- }
-
-
- ret = fit_open_image(fit, conf, "firmware", &buf, &firmware_size);
- if (ret) {
- pr_err("Cannot open firmware image in ppa FIT image: %s\n",
- strerror(-ret));
- goto err;
- }
-
- /* Copy the secure firmware to secure memory */
- memcpy(sec_firmware_addr, buf, firmware_size);
- sync_caches_for_execution();
-
- ret = ppa_entry(sec_firmware_addr, boot_loc_ptr_l, boot_loc_ptr_h);
- if (ret) {
- pr_err("Couldn't install PPA firmware: %s\n", strerror(-ret));
- goto err;
- }
-
- pr_info("PPA firmware installed at 0x%p, now in EL%d\n",
- sec_firmware_addr, current_el());
-
- of_register_fixup(of_psci_do_fixup, NULL);
-err:
- fit_close(fit);
-
- return ret;
-}
-
-int ls1046a_ppa_init(resource_size_t ppa_start, resource_size_t ppa_size)
-{
- resource_size_t ppa_end = ppa_start + ppa_size - 1;
- struct resource *res;
- void *ppa_fw;
- size_t ppa_fw_size;
- int el = current_el();
- int ret;
-
- res = reserve_sdram_region("ppa", ppa_start, ppa_size);
- if (!res) {
- pr_err("Cannot request SDRAM region %pa - %pa\n",
- &ppa_start, &ppa_end);
- return -EINVAL;
- }
-
- get_builtin_firmware(ppa_ls1046a_bin, &ppa_fw, &ppa_fw_size);
- if (!ppa_fw_size) {
- pr_err("PPA Firmware was not included in build\n");
- return -ENOSYS;
- }
-
- if (el == 3) {
- unsigned long cr;
-
- asm volatile("mrs %0, sctlr_el3" : "=r" (cr) : : "cc");
- remap_range((void *)ppa_start, ppa_size, MAP_CACHED);
-
- ret = ppa_init(ppa_fw, ppa_fw_size, (void *)ppa_start);
-
- asm volatile("msr sctlr_el2, %0" : : "r" (cr) : "cc");
- remap_range((void *)ppa_start, ppa_size, MAP_UNCACHED);
-
- if (ret)
- return ret;
- }
-
- of_register_fixup(of_fixup_reserved_memory, res);
-
- return 0;
-}
diff --git a/firmware/Makefile b/firmware/Makefile
index 9351e24e86..fd63de1c55 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -31,7 +31,6 @@ pbl-firmware-$(CONFIG_ARCH_RK3399) += rk3399-bl31.bin
pbl-firmware-$(CONFIG_ARCH_RK3399_OPTEE) += rk3399-op-tee.bin
firmware-$(CONFIG_DRIVER_NET_FSL_FMAN) += fsl_fman_ucode_ls1046_r1.0_106_4_18.bin
-firmware-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa-ls1046a.bin
fw-external-$(CONFIG_FIRMWARE_LS1028A_ATF) += ls1028a-bl31.bin
fw-external-$(CONFIG_FIRMWARE_LS1046A_ATF) += ls1046a-bl31.bin
diff --git a/include/mach/layerscape/layerscape.h b/include/mach/layerscape/layerscape.h
index 7f9dc7d8a1..ab8304ede0 100644
--- a/include/mach/layerscape/layerscape.h
+++ b/include/mach/layerscape/layerscape.h
@@ -32,16 +32,6 @@ enum bootsource ls1021a_bootsource_get(void);
#define LAYERSCAPE_SOC_LS1028A 1028
#define LAYERSCAPE_SOC_LS1046A 1046
-#ifdef CONFIG_ARCH_LAYERSCAPE_PPA
-int ls1046a_ppa_init(resource_size_t ppa_start, resource_size_t ppa_size);
-#else
-static inline int ls1046a_ppa_init(resource_size_t ppa_start,
- resource_size_t ppa_size)
-{
- return -ENOSYS;
-}
-#endif
-
struct dram_region_info {
uint64_t addr;
uint64_t size;
--
2.39.5
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 8/9] ARM: Layerscape: LS1046a: remove PPA support
2024-10-21 7:21 ` [PATCH 8/9] ARM: Layerscape: LS1046a: remove PPA support Sascha Hauer
@ 2024-10-21 8:55 ` Ahmad Fatoum
2024-10-21 14:18 ` Sascha Hauer
0 siblings, 1 reply; 21+ messages in thread
From: Ahmad Fatoum @ 2024-10-21 8:55 UTC (permalink / raw)
To: Sascha Hauer, open list:BAREBOX
Hello Sascha,
On 21.10.24 09:21, Sascha Hauer wrote:
> Both LS1046a boards supported by barebox have been switched to TF-A, so
> drop no longer used PPA support.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/mach-layerscape/Kconfig | 12 ---
> arch/arm/mach-layerscape/Makefile | 1 -
> arch/arm/mach-layerscape/ppa-entry.S | 32 --------
> arch/arm/mach-layerscape/ppa.c | 147 -----------------------------------
> firmware/Makefile | 1 -
> include/mach/layerscape/layerscape.h | 10 ---
generate-dummy-fw.sh still has a firmware/ppa-ls1046a.bin
reference.
> -static int of_psci_do_fixup(struct device_node *root, void *unused)
> -{
> - unsigned long psci_version;
> - struct device_node *np;
> - struct arm_smccc_res res = {};
> -
> - arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
> - psci_version = res.a0;
> -
> - for_each_compatible_node_from(np, root, NULL, "fsl,sec-v4.0-job-ring") {
The TF-A doesn't expect one of the job rings to be for its own use?
Cheers,
Ahmad
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 8/9] ARM: Layerscape: LS1046a: remove PPA support
2024-10-21 8:55 ` Ahmad Fatoum
@ 2024-10-21 14:18 ` Sascha Hauer
2024-10-22 7:46 ` Sascha Hauer
0 siblings, 1 reply; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 14:18 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: open list:BAREBOX
On Mon, Oct 21, 2024 at 10:55:45AM +0200, Ahmad Fatoum wrote:
> Hello Sascha,
>
> On 21.10.24 09:21, Sascha Hauer wrote:
> > Both LS1046a boards supported by barebox have been switched to TF-A, so
> > drop no longer used PPA support.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/mach-layerscape/Kconfig | 12 ---
> > arch/arm/mach-layerscape/Makefile | 1 -
> > arch/arm/mach-layerscape/ppa-entry.S | 32 --------
> > arch/arm/mach-layerscape/ppa.c | 147 -----------------------------------
> > firmware/Makefile | 1 -
> > include/mach/layerscape/layerscape.h | 10 ---
>
> generate-dummy-fw.sh still has a firmware/ppa-ls1046a.bin
> reference.
>
> > -static int of_psci_do_fixup(struct device_node *root, void *unused)
> > -{
> > - unsigned long psci_version;
> > - struct device_node *np;
> > - struct arm_smccc_res res = {};
> > -
> > - arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
> > - psci_version = res.a0;
> > -
> > - for_each_compatible_node_from(np, root, NULL, "fsl,sec-v4.0-job-ring") {
>
> The TF-A doesn't expect one of the job rings to be for its own use?
Good question. It looks like U-Boot still has this fixup code eventhough
they have converted to TF-A.
I wonder what the effects are when we don't apply this quirk. At least
starting a kernel with PPA and without this quirk doesn't cause any
problems.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 8/9] ARM: Layerscape: LS1046a: remove PPA support
2024-10-21 14:18 ` Sascha Hauer
@ 2024-10-22 7:46 ` Sascha Hauer
0 siblings, 0 replies; 21+ messages in thread
From: Sascha Hauer @ 2024-10-22 7:46 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: open list:BAREBOX
On Mon, Oct 21, 2024 at 04:18:01PM +0200, Sascha Hauer wrote:
> On Mon, Oct 21, 2024 at 10:55:45AM +0200, Ahmad Fatoum wrote:
> > Hello Sascha,
> >
> > On 21.10.24 09:21, Sascha Hauer wrote:
> > > Both LS1046a boards supported by barebox have been switched to TF-A, so
> > > drop no longer used PPA support.
> > >
> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > ---
> > > arch/arm/mach-layerscape/Kconfig | 12 ---
> > > arch/arm/mach-layerscape/Makefile | 1 -
> > > arch/arm/mach-layerscape/ppa-entry.S | 32 --------
> > > arch/arm/mach-layerscape/ppa.c | 147 -----------------------------------
> > > firmware/Makefile | 1 -
> > > include/mach/layerscape/layerscape.h | 10 ---
> >
> > generate-dummy-fw.sh still has a firmware/ppa-ls1046a.bin
> > reference.
> >
> > > -static int of_psci_do_fixup(struct device_node *root, void *unused)
> > > -{
> > > - unsigned long psci_version;
> > > - struct device_node *np;
> > > - struct arm_smccc_res res = {};
> > > -
> > > - arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
> > > - psci_version = res.a0;
> > > -
> > > - for_each_compatible_node_from(np, root, NULL, "fsl,sec-v4.0-job-ring") {
> >
> > The TF-A doesn't expect one of the job rings to be for its own use?
>
> Good question. It looks like U-Boot still has this fixup code eventhough
> they have converted to TF-A.
>
> I wonder what the effects are when we don't apply this quirk. At least
> starting a kernel with PPA and without this quirk doesn't cause any
> problems.
Looking at the TF-A code the CAAM JR3 indeed seems to be used, at least
under certain circumstances, so I'll put the code to disable JR3 in the
kernel back in.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 9/9] ARM: Layerscape: LS1046a: add PSCI node
2024-10-21 7:21 [PATCH 0/9] ARM: Layerscape: LS1046a: switch to TF-A Sascha Hauer
` (7 preceding siblings ...)
2024-10-21 7:21 ` [PATCH 8/9] ARM: Layerscape: LS1046a: remove PPA support Sascha Hauer
@ 2024-10-21 7:21 ` Sascha Hauer
2024-10-21 7:33 ` Ahmad Fatoum
2024-10-21 8:03 ` Ahmad Fatoum
8 siblings, 2 replies; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 7:21 UTC (permalink / raw)
To: open list:BAREBOX
Unlike other SoCs the LS1046a upstream dtsi files do not have a PSCI
node. Add one for barebox and Linux to find the PSCI support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/fsl-ls1046a.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index a661cb0c89..2dc24ba8c7 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -4,4 +4,9 @@ / {
aliases {
mmc0 = &esdhc;
};
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
};
--
2.39.5
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 9/9] ARM: Layerscape: LS1046a: add PSCI node
2024-10-21 7:21 ` [PATCH 9/9] ARM: Layerscape: LS1046a: add PSCI node Sascha Hauer
@ 2024-10-21 7:33 ` Ahmad Fatoum
2024-10-21 7:57 ` Sascha Hauer
2024-10-21 8:03 ` Ahmad Fatoum
1 sibling, 1 reply; 21+ messages in thread
From: Ahmad Fatoum @ 2024-10-21 7:33 UTC (permalink / raw)
To: Sascha Hauer, open list:BAREBOX
Hello Sascha,
On 21.10.24 09:21, Sascha Hauer wrote:
> Unlike other SoCs the LS1046a upstream dtsi files do not have a PSCI
> node. Add one for barebox and Linux to find the PSCI support.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
I am wondering how powering CPUs on and off worked before?
I see no enable-method = "spin-table" in the kernel DT for the SoC.
Anyhow, barebox should probably fixup enable-method = "psci" into each
CPU in /cpus in the kernel DT.
Cheers,
Ahmad
> ---
> arch/arm/dts/fsl-ls1046a.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
> index a661cb0c89..2dc24ba8c7 100644
> --- a/arch/arm/dts/fsl-ls1046a.dtsi
> +++ b/arch/arm/dts/fsl-ls1046a.dtsi
> @@ -4,4 +4,9 @@ / {
> aliases {
> mmc0 = &esdhc;
> };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> };
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 9/9] ARM: Layerscape: LS1046a: add PSCI node
2024-10-21 7:33 ` Ahmad Fatoum
@ 2024-10-21 7:57 ` Sascha Hauer
2024-10-21 8:02 ` Ahmad Fatoum
0 siblings, 1 reply; 21+ messages in thread
From: Sascha Hauer @ 2024-10-21 7:57 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: open list:BAREBOX
Hi Ahmad,
On Mon, Oct 21, 2024 at 09:33:23AM +0200, Ahmad Fatoum wrote:
> Hello Sascha,
>
> On 21.10.24 09:21, Sascha Hauer wrote:
> > Unlike other SoCs the LS1046a upstream dtsi files do not have a PSCI
> > node. Add one for barebox and Linux to find the PSCI support.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>
> I am wondering how powering CPUs on and off worked before?
> I see no enable-method = "spin-table" in the kernel DT for the SoC.
The PPA is PSCI compatible. The barebox PPA adapter called
of_psci_fixup() to register a PSCI node.
>
> Anyhow, barebox should probably fixup enable-method = "psci" into each
> CPU in /cpus in the kernel DT.
This is already done in of_psci_fixup().
The PSCI node in the barebox dts is only needed to probe the psci-client
driver which in turn creates/fixups the PSCI node for the kernel. We
already know that we started the TF-A. I thought about using this
knowledge to register the PSCI client driver without explicitly creating
a device node for it, but on the other hand there isn't too much gain in
doing so, so I just created a node for now.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 9/9] ARM: Layerscape: LS1046a: add PSCI node
2024-10-21 7:57 ` Sascha Hauer
@ 2024-10-21 8:02 ` Ahmad Fatoum
0 siblings, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2024-10-21 8:02 UTC (permalink / raw)
To: Sascha Hauer; +Cc: open list:BAREBOX
On 21.10.24 09:57, Sascha Hauer wrote:
> Hi Ahmad,
>
> On Mon, Oct 21, 2024 at 09:33:23AM +0200, Ahmad Fatoum wrote:
>> Hello Sascha,
>>
>> On 21.10.24 09:21, Sascha Hauer wrote:
>>> Unlike other SoCs the LS1046a upstream dtsi files do not have a PSCI
>>> node. Add one for barebox and Linux to find the PSCI support.
>>>
>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>
>> I am wondering how powering CPUs on and off worked before?
>> I see no enable-method = "spin-table" in the kernel DT for the SoC.
>
> The PPA is PSCI compatible. The barebox PPA adapter called
> of_psci_fixup() to register a PSCI node.
Ah, I see.
>> Anyhow, barebox should probably fixup enable-method = "psci" into each
>> CPU in /cpus in the kernel DT.
>
> This is already done in of_psci_fixup().
>
> The PSCI node in the barebox dts is only needed to probe the psci-client
> driver which in turn creates/fixups the PSCI node for the kernel. We
> already know that we started the TF-A. I thought about using this
> knowledge to register the PSCI client driver without explicitly creating
> a device node for it, but on the other hand there isn't too much gain in
> doing so, so I just created a node for now.
Sounds perfectly sensible.
Thanks for the clarification,
Ahmad
>
> Sascha
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 9/9] ARM: Layerscape: LS1046a: add PSCI node
2024-10-21 7:21 ` [PATCH 9/9] ARM: Layerscape: LS1046a: add PSCI node Sascha Hauer
2024-10-21 7:33 ` Ahmad Fatoum
@ 2024-10-21 8:03 ` Ahmad Fatoum
1 sibling, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2024-10-21 8:03 UTC (permalink / raw)
To: Sascha Hauer, open list:BAREBOX
On 21.10.24 09:21, Sascha Hauer wrote:
> Unlike other SoCs the LS1046a upstream dtsi files do not have a PSCI
> node. Add one for barebox and Linux to find the PSCI support.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/arm/dts/fsl-ls1046a.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
> index a661cb0c89..2dc24ba8c7 100644
> --- a/arch/arm/dts/fsl-ls1046a.dtsi
> +++ b/arch/arm/dts/fsl-ls1046a.dtsi
> @@ -4,4 +4,9 @@ / {
> aliases {
> mmc0 = &esdhc;
> };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> };
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread