From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Sascha Hauer <s.hauer@pengutronix.de>,
BAREBOX <barebox@lists.infradead.org>
Subject: Re: [PATCH v2 5/6] ARM: MMU64: map memory for barebox proper pagewise
Date: Wed, 18 Jun 2025 10:32:28 +0200 [thread overview]
Message-ID: <d6adcae9-fff6-480e-b612-5f2e055ac152@pengutronix.de> (raw)
In-Reply-To: <20250617-mmu-xn-ro-v2-5-3c7aa9046b67@pengutronix.de>
Hello Sascha,
On 6/17/25 16:28, Sascha Hauer wrote:
> Map the remainder of the memory explicitly with two level page tables. This is
> the place where barebox proper ends at. In barebox proper we'll remap the code
> segments readonly/executable and the ro segments readonly/execute never. For this
> we need the memory being mapped pagewise. We can't do the split up from section
> wise mapping to pagewise mapping later because that would require us to do
> a break-before-make sequence which we can't do when barebox proper is running
> at the location being remapped.
>
> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Got a small change request below.
> uint64_t *ttb = get_ttb();
> uint64_t block_size;
> @@ -149,19 +150,25 @@ static void create_sections(uint64_t virt, uint64_t phys, uint64_t size,
> while (size) {
> table = ttb;
> for (level = 0; level < 4; level++) {
> + bool finish = false;
> block_shift = level2shift(level);
> idx = (addr & level2mask(level)) >> block_shift;
> block_size = (1ULL << block_shift);
>
> pte = table + idx;
>
> - if (size >= block_size && IS_ALIGNED(addr, block_size) &&
> - IS_ALIGNED(phys, block_size)) {
> + if (force_pages) {
> + if (level == 3)
> + finish = true;
> + } else if (size >= block_size && IS_ALIGNED(addr, block_size) &&
> + IS_ALIGNED(phys, block_size)) {
> + finish = true;
> + }
> +
> + if (finish) {
Nitpick: I think code would be clearer with:
bool block_aligned = size >= block_size &&
IS_ALIGNED(addr, block_size) &&
IS_ALIGNED(phys, block_size))
if ((force_pages && level == 3) || (!force_pages && block_aligned))
> type = (level == 3) ?
> PTE_TYPE_PAGE : PTE_TYPE_BLOCK;
> -
> - /* TODO: break-before-make missing */
> - set_pte(pte, phys | attr | type);
> + *pte = phys | attr | type;
create_sections is also used in situation where BBM is required.
We should also keep the volatile writes to the page tables.
Can you revert to:
/* TODO: break-before-make missing for non barebox-regions */
set_pte(pte, phys | attr | type);
So we know there is something still left to do?
Thanks,
Ahmad
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next prev parent reply other threads:[~2025-06-18 8:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-17 14:28 [PATCH v2 0/6] ARM: Map sections RO/XN Sascha Hauer
2025-06-17 14:28 ` [PATCH v2 1/6] ARM: pass barebox base to mmu_early_enable() Sascha Hauer
2025-06-17 14:28 ` [PATCH v2 2/6] ARM: mmu: move ARCH_MAP_WRITECOMBINE to header Sascha Hauer
2025-06-17 14:28 ` [PATCH v2 3/6] ARM: MMU: map memory for barebox proper pagewise Sascha Hauer
2025-06-17 14:28 ` [PATCH v2 4/6] ARM: MMU: map text segment ro and data segments execute never Sascha Hauer
2025-06-18 8:13 ` Ahmad Fatoum
2025-06-17 14:28 ` [PATCH v2 5/6] ARM: MMU64: map memory for barebox proper pagewise Sascha Hauer
2025-06-18 8:32 ` Ahmad Fatoum [this message]
2025-06-17 14:28 ` [PATCH v2 6/6] ARM: MMU64: map text segment ro and data segments execute never Sascha Hauer
2025-06-18 8:33 ` Ahmad Fatoum
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