* [PATCH 0/5] Add support for Kalray k1c core
@ 2020-01-15 10:26 Clement Leger
2020-01-15 10:26 ` [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support Clement Leger
` (6 more replies)
0 siblings, 7 replies; 22+ messages in thread
From: Clement Leger @ 2020-01-15 10:26 UTC (permalink / raw)
To: barebox, Sascha Hauer; +Cc: Clement Leger
Kalray k1c core is embedded in Kalray Coolidge SoC. This core has the
following features:
- 32/64 bits
- 6-issue VLIW architecture
- 64 x 64bits general purpose registers
- SIMD instructions
- little-endian
This port is a 64 bits one and allows to boot up to a barebox prompt on a k200
board. k1c support for clocksource and watchdog is also part of this port.
In order to build a usable toolchain, build scripts are provided at the
following address: https://github.com/kalray/build-scripts.
Kalray uses FOSS which is available at https://github.com/kalray
Clement Leger (5):
k1c: Initial Kalray Coolidge (k1c) architecture support
k1c: Add processor definitions
k1c: Add support for device tree
clocksource: k1c: Add k1c clocksource support
watchdog: k1c: Add k1c watchdog support
arch/k1c/Kconfig | 65 +
arch/k1c/Makefile | 37 +
arch/k1c/boards/generic/Makefile | 0
arch/k1c/configs/generic_defconfig | 13 +
arch/k1c/cpu/Makefile | 7 +
arch/k1c/cpu/barebox.lds.S | 98 +
arch/k1c/cpu/cpu.c | 22 +
arch/k1c/cpu/exception.S | 18 +
arch/k1c/cpu/start.S | 164 ++
arch/k1c/dts/Makefile | 13 +
arch/k1c/dts/k200.dts | 105 +
arch/k1c/include/asm/barrier.h | 18 +
arch/k1c/include/asm/bitops.h | 27 +
arch/k1c/include/asm/bitsperlong.h | 12 +
arch/k1c/include/asm/byteorder.h | 12 +
arch/k1c/include/asm/common.h | 19 +
arch/k1c/include/asm/elf.h | 21 +
arch/k1c/include/asm/io.h | 14 +
arch/k1c/include/asm/linkage.h | 10 +
arch/k1c/include/asm/posix_types.h | 12 +
arch/k1c/include/asm/privilege.h | 166 ++
arch/k1c/include/asm/sections.h | 12 +
arch/k1c/include/asm/sfr.h | 61 +
arch/k1c/include/asm/sfr_defs.h | 5029 ++++++++++++++++++++++++++++++++++++
arch/k1c/include/asm/string.h | 14 +
arch/k1c/include/asm/swab.h | 14 +
arch/k1c/include/asm/sys_arch.h | 46 +
arch/k1c/include/asm/types.h | 14 +
arch/k1c/include/asm/unaligned.h | 17 +
arch/k1c/lib/Makefile | 6 +
arch/k1c/lib/asm-offsets.c | 11 +
arch/k1c/lib/board.c | 20 +
arch/k1c/lib/cpuinfo.c | 20 +
arch/k1c/lib/dtb.c | 31 +
arch/k1c/lib/poweroff.c | 43 +
drivers/clocksource/Kconfig | 4 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/k1c_timer.c | 59 +
drivers/of/Kconfig | 2 +-
drivers/watchdog/Kconfig | 7 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/k1c_wdt.c | 126 +
42 files changed, 6390 insertions(+), 1 deletion(-)
create mode 100644 arch/k1c/Kconfig
create mode 100644 arch/k1c/Makefile
create mode 100644 arch/k1c/boards/generic/Makefile
create mode 100644 arch/k1c/configs/generic_defconfig
create mode 100644 arch/k1c/cpu/Makefile
create mode 100644 arch/k1c/cpu/barebox.lds.S
create mode 100644 arch/k1c/cpu/cpu.c
create mode 100644 arch/k1c/cpu/exception.S
create mode 100644 arch/k1c/cpu/start.S
create mode 100644 arch/k1c/dts/Makefile
create mode 100644 arch/k1c/dts/k200.dts
create mode 100644 arch/k1c/include/asm/barrier.h
create mode 100644 arch/k1c/include/asm/bitops.h
create mode 100644 arch/k1c/include/asm/bitsperlong.h
create mode 100644 arch/k1c/include/asm/byteorder.h
create mode 100644 arch/k1c/include/asm/common.h
create mode 100644 arch/k1c/include/asm/elf.h
create mode 100644 arch/k1c/include/asm/io.h
create mode 100644 arch/k1c/include/asm/linkage.h
create mode 100644 arch/k1c/include/asm/posix_types.h
create mode 100644 arch/k1c/include/asm/privilege.h
create mode 100644 arch/k1c/include/asm/sections.h
create mode 100644 arch/k1c/include/asm/sfr.h
create mode 100644 arch/k1c/include/asm/sfr_defs.h
create mode 100644 arch/k1c/include/asm/string.h
create mode 100644 arch/k1c/include/asm/swab.h
create mode 100644 arch/k1c/include/asm/sys_arch.h
create mode 100644 arch/k1c/include/asm/types.h
create mode 100644 arch/k1c/include/asm/unaligned.h
create mode 100644 arch/k1c/lib/Makefile
create mode 100644 arch/k1c/lib/asm-offsets.c
create mode 100644 arch/k1c/lib/board.c
create mode 100644 arch/k1c/lib/cpuinfo.c
create mode 100644 arch/k1c/lib/dtb.c
create mode 100644 arch/k1c/lib/poweroff.c
create mode 100644 drivers/clocksource/k1c_timer.c
create mode 100644 drivers/watchdog/k1c_wdt.c
--
2.15.0.276.g89ea799
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^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support 2020-01-15 10:26 [PATCH 0/5] Add support for Kalray k1c core Clement Leger @ 2020-01-15 10:26 ` Clement Leger 2020-01-16 9:26 ` Sascha Hauer 2020-01-15 10:26 ` [PATCH 2/5] k1c: Add processor definitions Clement Leger ` (5 subsequent siblings) 6 siblings, 1 reply; 22+ messages in thread From: Clement Leger @ 2020-01-15 10:26 UTC (permalink / raw) To: barebox, Sascha Hauer; +Cc: Clement Leger Add kalray coolidge arch/ support. Signed-off-by: Clement Leger <cleger@kalray.eu> --- arch/k1c/Kconfig | 45 ++++++++++ arch/k1c/Makefile | 36 ++++++++ arch/k1c/boards/generic/Makefile | 0 arch/k1c/configs/generic_defconfig | 9 ++ arch/k1c/cpu/Makefile | 7 ++ arch/k1c/cpu/barebox.lds.S | 98 ++++++++++++++++++++++ arch/k1c/cpu/cpu.c | 22 +++++ arch/k1c/cpu/exception.S | 18 ++++ arch/k1c/cpu/start.S | 164 ++++++++++++++++++++++++++++++++++++ arch/k1c/include/asm/barrier.h | 18 ++++ arch/k1c/include/asm/bitops.h | 27 ++++++ arch/k1c/include/asm/bitsperlong.h | 12 +++ arch/k1c/include/asm/byteorder.h | 12 +++ arch/k1c/include/asm/common.h | 19 +++++ arch/k1c/include/asm/elf.h | 21 +++++ arch/k1c/include/asm/io.h | 14 ++++ arch/k1c/include/asm/linkage.h | 10 +++ arch/k1c/include/asm/posix_types.h | 12 +++ arch/k1c/include/asm/privilege.h | 166 +++++++++++++++++++++++++++++++++++++ arch/k1c/include/asm/sections.h | 12 +++ arch/k1c/include/asm/sfr.h | 61 ++++++++++++++ arch/k1c/include/asm/string.h | 14 ++++ arch/k1c/include/asm/swab.h | 14 ++++ arch/k1c/include/asm/sys_arch.h | 46 ++++++++++ arch/k1c/include/asm/types.h | 14 ++++ arch/k1c/include/asm/unaligned.h | 17 ++++ arch/k1c/lib/Makefile | 6 ++ arch/k1c/lib/asm-offsets.c | 11 +++ arch/k1c/lib/board.c | 20 +++++ arch/k1c/lib/cpuinfo.c | 20 +++++ arch/k1c/lib/dtb.c | 31 +++++++ arch/k1c/lib/poweroff.c | 43 ++++++++++ drivers/of/Kconfig | 2 +- 33 files changed, 1020 insertions(+), 1 deletion(-) create mode 100644 arch/k1c/Kconfig create mode 100644 arch/k1c/Makefile create mode 100644 arch/k1c/boards/generic/Makefile create mode 100644 arch/k1c/configs/generic_defconfig create mode 100644 arch/k1c/cpu/Makefile create mode 100644 arch/k1c/cpu/barebox.lds.S create mode 100644 arch/k1c/cpu/cpu.c create mode 100644 arch/k1c/cpu/exception.S create mode 100644 arch/k1c/cpu/start.S create mode 100644 arch/k1c/include/asm/barrier.h create mode 100644 arch/k1c/include/asm/bitops.h create mode 100644 arch/k1c/include/asm/bitsperlong.h create mode 100644 arch/k1c/include/asm/byteorder.h create mode 100644 arch/k1c/include/asm/common.h create mode 100644 arch/k1c/include/asm/elf.h create mode 100644 arch/k1c/include/asm/io.h create mode 100644 arch/k1c/include/asm/linkage.h create mode 100644 arch/k1c/include/asm/posix_types.h create mode 100644 arch/k1c/include/asm/privilege.h create mode 100644 arch/k1c/include/asm/sections.h create mode 100644 arch/k1c/include/asm/sfr.h create mode 100644 arch/k1c/include/asm/string.h create mode 100644 arch/k1c/include/asm/swab.h create mode 100644 arch/k1c/include/asm/sys_arch.h create mode 100644 arch/k1c/include/asm/types.h create mode 100644 arch/k1c/include/asm/unaligned.h create mode 100644 arch/k1c/lib/Makefile create mode 100644 arch/k1c/lib/asm-offsets.c create mode 100644 arch/k1c/lib/board.c create mode 100644 arch/k1c/lib/cpuinfo.c create mode 100644 arch/k1c/lib/dtb.c create mode 100644 arch/k1c/lib/poweroff.c diff --git a/arch/k1c/Kconfig b/arch/k1c/Kconfig new file mode 100644 index 000000000..f0f9d1728 --- /dev/null +++ b/arch/k1c/Kconfig @@ -0,0 +1,45 @@ +config K1C + bool + select 64BIT + select CLKDEV_LOOKUP + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select FLEXIBLE_BOOTARGS + select GENERIC_FIND_NEXT_BIT + select OF_BAREBOX_DRIVERS + select OFDEVICE + select PARTITION + default y + +config PHYS_ADDR_T_64BIT + bool + +config 64BIT + bool + select ARCH_DMA_ADDR_T_64BIT + select PHYS_ADDR_T_64BIT + default y + +config ARCH_TEXT_BASE + hex + default 0x00000000 + +menu "Kalray specific settings" + +config ARCHINFO + string + default "coolidge" + +config SMEM_SIZE + hex + default 0x400000 + +config MALLOC_BASE + hex + default 0x100000000 + +config MALLOC_SIZE + hex + default 0x800000 + prompt "malloc area size" +endmenu diff --git a/arch/k1c/Makefile b/arch/k1c/Makefile new file mode 100644 index 000000000..10852406f --- /dev/null +++ b/arch/k1c/Makefile @@ -0,0 +1,36 @@ +KBUILD_DEFCONFIG := generic_defconfig + +CPPFLAGS += -fno-strict-aliasing + +board-$(CONFIG_GENERIC) := generic + +KALLSYMS += --symbol-prefix=_ + +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := k1-elf- +endif + +DEFAULT_CFLAGS := -nostdlib -fno-builtin -fstrict-align -g +DEFAULT_CFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) + +LIBGCC_PATH = $(dir $(shell $(CC) $(CFLAGS) --print-libgcc-file-name)) + +CFLAGS += $(DEFAULT_CFLAGS) +AFLAGS += $(DEFAULT_CFLAGS) + +LDFLAGS += -m elf64k1 + +archprepare: maketools + +PHONY += maketools + +common-y += arch/k1c/lib/ +common-y += arch/k1c/cpu/ + +lds-y += arch/k1c/cpu/barebox.lds + +cmd_barebox__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_barebox) -o $@ \ + -T $(barebox-lds) \ + --start-group $(barebox-common) --end-group \ + -L$(LIBGCC_PATH) -lgcc \ + $(filter-out $(barebox-lds) $(barebox-common) FORCE ,$^) diff --git a/arch/k1c/boards/generic/Makefile b/arch/k1c/boards/generic/Makefile new file mode 100644 index 000000000..e69de29bb diff --git a/arch/k1c/configs/generic_defconfig b/arch/k1c/configs/generic_defconfig new file mode 100644 index 000000000..535f1cf8b --- /dev/null +++ b/arch/k1c/configs/generic_defconfig @@ -0,0 +1,9 @@ +CONFIG_AUTO_COMPLETE=y +CONFIG_BAUDRATE=115200 +# CONFIG_BOOTM is not set +CONFIG_CMD_CMP=y +CONFIG_CMD_OF_DUMP=y +CONFIG_CMD_POWEROFF=y +CONFIG_CONSOLE_RATP=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_PINCTRL_SINGLE=y diff --git a/arch/k1c/cpu/Makefile b/arch/k1c/cpu/Makefile new file mode 100644 index 000000000..1d0635206 --- /dev/null +++ b/arch/k1c/cpu/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2019 Kalray Inc. +# + +obj-y += start.o cpu.o exception.o +extra-y += barebox.lds diff --git a/arch/k1c/cpu/barebox.lds.S b/arch/k1c/cpu/barebox.lds.S new file mode 100644 index 000000000..9b0c338d2 --- /dev/null +++ b/arch/k1c/cpu/barebox.lds.S @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <config.h> +#include <asm/common.h> +#include <asm/sys_arch.h> +#include <asm-generic/barebox.lds.h> + +OUTPUT_FORMAT("elf64-k1") +OUTPUT_ARCH("k1:k1c:64") + +#define K1C_ENTRY_ADDRESS 0x0 +#define DTB_DEFAULT_SIZE (24 * 1024) + +MEMORY +{ + smem : ORIGIN = 0, LENGTH = CONFIG_SMEM_SIZE +} + +SECTIONS +{ + . = K1C_ENTRY_ADDRESS; + . = ALIGN(4); + + __start = .; + .text : AT (__start) { + *(.startup); + _stext = .; + *(.text) + _etext = .; + } > smem + + /* Exception vector must be aligned on a huge frontier */ + .exception ALIGN(EXCEPTION_ALIGNMENT) : + { + _exception_start = ABSOLUTE(.); + /** + * First handler is at _exception_start + EXCEPTION_STRIDE + * In order to force getting to the next stride, add at + * least 1 byte of data. The next ALIGN will then be + * forced to get to the next stride. + */ + . += 1; + . = ALIGN(EXCEPTION_STRIDE); + + /* Entry for traps */ + KEEP(*(.exception.trap)); + . += 1; + + /* Entry for interrupts */ + . = ALIGN(EXCEPTION_STRIDE); + KEEP(*(.exception.interrupt)); + . += 1; + + /* Entry for syscall */ + . = ALIGN(EXCEPTION_STRIDE); + KEEP(*(.exception.syscall)); + } > smem + + .rodata ALIGN(8) : { + *(.rodata*) + . = ALIGN(8); + RO_DATA_SECTION + } > smem + + __etext = .; /* End of text and rodata section */ + + . = ALIGN(4); + .data : { + sdata = .; + _sdata = .; + *(.data) + edata = .; + _edata = .; + } > smem + + .gdb_page ALIGN(4 * 1024) : + { + _debug_start = ABSOLUTE(.); + _debug_phy_start = ABSOLUTE(.); + . += 4 * 1024; + } + __debug_phy_end = ABSOLUTE(.); + + /* We use store quad for bss init so align on 16 bytes */ + .bss ALIGN(16): + { + __bss_start = .; + *(.shbss) + *(.bss) + *(COMMON) + } > smem + . = ALIGN(16); + __bss_stop = .; + __end = .; +} diff --git a/arch/k1c/cpu/cpu.c b/arch/k1c/cpu/cpu.c new file mode 100644 index 000000000..209f333a2 --- /dev/null +++ b/arch/k1c/cpu/cpu.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <common.h> +#include <asm/sfr.h> +#include <asm/sys_arch.h> + +void k1c_lowlevel_setup(void) +{ + uint64_t ev_val = (uint64_t) &_exception_start | EXCEPTION_STRIDE; + + /* Install exception handlers */ + k1c_sfr_set(K1C_SFR_EV, ev_val); + + /* Clear exception taken bit now that we setup our handlers */ + k1c_sfr_clear_bit(K1C_SFR_PS, K1C_SFR_PS_ET_SHIFT); + + /* Finally, make sure nobody disabled hardware trap before us */ + k1c_sfr_clear_bit(K1C_SFR_PS, K1C_SFR_PS_HTD_SHIFT); +} diff --git a/arch/k1c/cpu/exception.S b/arch/k1c/cpu/exception.S new file mode 100644 index 000000000..d1b44ae22 --- /dev/null +++ b/arch/k1c/cpu/exception.S @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <linux/linkage.h> + +/** + * We do not aim at handling traps but at least, we want the CPU to + * stop when taking a trap. + * Note that we can not expect to be able to issue a print since + * it might be the cause of trap... + */ +.section .exception.trap, "ax", @progbits +ENTRY(k1c_trap_handler): + goto k1c_trap_handler + ;; +ENDPROC(k1c_trap_handler) diff --git a/arch/k1c/cpu/start.S b/arch/k1c/cpu/start.S new file mode 100644 index 000000000..4cbd3bbd5 --- /dev/null +++ b/arch/k1c/cpu/start.S @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/privilege.h> +#include <asm/sys_arch.h> + +#define PS_VAL_WFXL(__field, __val) \ + SFR_SET_VAL_WFXL(PS, __field, __val) + +#define PS_WFXL_START_VALUE PS_VAL_WFXL(HLE, 1) | \ + PS_VAL_WFXL(USE, 1) | \ + PS_VAL_WFXL(DCE, 1) | \ + PS_VAL_WFXL(ICE, 1) | \ + PS_VAL_WFXL(V64, 1) | \ + PS_VAL_WFXL(ET, 0) + +#define PCR_VAL_WFXM(__field, __val) \ + SFR_SET_VAL_WFXM(PCR, __field, __val) + +#define PCR_WFXM_START_VALUE PCR_VAL_WFXM(L1CE, 1) + +/* Enable STOP in WS */ +#define WS_ENABLE_WU2 (K1C_SFR_WS_WU2_MASK) + +#define WS_WFXL_VALUE (WS_ENABLE_WU2) + +.section .startup, "ax" +ENTRY(k1c_start) + /* (Re)initialize performance counter */ + make $r20 = 0x00000000 + ;; + set $pmc = $r20 + ;; + call asm_init_pl + ;; + /* Setup default processor status */ + make $r25 = PS_WFXL_START_VALUE + ;; + wfxl $ps = $r25 + ;; + make $r25 = PCR_WFXM_START_VALUE + ;; + wfxm $pcr = $r25 + ;; + /* Clear BSS */ + make $r22 = __bss_stop + make $r21 = __bss_start + ;; + sbfd $r22 = $r21, $r22 + make $r24 = 0 + ;; + /* Divide by 16 for hardware loop */ + srld $r22, $r22, 4 + make $r25 = 0 + ;; + /* Clear bss with hardware loop */ + loopdo $r22, clear_bss_done + ;; + sq 0[$r21] = $r24r25 + addd $r21 = $r21, 16 + ;; + clear_bss_done: + /* Setup stack */ + make $sp, CONFIG_SMEM_SIZE + ;; + call k1c_lowlevel_setup + ;; + call k1c_start_barebox + ;; + goto k1c_proc_power_off + ;; +ENDPROC(k1c_start) + +/** + * Initialize privilege level + */ +ENTRY(asm_init_pl) + get $r21 = $ps + ;; + /* Extract privilege level from $ps to check if we need to + * lower our privilege level (we might already be in PL1) + */ + extfz $r20 = $r21, K1C_SFR_END(PS_PL), K1C_SFR_START(PS_PL) + ;; + /* If our pviliege level is not 0 (ie we are already in a less + * privilege level, then, somebody take care of setting the + * ring settings for us and we can return directly + */ + cb.deqz $r20? delegate_pl + ;; + ret + ;; +delegate_pl: + make $r21 = SYO_WFXL_VALUE + ;; + wfxl $syow = $r21 + ;; + make $r21 = HTO_WFXL_VALUE + ;; + wfxl $htow = $r21 + ;; + make $r21 = DO_WFXL_VALUE + ;; + wfxl $dow = $r21 + ;; + make $r21 = MO_WFXL_VALUE + make $r22 = MO_WFXM_VALUE + ;; + wfxl $mow = $r21 + ;; + wfxm $mow = $r22 + ;; + make $r21 = ITO_WFXL_VALUE + make $r22 = ITO_WFXM_VALUE + ;; + wfxl $itow = $r21 + ;; + wfxm $itow = $r21 + ;; + make $r21 = PSO_WFXL_VALUE + ;; + wfxl $psow = $r21 + ;; + make $r21 = PSO_WFXM_VALUE + ;; + wfxm $psow = $r21 + ;; + /* Copy our $ps into $sps for 1:1 restoration */ + get $r22 = $ps + ;; + /* We will return to $ra after rfe */ + get $r21 = $ra + /* Set privilege level to +1 in $sps (relative level from the + * current one) + */ + addd $r22 = $r22, PL_BAREBOX_REL_LEVEL + ;; + set $spc = $r21 + ;; + set $sps = $r22 + ;; + /* When using rfe, $spc and $sps will be restored in $ps and $pc, + * We will then return to the caller ($ra) in current PL + 1 + */ + rfe + ;; +ENDPROC(asm_init_pl) + +ENTRY(k1c_proc_power_off): + dinval + make $r1 = WS_WFXL_VALUE + ;; + /* Enable STOP */ + wfxl $ws, $r1 + ;; +1: stop + ;; + goto 1b + ;; +ENDPROC(k1c_proc_power_off) diff --git a/arch/k1c/include/asm/barrier.h b/arch/k1c/include/asm/barrier.h new file mode 100644 index 000000000..7c1281e7a --- /dev/null +++ b/arch/k1c/include/asm/barrier.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_BARRIER_H +#define _ASM_K1C_BARRIER_H + +/* fence is sufficient to guarantee write ordering */ +#define wmb() __builtin_k1_fence() + +/* no L2 coherency, therefore rmb is D$ invalidation */ +#define rmb() __builtin_k1_dinval() + +/* general memory barrier */ +#define mb() do { wmb(); rmb(); } while (0) + +#endif /* _ASM_K1C_BARRIER_H */ diff --git a/arch/k1c/include/asm/bitops.h b/arch/k1c/include/asm/bitops.h new file mode 100644 index 000000000..c22e5717b --- /dev/null +++ b/arch/k1c/include/asm/bitops.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_BITOPS_H +#define _ASM_K1C_BITOPS_H + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit(x, y) __set_bit(x, y) +#define clear_bit(x, y) __clear_bit(x, y) +#define change_bit(x, y) __change_bit(x, y) +#define test_and_set_bit(x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit(x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit(x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_K1C_BITOPS_H */ + diff --git a/arch/k1c/include/asm/bitsperlong.h b/arch/k1c/include/asm/bitsperlong.h new file mode 100644 index 000000000..42b669ace --- /dev/null +++ b/arch/k1c/include/asm/bitsperlong.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_BITSPERLONG_H +#define _ASM_K1C_BITSPERLONG_H + +#include <asm-generic/bitsperlong.h> + +#endif /* _ASM_K1C_BITSPERLONG_H */ + diff --git a/arch/k1c/include/asm/byteorder.h b/arch/k1c/include/asm/byteorder.h new file mode 100644 index 000000000..12b90bd66 --- /dev/null +++ b/arch/k1c/include/asm/byteorder.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_BYTEORDER_H +#define _ASM_K1C_BYTEORDER_H + +#include <linux/byteorder/little_endian.h> + +#endif /* _ASM_K1C_BYTEORDER_H */ + diff --git a/arch/k1c/include/asm/common.h b/arch/k1c/include/asm/common.h new file mode 100644 index 000000000..81d31dc4c --- /dev/null +++ b/arch/k1c/include/asm/common.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_COMMON_H +#define _ASM_K1C_COMMON_H + +#ifndef __ASSEMBLY__ + +extern char _exception_start; + +void k1c_start_barebox(void); +void k1c_lowlevel_setup(void); + +#endif + +#endif /* _ASM_K1C_COMMON_H */ + diff --git a/arch/k1c/include/asm/elf.h b/arch/k1c/include/asm/elf.h new file mode 100644 index 000000000..ff9b8b274 --- /dev/null +++ b/arch/k1c/include/asm/elf.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_ELF_H +#define _ASM_K1C_ELF_H + +/* + * ELF register definitions.. + */ +#include <linux/types.h> + +#define EM_KALRAY 0x1337 + +#define ELF_ARCH EM_KALRAY +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2MSB + +#endif /* _ASM_K1C_ELF_H */ + diff --git a/arch/k1c/include/asm/io.h b/arch/k1c/include/asm/io.h new file mode 100644 index 000000000..0345d05de --- /dev/null +++ b/arch/k1c/include/asm/io.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_IO_H +#define _ASM_K1C_IO_H + +#define IO_SPACE_LIMIT 0x0 + +#include <asm/byteorder.h> +#include <asm-generic/io.h> + +#endif /* _ASM_K1C_IO_H */ diff --git a/arch/k1c/include/asm/linkage.h b/arch/k1c/include/asm/linkage.h new file mode 100644 index 000000000..9b0f103f9 --- /dev/null +++ b/arch/k1c/include/asm/linkage.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_LINKAGE_H +#define _ASM_K1C_LINKAGE_H + + +#endif /* _ASM_K1C_LINKAGE_H */ diff --git a/arch/k1c/include/asm/posix_types.h b/arch/k1c/include/asm/posix_types.h new file mode 100644 index 000000000..0eba70be6 --- /dev/null +++ b/arch/k1c/include/asm/posix_types.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_POSIX_TYPES_H +#define _ASM_K1C_POSIX_TYPES_H + +#include <asm-generic/posix_types.h> + +#endif /* _ASM_K1C_POSIX_TYPES_H */ + diff --git a/arch/k1c/include/asm/privilege.h b/arch/k1c/include/asm/privilege.h new file mode 100644 index 000000000..d3d1810f2 --- /dev/null +++ b/arch/k1c/include/asm/privilege.h @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_PRIVILEGE_H +#define _ASM_K1C_PRIVILEGE_H + +#include <asm/sys_arch.h> + +/** + * Privilege level stuff + */ + +/* Relative kernel level (+1 from current privilege level) */ +#define PL_BAREBOX_REL_LEVEL 1 + +/** + * Syscall owner configuration + */ +#define SYO_OWN(__field) \ + SFR_SET_VAL_WFXL(SYO, __field, PL_BAREBOX_REL_LEVEL) + +#define SYO_WFXL_VALUE (SYO_OWN(Q0) | \ + SYO_OWN(Q1) | \ + SYO_OWN(Q2) | \ + SYO_OWN(Q3)) + +/** + * hardware trap owner configuration + */ +#define HTO_OWN(__field) \ + SFR_SET_VAL_WFXL(HTO, __field, PL_BAREBOX_REL_LEVEL) + +#define HTO_WFXL_VALUE (HTO_OWN(OPC) | \ + HTO_OWN(DMIS) | \ + HTO_OWN(PSYS) | \ + HTO_OWN(DSYS) | \ + HTO_OWN(DECCG) | \ + HTO_OWN(SECCG) | \ + HTO_OWN(NOMAP) | \ + HTO_OWN(PROT) | \ + HTO_OWN(W2CL) | \ + HTO_OWN(A2CL) | \ + HTO_OWN(DE) | \ + HTO_OWN(VSFR) | \ + HTO_OWN(PLO)) + +/** + * Interrupt owner configuration + */ +#define ITO_WFXL_OWN(__field) \ + SFR_SET_VAL_WFXL(ITO, __field, PL_BAREBOX_REL_LEVEL) + +#define ITO_WFXL_VALUE (ITO_WFXL_OWN(IT0) | \ + ITO_WFXL_OWN(IT1) | \ + ITO_WFXL_OWN(IT2) | \ + ITO_WFXL_OWN(IT3) | \ + ITO_WFXL_OWN(IT4) | \ + ITO_WFXL_OWN(IT5) | \ + ITO_WFXL_OWN(IT6) | \ + ITO_WFXL_OWN(IT7) | \ + ITO_WFXL_OWN(IT8) | \ + ITO_WFXL_OWN(IT9) | \ + ITO_WFXL_OWN(IT10) | \ + ITO_WFXL_OWN(IT11) | \ + ITO_WFXL_OWN(IT12) | \ + ITO_WFXL_OWN(IT13) | \ + ITO_WFXL_OWN(IT14) | \ + ITO_WFXL_OWN(IT15)) + +#define ITO_WFXM_OWN(__field) \ + SFR_SET_VAL_WFXM(ITO, __field, PL_BAREBOX_REL_LEVEL) + +#define ITO_WFXM_VALUE (ITO_WFXM_OWN(IT16) | \ + ITO_WFXM_OWN(IT17) | \ + ITO_WFXM_OWN(IT18) | \ + ITO_WFXM_OWN(IT19) | \ + ITO_WFXM_OWN(IT20) | \ + ITO_WFXM_OWN(IT21) | \ + ITO_WFXM_OWN(IT22) | \ + ITO_WFXM_OWN(IT23) | \ + ITO_WFXM_OWN(IT24) | \ + ITO_WFXM_OWN(IT25) | \ + ITO_WFXM_OWN(IT26) | \ + ITO_WFXM_OWN(IT27) | \ + ITO_WFXM_OWN(IT28) | \ + ITO_WFXM_OWN(IT29) | \ + ITO_WFXM_OWN(IT30) | \ + ITO_WFXM_OWN(IT31)) + +/** + * Misc owner configuration + */ +#define DO_OWN(__field) \ + SFR_SET_VAL_WFXL(DO, __field, PL_BAREBOX_REL_LEVEL) + +#define DO_WFXL_VALUE (DO_OWN(B0) | \ + DO_OWN(B1) | \ + DO_OWN(W0) | \ + DO_OWN(W1)) + +/** + * Misc owner configuration + */ +#define MO_WFXL_OWN(__field) \ + SFR_SET_VAL_WFXL(MO, __field, PL_BAREBOX_REL_LEVEL) + +#define MO_WFXL_VALUE (MO_WFXL_OWN(MMI) | \ + MO_WFXL_OWN(RFE) | \ + MO_WFXL_OWN(STOP) | \ + MO_WFXL_OWN(SYNC) | \ + MO_WFXL_OWN(PCR) | \ + MO_WFXL_OWN(MSG) | \ + MO_WFXL_OWN(MEN) | \ + MO_WFXL_OWN(MES) | \ + MO_WFXL_OWN(CSIT) | \ + MO_WFXL_OWN(T0) | \ + MO_WFXL_OWN(T1) | \ + MO_WFXL_OWN(WD) | \ + MO_WFXL_OWN(PM0) | \ + MO_WFXL_OWN(PM1) | \ + MO_WFXL_OWN(PM2) | \ + MO_WFXL_OWN(PM3)) + +#define MO_WFXM_OWN(__field) \ + SFR_SET_VAL_WFXM(MO, __field, PL_BAREBOX_REL_LEVEL) + +#define MO_WFXM_VALUE (MO_WFXM_OWN(PMIT)) + +/** + * $ps owner configuration + */ +#define PSO_WFXL_OWN(__field) \ + SFR_SET_VAL_WFXL(PSO, __field, PL_BAREBOX_REL_LEVEL) + +#define PSO_WFXL_VALUE (PSO_WFXL_OWN(PL0) | \ + PSO_WFXL_OWN(PL1) | \ + PSO_WFXL_OWN(ET) | \ + PSO_WFXL_OWN(HTD) | \ + PSO_WFXL_OWN(IE) | \ + PSO_WFXL_OWN(HLE) | \ + PSO_WFXL_OWN(SRE) | \ + PSO_WFXL_OWN(ICE) | \ + PSO_WFXL_OWN(USE) | \ + PSO_WFXL_OWN(DCE) | \ + PSO_WFXL_OWN(MME) | \ + PSO_WFXL_OWN(IL0) | \ + PSO_WFXL_OWN(IL1) | \ + PSO_WFXL_OWN(VS0) | \ + PSO_WFXL_OWN(VS1)) + +#define PSO_WFXM_OWN(__field) \ + SFR_SET_VAL_WFXM(PSO, __field, PL_BAREBOX_REL_LEVEL) + +#define PSO_WFXM_VALUE (PSO_WFXM_OWN(V64) | \ + PSO_WFXM_OWN(L2E) | \ + PSO_WFXM_OWN(SME) | \ + PSO_WFXM_OWN(SMR) | \ + PSO_WFXM_OWN(PMJ0) | \ + PSO_WFXM_OWN(PMJ1) | \ + PSO_WFXM_OWN(PMJ2) | \ + PSO_WFXM_OWN(PMJ3) | \ + PSO_WFXM_OWN(MMUP)) + +#endif /* _ASM_K1C_PRIVILEGE_H */ diff --git a/arch/k1c/include/asm/sections.h b/arch/k1c/include/asm/sections.h new file mode 100644 index 000000000..85e76c013 --- /dev/null +++ b/arch/k1c/include/asm/sections.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_SECTIONS_H +#define _ASM_K1C_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif /* _ASM_K1C_SECTIONS_H */ + diff --git a/arch/k1c/include/asm/sfr.h b/arch/k1c/include/asm/sfr.h new file mode 100644 index 000000000..3569924a8 --- /dev/null +++ b/arch/k1c/include/asm/sfr.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_SFR_H +#define _ASM_K1C_SFR_H + +#include <asm/sfr_defs.h> + +#define wfxl(_sfr, _val) __builtin_k1_wfxl(_sfr, _val) + +#define wfxm(_sfr, _val) __builtin_k1_wfxm(_sfr, _val) + +static inline void +k1c_sfr_set_bit(unsigned char sfr, unsigned char bit) +{ + if (bit < 32) + wfxl(sfr, (uint64_t) (1 << bit) << 32); + else + wfxm(sfr, (uint64_t) 1 << bit); +} + +static inline uint64_t make_sfr_val(uint64_t mask, uint64_t value) +{ + return ((value & 0xFFFFFFFF) << 32) | (mask & 0xFFFFFFFF); +} + +static inline void +k1c_sfr_set_mask(unsigned char sfr, uint64_t mask, uint64_t value) +{ + uint64_t wf_val; + /* Least significant bits */ + if (mask & 0xFFFFFFFF) { + wf_val = make_sfr_val(value, mask); + wfxl(sfr, wf_val); + } + + /* Most significant bits */ + if (mask & (0xFFFFFFFFULL << 32)) { + value >>= 32; + mask >>= 32; + wf_val = make_sfr_val(value, mask); + wfxm(sfr, wf_val); + } +} + +static inline void +k1c_sfr_clear_bit(unsigned char sfr, unsigned char bit) +{ + if (bit < 32) + wfxl(sfr, 1 << bit); + else + wfxm(sfr, 1 << (bit - 32)); +} + +#define k1c_sfr_set(_sfr, _val) __builtin_k1_set(_sfr, _val) +#define k1c_sfr_get(_sfr) __builtin_k1_get(_sfr) + + +#endif /* _ASM_K1C_SFR_DEFS_H */ diff --git a/arch/k1c/include/asm/string.h b/arch/k1c/include/asm/string.h new file mode 100644 index 000000000..902811b8a --- /dev/null +++ b/arch/k1c/include/asm/string.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_STRING_H +#define _ASM_K1C_STRING_H + +/** + * FIXME AUTO: Implement optimized memcpy and memset for k1c + */ + +#endif /* _ASM_K1C_STRING_H */ + diff --git a/arch/k1c/include/asm/swab.h b/arch/k1c/include/asm/swab.h new file mode 100644 index 000000000..4149bf50f --- /dev/null +++ b/arch/k1c/include/asm/swab.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_SWAB_H +#define _ASM_K1C_SWAB_H + +/** + * FIXME AUTO: Implement optimized byte swap using sbmm for k1c + */ + +#endif /* _ASM_K1C_SWAB_H */ + diff --git a/arch/k1c/include/asm/sys_arch.h b/arch/k1c/include/asm/sys_arch.h new file mode 100644 index 000000000..f7049fd37 --- /dev/null +++ b/arch/k1c/include/asm/sys_arch.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_SYS_ARCH_H +#define _ASM_K1C_SYS_ARCH_H + +#include <asm/sfr_defs.h> + +#define EXCEPTION_STRIDE 0x40 +#define EXCEPTION_ALIGNMENT 0x100 + +#define K1C_SFR_START(__sfr_reg) \ + (K1C_SFR_## __sfr_reg ## _SHIFT) + +#define K1C_SFR_END(__sfr_reg) \ + (K1C_SFR_## __sfr_reg ## _SHIFT + K1C_SFR_## __sfr_reg ## _WIDTH - 1) + +/** + * Get the value to clear a sfr + */ +#define SFR_CLEAR(__sfr, __field, __lm) \ + K1C_SFR_## __sfr ## _ ## __field ## _ ## __lm ## _CLEAR + +#define SFR_CLEAR_WFXL(__sfr, __field) SFR_CLEAR(__sfr, __field, WFXL) +#define SFR_CLEAR_WFXM(__sfr, __field) SFR_CLEAR(__sfr, __field, WFXM) + +/** + * Get the value to set a sfr. + */ +#define SFR_SET_WFXL(__sfr, __field, __val) \ + (__val << (K1C_SFR_ ## __sfr ## _ ## __field ## _SHIFT + 32)) + +#define SFR_SET_WFXM(__sfr, __field, __val) \ + (__val << (K1C_SFR_ ## __sfr ## _ ## __field ## _SHIFT)) + +/** + * Generate the mask to clear and set a value using wfx{m|l}. + */ +#define SFR_SET_VAL_WFXL(__sfr, __field, __val) \ + (SFR_SET_WFXL(__sfr, __field, __val) | SFR_CLEAR_WFXL(__sfr, __field)) +#define SFR_SET_VAL_WFXM(__sfr, __field, __val) \ + (SFR_SET_WFXM(__sfr, __field, __val) | SFR_CLEAR_WFXM(__sfr, __field)) + +#endif /* _ASM_K1C_SYS_ARCH_H */ diff --git a/arch/k1c/include/asm/types.h b/arch/k1c/include/asm/types.h new file mode 100644 index 000000000..f58746ddf --- /dev/null +++ b/arch/k1c/include/asm/types.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_TYPES_H +#define _ASM_K1C_TYPES_H + +#include <asm-generic/int-ll64.h> + +typedef unsigned short umode_t; + +#endif /* _ASM_K1C_TYPES_H */ + diff --git a/arch/k1c/include/asm/unaligned.h b/arch/k1c/include/asm/unaligned.h new file mode 100644 index 000000000..37a5790a0 --- /dev/null +++ b/arch/k1c/include/asm/unaligned.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_UNALIGNED_H +#define _ASM_K1C_UNALIGNED_H + +#include <linux/unaligned/le_struct.h> +#include <linux/unaligned/be_byteshift.h> +#include <linux/unaligned/generic.h> + +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le + +#endif /* _ASM_K1C_UNALIGNED_H */ + diff --git a/arch/k1c/lib/Makefile b/arch/k1c/lib/Makefile new file mode 100644 index 000000000..352e7034a --- /dev/null +++ b/arch/k1c/lib/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2019 Kalray Inc. +# + +obj-y += cpuinfo.o board.o dtb.o poweroff.o diff --git a/arch/k1c/lib/asm-offsets.c b/arch/k1c/lib/asm-offsets.c new file mode 100644 index 000000000..9ab4fc4d4 --- /dev/null +++ b/arch/k1c/lib/asm-offsets.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <linux/kbuild.h> + +int main(void) +{ + return 0; +} diff --git a/arch/k1c/lib/board.c b/arch/k1c/lib/board.c new file mode 100644 index 000000000..d17a32614 --- /dev/null +++ b/arch/k1c/lib/board.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <common.h> +#include <malloc.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> + + +void __noreturn k1c_start_barebox(void) +{ + mem_malloc_init((void *)CONFIG_MALLOC_BASE, + (void *)(CONFIG_MALLOC_BASE + MALLOC_SIZE - 1)); + + start_barebox(); + + hang(); +} diff --git a/arch/k1c/lib/cpuinfo.c b/arch/k1c/lib/cpuinfo.c new file mode 100644 index 000000000..f17a0dc6b --- /dev/null +++ b/arch/k1c/lib/cpuinfo.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <common.h> +#include <command.h> + +static int do_cpuinfo(int argc, char *argv[]) +{ + printf("Kalray Coolidge\n"); + + return 0; +} + +BAREBOX_CMD_START(cpuinfo) + .cmd = do_cpuinfo, + BAREBOX_CMD_DESC("show CPU information") + BAREBOX_CMD_GROUP(CMD_GRP_INFO) +BAREBOX_CMD_END diff --git a/arch/k1c/lib/dtb.c b/arch/k1c/lib/dtb.c new file mode 100644 index 000000000..582967e72 --- /dev/null +++ b/arch/k1c/lib/dtb.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <common.h> +#include <init.h> +#include <of.h> + +extern char __dtb_start[]; + +static int of_k1c_init(void) +{ + int ret; + struct device_node *root; + + root = of_unflatten_dtb(__dtb_start); + if (IS_ERR(root)) { + ret = PTR_ERR(root); + panic("Failed to parse DTB: %d\n", ret); + } + + ret = of_set_root_node(root); + if (ret) + panic("Failed to set of root node\n"); + + of_probe(); + + return 0; +} +core_initcall(of_k1c_init); diff --git a/arch/k1c/lib/poweroff.c b/arch/k1c/lib/poweroff.c new file mode 100644 index 000000000..001ca6b6c --- /dev/null +++ b/arch/k1c/lib/poweroff.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <init.h> +#include <common.h> +#include <poweroff.h> + +static void __noreturn k1c_poweroff(struct poweroff_handler *handler) +{ + register int status asm("r0") = 0; + + shutdown_barebox(); + + asm volatile ("scall 0xfff\n\t;;" + : : "r"(status) + : "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "memory"); + hang(); +} + +static int k1c_scall_poweroff_probe(struct device_d *dev) +{ + poweroff_handler_register_fn(k1c_poweroff); + + return 0; +} + +static __maybe_unused struct of_device_id k1c_scall_poweroff_id[] = { + { + .compatible = "kalray,k1c-scall-poweroff", + }, { + } +}; + +static struct driver_d k1c_scall_poweroff = { + .name = "k1c_scall_poweroff", + .probe = k1c_scall_poweroff_probe, + .of_compatible = DRV_OF_COMPAT(k1c_scall_poweroff_id), +}; + +device_platform_driver(k1c_scall_poweroff); diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig index 7436fc2de..24ab2eddb 100644 --- a/drivers/of/Kconfig +++ b/drivers/of/Kconfig @@ -4,7 +4,7 @@ config OFTREE config OFTREE_MEM_GENERIC depends on OFTREE - depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX || RISCV + depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX || RISCV || K1C def_bool y config DTC -- 2.15.0.276.g89ea799 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support 2020-01-15 10:26 ` [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support Clement Leger @ 2020-01-16 9:26 ` Sascha Hauer 2020-01-16 10:49 ` Clément Leger 0 siblings, 1 reply; 22+ messages in thread From: Sascha Hauer @ 2020-01-16 9:26 UTC (permalink / raw) To: Clement Leger; +Cc: barebox On Wed, Jan 15, 2020 at 11:26:46AM +0100, Clement Leger wrote: > +config MALLOC_BASE > + hex > + default 0x100000000 > + > +config MALLOC_SIZE > + hex > + default 0x800000 > + prompt "malloc area size" > +endmenu > diff --git a/arch/k1c/lib/board.c b/arch/k1c/lib/board.c > new file mode 100644 > index 000000000..d17a32614 > --- /dev/null > +++ b/arch/k1c/lib/board.c > @@ -0,0 +1,20 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2019 Kalray Inc. > + */ > + > +#include <common.h> > +#include <malloc.h> > +#include <memory.h> > +#include <asm-generic/memory_layout.h> > + > + > +void __noreturn k1c_start_barebox(void) > +{ > + mem_malloc_init((void *)CONFIG_MALLOC_BASE, > + (void *)(CONFIG_MALLOC_BASE + MALLOC_SIZE - 1)); You could extract valid memory from the device tree instead and pick some memory for malloc there. See of_find_mem() how this can be done. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support 2020-01-16 9:26 ` Sascha Hauer @ 2020-01-16 10:49 ` Clément Leger 2020-01-16 10:55 ` Sascha Hauer 0 siblings, 1 reply; 22+ messages in thread From: Clément Leger @ 2020-01-16 10:49 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List Hi Sasha ----- On 16 Jan, 2020, at 10:26, Sascha Hauer s.hauer@pengutronix.de wrote: > On Wed, Jan 15, 2020 at 11:26:46AM +0100, Clement Leger wrote: >> +config MALLOC_BASE >> + hex >> + default 0x100000000 >> + >> +config MALLOC_SIZE >> + hex >> + default 0x800000 >> + prompt "malloc area size" >> +endmenu > >> diff --git a/arch/k1c/lib/board.c b/arch/k1c/lib/board.c >> new file mode 100644 >> index 000000000..d17a32614 >> --- /dev/null >> +++ b/arch/k1c/lib/board.c >> @@ -0,0 +1,20 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (C) 2019 Kalray Inc. >> + */ >> + >> +#include <common.h> >> +#include <malloc.h> >> +#include <memory.h> >> +#include <asm-generic/memory_layout.h> >> + >> + >> +void __noreturn k1c_start_barebox(void) >> +{ >> + mem_malloc_init((void *)CONFIG_MALLOC_BASE, >> + (void *)(CONFIG_MALLOC_BASE + MALLOC_SIZE - 1)); > > You could extract valid memory from the device tree instead and pick > some memory for malloc there. See of_find_mem() how this can be done. I think we are going to bite our tail here since of_unflatten_dtb does some xzalloc to unflatten the DTB so we need to initialize the malloc allocator before accessing DTB. > > Sascha > > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support 2020-01-16 10:49 ` Clément Leger @ 2020-01-16 10:55 ` Sascha Hauer 2020-01-16 12:24 ` Clément Leger 0 siblings, 1 reply; 22+ messages in thread From: Sascha Hauer @ 2020-01-16 10:55 UTC (permalink / raw) To: Clément Leger; +Cc: Barebox List On Thu, Jan 16, 2020 at 11:49:31AM +0100, Clément Leger wrote: > Hi Sasha > > ----- On 16 Jan, 2020, at 10:26, Sascha Hauer s.hauer@pengutronix.de wrote: > > > On Wed, Jan 15, 2020 at 11:26:46AM +0100, Clement Leger wrote: > >> +config MALLOC_BASE > >> + hex > >> + default 0x100000000 > >> + > >> +config MALLOC_SIZE > >> + hex > >> + default 0x800000 > >> + prompt "malloc area size" > >> +endmenu > > > >> diff --git a/arch/k1c/lib/board.c b/arch/k1c/lib/board.c > >> new file mode 100644 > >> index 000000000..d17a32614 > >> --- /dev/null > >> +++ b/arch/k1c/lib/board.c > >> @@ -0,0 +1,20 @@ > >> +// SPDX-License-Identifier: GPL-2.0-only > >> +/* > >> + * Copyright (C) 2019 Kalray Inc. > >> + */ > >> + > >> +#include <common.h> > >> +#include <malloc.h> > >> +#include <memory.h> > >> +#include <asm-generic/memory_layout.h> > >> + > >> + > >> +void __noreturn k1c_start_barebox(void) > >> +{ > >> + mem_malloc_init((void *)CONFIG_MALLOC_BASE, > >> + (void *)(CONFIG_MALLOC_BASE + MALLOC_SIZE - 1)); > > > > You could extract valid memory from the device tree instead and pick > > some memory for malloc there. See of_find_mem() how this can be done. > > I think we are going to bite our tail here since of_unflatten_dtb does > some xzalloc to unflatten the DTB so we need to initialize the malloc > allocator before accessing DTB. of_find_mem() doesn't use of_unflatten_dtb(), it uses libfdt to parse the device tree. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support 2020-01-16 10:55 ` Sascha Hauer @ 2020-01-16 12:24 ` Clément Leger 2020-01-16 13:11 ` Sascha Hauer 0 siblings, 1 reply; 22+ messages in thread From: Clément Leger @ 2020-01-16 12:24 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List ----- On 16 Jan, 2020, at 11:55, Sascha Hauer s.hauer@pengutronix.de wrote: > On Thu, Jan 16, 2020 at 11:49:31AM +0100, Clément Leger wrote: >> Hi Sasha >> >> ----- On 16 Jan, 2020, at 10:26, Sascha Hauer s.hauer@pengutronix.de wrote: >> >> > On Wed, Jan 15, 2020 at 11:26:46AM +0100, Clement Leger wrote: >> >> +config MALLOC_BASE >> >> + hex >> >> + default 0x100000000 >> >> + >> >> +config MALLOC_SIZE >> >> + hex >> >> + default 0x800000 >> >> + prompt "malloc area size" >> >> +endmenu >> > >> >> diff --git a/arch/k1c/lib/board.c b/arch/k1c/lib/board.c >> >> new file mode 100644 >> >> index 000000000..d17a32614 >> >> --- /dev/null >> >> +++ b/arch/k1c/lib/board.c >> >> @@ -0,0 +1,20 @@ >> >> +// SPDX-License-Identifier: GPL-2.0-only >> >> +/* >> >> + * Copyright (C) 2019 Kalray Inc. >> >> + */ >> >> + >> >> +#include <common.h> >> >> +#include <malloc.h> >> >> +#include <memory.h> >> >> +#include <asm-generic/memory_layout.h> >> >> + >> >> + >> >> +void __noreturn k1c_start_barebox(void) >> >> +{ >> >> + mem_malloc_init((void *)CONFIG_MALLOC_BASE, >> >> + (void *)(CONFIG_MALLOC_BASE + MALLOC_SIZE - 1)); >> > >> > You could extract valid memory from the device tree instead and pick >> > some memory for malloc there. See of_find_mem() how this can be done. >> >> I think we are going to bite our tail here since of_unflatten_dtb does >> some xzalloc to unflatten the DTB so we need to initialize the malloc >> allocator before accessing DTB. > > of_find_mem() doesn't use of_unflatten_dtb(), it uses libfdt to parse > the device tree. Oh indeed. I looked at it and I see potential problems: - Stack address/size will still need to be hardcoded because it needs to be setup before executing C code. - We have multiple memory nodes in our device tree (SMEM and DDR) so we will probably have to do some quirks to finally find the DDR memory node. - MALLOC_SIZE will still needs to be there I'm afraid we will end up with some mixed up approach were one mecanism is dynamic (malloc) and the other is not (stack). Moreover, the "dynamic" memory detection will be potentially tainted with some if (mem_addr > 0x100000000). One other option would be to add a compatible field in the memory node. This way, the search could be easier but I will still have to hardcode the stack address. Tell me if you see another mecanism > > Sascha > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support 2020-01-16 12:24 ` Clément Leger @ 2020-01-16 13:11 ` Sascha Hauer 2020-01-16 13:26 ` Clément Leger 0 siblings, 1 reply; 22+ messages in thread From: Sascha Hauer @ 2020-01-16 13:11 UTC (permalink / raw) To: Clément Leger; +Cc: Barebox List On Thu, Jan 16, 2020 at 01:24:41PM +0100, Clément Leger wrote: > > ----- On 16 Jan, 2020, at 11:55, Sascha Hauer s.hauer@pengutronix.de wrote: > > > On Thu, Jan 16, 2020 at 11:49:31AM +0100, Clément Leger wrote: > >> Hi Sasha > >> > >> ----- On 16 Jan, 2020, at 10:26, Sascha Hauer s.hauer@pengutronix.de wrote: > >> > >> > On Wed, Jan 15, 2020 at 11:26:46AM +0100, Clement Leger wrote: > >> >> +config MALLOC_BASE > >> >> + hex > >> >> + default 0x100000000 > >> >> + > >> >> +config MALLOC_SIZE > >> >> + hex > >> >> + default 0x800000 > >> >> + prompt "malloc area size" > >> >> +endmenu > >> > > >> >> diff --git a/arch/k1c/lib/board.c b/arch/k1c/lib/board.c > >> >> new file mode 100644 > >> >> index 000000000..d17a32614 > >> >> --- /dev/null > >> >> +++ b/arch/k1c/lib/board.c > >> >> @@ -0,0 +1,20 @@ > >> >> +// SPDX-License-Identifier: GPL-2.0-only > >> >> +/* > >> >> + * Copyright (C) 2019 Kalray Inc. > >> >> + */ > >> >> + > >> >> +#include <common.h> > >> >> +#include <malloc.h> > >> >> +#include <memory.h> > >> >> +#include <asm-generic/memory_layout.h> > >> >> + > >> >> + > >> >> +void __noreturn k1c_start_barebox(void) > >> >> +{ > >> >> + mem_malloc_init((void *)CONFIG_MALLOC_BASE, > >> >> + (void *)(CONFIG_MALLOC_BASE + MALLOC_SIZE - 1)); > >> > > >> > You could extract valid memory from the device tree instead and pick > >> > some memory for malloc there. See of_find_mem() how this can be done. > >> > >> I think we are going to bite our tail here since of_unflatten_dtb does > >> some xzalloc to unflatten the DTB so we need to initialize the malloc > >> allocator before accessing DTB. > > > > of_find_mem() doesn't use of_unflatten_dtb(), it uses libfdt to parse > > the device tree. > > Oh indeed. I looked at it and I see potential problems: > - Stack address/size will still need to be hardcoded because it needs to > be setup before executing C code. mem_malloc_init() actually is C code, so you must have have configured a stack already ;) > - We have multiple memory nodes in our device tree (SMEM and DDR) so we will > probably have to do some quirks to finally find the DDR memory node. Indeed. > - MALLOC_SIZE will still needs to be there On ARM we use roughly half of the available memory for malloc. Maximum is 1GiB anyway, as this is the maximum supported by tlsf malloc. The preferred layout is to put barebox binary and stack to the end of available SDRAM and put the malloc area beneath it. That of course needs a relocatable barebox binary, I don't know if you can generate such an image. If not you have to think of some good base address and put the malloc area whereever it fits. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support 2020-01-16 13:11 ` Sascha Hauer @ 2020-01-16 13:26 ` Clément Leger 2020-01-16 13:34 ` Sascha Hauer 0 siblings, 1 reply; 22+ messages in thread From: Clément Leger @ 2020-01-16 13:26 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List ----- On 16 Jan, 2020, at 14:11, Sascha Hauer s.hauer@pengutronix.de wrote: > On Thu, Jan 16, 2020 at 01:24:41PM +0100, Clément Leger wrote: >> >> ----- On 16 Jan, 2020, at 11:55, Sascha Hauer s.hauer@pengutronix.de wrote: >> >> > On Thu, Jan 16, 2020 at 11:49:31AM +0100, Clément Leger wrote: >> >> Hi Sasha >> >> >> >> ----- On 16 Jan, 2020, at 10:26, Sascha Hauer s.hauer@pengutronix.de wrote: >> >> >> >> > On Wed, Jan 15, 2020 at 11:26:46AM +0100, Clement Leger wrote: >> >> >> +config MALLOC_BASE >> >> >> + hex >> >> >> + default 0x100000000 >> >> >> + >> >> >> +config MALLOC_SIZE >> >> >> + hex >> >> >> + default 0x800000 >> >> >> + prompt "malloc area size" >> >> >> +endmenu >> >> > >> >> >> diff --git a/arch/k1c/lib/board.c b/arch/k1c/lib/board.c >> >> >> new file mode 100644 >> >> >> index 000000000..d17a32614 >> >> >> --- /dev/null >> >> >> +++ b/arch/k1c/lib/board.c >> >> >> @@ -0,0 +1,20 @@ >> >> >> +// SPDX-License-Identifier: GPL-2.0-only >> >> >> +/* >> >> >> + * Copyright (C) 2019 Kalray Inc. >> >> >> + */ >> >> >> + >> >> >> +#include <common.h> >> >> >> +#include <malloc.h> >> >> >> +#include <memory.h> >> >> >> +#include <asm-generic/memory_layout.h> >> >> >> + >> >> >> + >> >> >> +void __noreturn k1c_start_barebox(void) >> >> >> +{ >> >> >> + mem_malloc_init((void *)CONFIG_MALLOC_BASE, >> >> >> + (void *)(CONFIG_MALLOC_BASE + MALLOC_SIZE - 1)); >> >> > >> >> > You could extract valid memory from the device tree instead and pick >> >> > some memory for malloc there. See of_find_mem() how this can be done. >> >> >> >> I think we are going to bite our tail here since of_unflatten_dtb does >> >> some xzalloc to unflatten the DTB so we need to initialize the malloc >> >> allocator before accessing DTB. >> > >> > of_find_mem() doesn't use of_unflatten_dtb(), it uses libfdt to parse >> > the device tree. >> >> Oh indeed. I looked at it and I see potential problems: >> - Stack address/size will still need to be hardcoded because it needs to >> be setup before executing C code. > > mem_malloc_init() actually is C code, so you must have have configured a > stack already ;) Yes of course ! Currently, I was using MALLOC_BASE. this way, stack and malloc were growing at opposite sides. But in fact, maybe the stack could be added into the linker script. This way, we would not have to hardcode it using STACK_BASE. This way it would not depend anymore on malloc base. Do you think it would be ok ? > >> - We have multiple memory nodes in our device tree (SMEM and DDR) so we will >> probably have to do some quirks to finally find the DDR memory node. > > Indeed. > >> - MALLOC_SIZE will still needs to be there > > On ARM we use roughly half of the available memory for malloc. Maximum > is 1GiB anyway, as this is the maximum supported by tlsf malloc. > > The preferred layout is to put barebox binary and stack to the end of > available SDRAM and put the malloc area beneath it. That of course needs > a relocatable barebox binary, I don't know if you can generate such an > image. If not you have to think of some good base address and put the > malloc area whereever it fits. That would be a good solution yes ! But we don't have implemented relocatable support yet. Since we will always have DDR on Coolidge SoC, we can safely assume SDRAM will always be present. So in the meantime, we can have the following memory layout (if stack included in barebox binary): - 0x100000000 -> 128M reserved for Linux loading - 0x100000000 + 128M -> barebox binary - 0x100000000 + 128M + text_size = malloc area start Device tree could then be used to check the available amount of memory. Clément > > Sascha > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support 2020-01-16 13:26 ` Clément Leger @ 2020-01-16 13:34 ` Sascha Hauer 0 siblings, 0 replies; 22+ messages in thread From: Sascha Hauer @ 2020-01-16 13:34 UTC (permalink / raw) To: Clément Leger; +Cc: Barebox List On Thu, Jan 16, 2020 at 02:26:13PM +0100, Clément Leger wrote: > > > ----- On 16 Jan, 2020, at 14:11, Sascha Hauer s.hauer@pengutronix.de wrote: > > > On Thu, Jan 16, 2020 at 01:24:41PM +0100, Clément Leger wrote: > >> > >> ----- On 16 Jan, 2020, at 11:55, Sascha Hauer s.hauer@pengutronix.de wrote: > >> > >> > On Thu, Jan 16, 2020 at 11:49:31AM +0100, Clément Leger wrote: > >> >> Hi Sasha > >> >> > >> >> ----- On 16 Jan, 2020, at 10:26, Sascha Hauer s.hauer@pengutronix.de wrote: > >> >> > >> >> > On Wed, Jan 15, 2020 at 11:26:46AM +0100, Clement Leger wrote: > >> >> >> +config MALLOC_BASE > >> >> >> + hex > >> >> >> + default 0x100000000 > >> >> >> + > >> >> >> +config MALLOC_SIZE > >> >> >> + hex > >> >> >> + default 0x800000 > >> >> >> + prompt "malloc area size" > >> >> >> +endmenu > >> >> > > >> >> >> diff --git a/arch/k1c/lib/board.c b/arch/k1c/lib/board.c > >> >> >> new file mode 100644 > >> >> >> index 000000000..d17a32614 > >> >> >> --- /dev/null > >> >> >> +++ b/arch/k1c/lib/board.c > >> >> >> @@ -0,0 +1,20 @@ > >> >> >> +// SPDX-License-Identifier: GPL-2.0-only > >> >> >> +/* > >> >> >> + * Copyright (C) 2019 Kalray Inc. > >> >> >> + */ > >> >> >> + > >> >> >> +#include <common.h> > >> >> >> +#include <malloc.h> > >> >> >> +#include <memory.h> > >> >> >> +#include <asm-generic/memory_layout.h> > >> >> >> + > >> >> >> + > >> >> >> +void __noreturn k1c_start_barebox(void) > >> >> >> +{ > >> >> >> + mem_malloc_init((void *)CONFIG_MALLOC_BASE, > >> >> >> + (void *)(CONFIG_MALLOC_BASE + MALLOC_SIZE - 1)); > >> >> > > >> >> > You could extract valid memory from the device tree instead and pick > >> >> > some memory for malloc there. See of_find_mem() how this can be done. > >> >> > >> >> I think we are going to bite our tail here since of_unflatten_dtb does > >> >> some xzalloc to unflatten the DTB so we need to initialize the malloc > >> >> allocator before accessing DTB. > >> > > >> > of_find_mem() doesn't use of_unflatten_dtb(), it uses libfdt to parse > >> > the device tree. > >> > >> Oh indeed. I looked at it and I see potential problems: > >> - Stack address/size will still need to be hardcoded because it needs to > >> be setup before executing C code. > > > > mem_malloc_init() actually is C code, so you must have have configured a > > stack already ;) > > Yes of course ! Currently, I was using MALLOC_BASE. this way, stack and > malloc were growing at opposite sides. > > But in fact, maybe the stack could be added into the linker script. This way, > we would not have to hardcode it using STACK_BASE. > This way it would not depend anymore on malloc base. > > Do you think it would be ok ? Yes, that sounds good. > > > > >> - We have multiple memory nodes in our device tree (SMEM and DDR) so we will > >> probably have to do some quirks to finally find the DDR memory node. > > > > Indeed. > > > >> - MALLOC_SIZE will still needs to be there > > > > On ARM we use roughly half of the available memory for malloc. Maximum > > is 1GiB anyway, as this is the maximum supported by tlsf malloc. > > > > The preferred layout is to put barebox binary and stack to the end of > > available SDRAM and put the malloc area beneath it. That of course needs > > a relocatable barebox binary, I don't know if you can generate such an > > image. If not you have to think of some good base address and put the > > malloc area whereever it fits. > > That would be a good solution yes ! But we don't have implemented relocatable > support yet. > Since we will always have DDR on Coolidge SoC, we can safely assume SDRAM > will always be present. > So in the meantime, we can have the following memory layout (if stack included > in barebox binary): > > - 0x100000000 -> 128M reserved for Linux loading > - 0x100000000 + 128M -> barebox binary > - 0x100000000 + 128M + text_size = malloc area start > > Device tree could then be used to check the available amount of memory. With todays multi gigabyte RAM sizes this approach is fine. In the old days when memory was sparse it was painful when barebox ended up somewhere in the middle of SDRAM and divided the usable memory size. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 2/5] k1c: Add processor definitions 2020-01-15 10:26 [PATCH 0/5] Add support for Kalray k1c core Clement Leger 2020-01-15 10:26 ` [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support Clement Leger @ 2020-01-15 10:26 ` Clement Leger 2020-01-15 10:26 ` [PATCH 3/5] k1c: Add support for device tree Clement Leger ` (4 subsequent siblings) 6 siblings, 0 replies; 22+ messages in thread From: Clement Leger @ 2020-01-15 10:26 UTC (permalink / raw) To: barebox, Sascha Hauer; +Cc: Clement Leger This file is generated from processor description and is used to access and modify processor registers. Signed-off-by: Clement Leger <cleger@kalray.eu> --- arch/k1c/include/asm/sfr_defs.h | 5029 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 5029 insertions(+) create mode 100644 arch/k1c/include/asm/sfr_defs.h diff --git a/arch/k1c/include/asm/sfr_defs.h b/arch/k1c/include/asm/sfr_defs.h new file mode 100644 index 000000000..4b9936fed --- /dev/null +++ b/arch/k1c/include/asm/sfr_defs.h @@ -0,0 +1,5029 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_K1C_SFR_DEFS_H +#define _ASM_K1C_SFR_DEFS_H + +#include <linux/const.h> + +#define _ULL(X) _AC(X, ULL) + +/* Register file indices */ +#define K1C_SFR_PC 0 /* Program Counter $pc $s0 */ +#define K1C_SFR_PS 1 /* Processor State $ps $s1 */ +#define K1C_SFR_PCR 2 /* Processing Identification $pcr $s2 */ +#define K1C_SFR_RA 3 /* Return Address $ra $s3 */ +#define K1C_SFR_CS 4 /* Compute Status $cs $s4 */ +#define K1C_SFR_CSIT 5 /* Compute Status arithmetic interrupt $csit $s5 */ +#define K1C_SFR_AESPC 6 /* Arithmetic Exception Saved PC $aespc $s6 */ +#define K1C_SFR_LS 7 /* Loop Start Address $ls $s7 */ +#define K1C_SFR_LE 8 /* Loop Exit Address $le $s8 */ +#define K1C_SFR_LC 9 /* Loop Counter $lc $s9 */ +#define K1C_SFR_IPE 10 /* Inter Processor Event $ipe $s10 */ +#define K1C_SFR_MEN 11 /* Misc External Notifications $men $s11 */ +#define K1C_SFR_PMC 12 /* Performance Monitor Control $pmc $s12 */ +#define K1C_SFR_PM0 13 /* Performance Monitor 0 $pm0 $s13 */ +#define K1C_SFR_PM1 14 /* Performance Monitor 1 $pm1 $s14 */ +#define K1C_SFR_PM2 15 /* Performance Monitor 2 $pm2 $s15 */ +#define K1C_SFR_PM3 16 /* Performance Monitor 3 $pm3 $s16 */ +#define K1C_SFR_PMSA 17 /* Performance Monitor Saved Address $pmsa $s17 */ +#define K1C_SFR_TCR 18 /* Timer Control $tcr $s18 */ +#define K1C_SFR_T0V 19 /* Timer 0 value $t0v $s19 */ +#define K1C_SFR_T1V 20 /* Timer 1 value $t1v $s20 */ +#define K1C_SFR_T0R 21 /* Timer 0 reload value $t0r $s21 */ +#define K1C_SFR_T1R 22 /* Timer 1 reload value $t1r $s22 */ +#define K1C_SFR_WDV 23 /* Watchdog Value $wdv $s23 */ +#define K1C_SFR_WDR 24 /* Watchdog Reload $wdr $s24 */ +#define K1C_SFR_ILE 25 /* Interrupt Line Enable $ile $s25 */ +#define K1C_SFR_ILL 26 /* Interrupt Line Level $ill $s26 */ +#define K1C_SFR_ILR 27 /* Interrupt Line Request $ilr $s27 */ +#define K1C_SFR_MMC 28 /* Memory Management Control $mmc $s28 */ +#define K1C_SFR_TEL 29 /* TLB Entry Low $tel $s29 */ +#define K1C_SFR_TEH 30 /* TLB Entry High $teh $s30 */ +#define K1C_SFR_SYO 32 /* Syscall Owners $syo $s32 */ +#define K1C_SFR_HTO 33 /* Hardware Trap Owners $hto $s33 */ +#define K1C_SFR_ITO 34 /* Interrupt Owners $ito $s34 */ +#define K1C_SFR_DO 35 /* Debug Owners $do $s35 */ +#define K1C_SFR_MO 36 /* Miscellaneous Owners $mo $s36 */ +#define K1C_SFR_PSO 37 /* PS register fields Owners $pso $s37 */ +#define K1C_SFR_DC 40 /* OCE (Debug) Control $dc $s40 */ +#define K1C_SFR_DBA0 41 /* Breakpoint Address 0 $dba0 $s41 */ +#define K1C_SFR_DBA1 42 /* Breakpoint Address 1 $dba1 $s42 */ +#define K1C_SFR_DWA0 43 /* Watchpoint Address 0 $dwa0 $s43 */ +#define K1C_SFR_DWA1 44 /* Watchpoint Address 1 $dwa1 $s44 */ +#define K1C_SFR_MES 45 /* Memory Error Status $mes $s45 */ +#define K1C_SFR_WS 46 /* Wake-Up Status $ws $s46 */ +#define K1C_SFR_SPC_PL0 64 /* Shadow PC PL 0 $spc_pl0 $s64 */ +#define K1C_SFR_SPC_PL1 65 /* Shadow PC PL 1 $spc_pl1 $s65 */ +#define K1C_SFR_SPC_PL2 66 /* Shadow PC PL 2 $spc_pl2 $s66 */ +#define K1C_SFR_SPC_PL3 67 /* Shadow PC PL 3 $spc_pl3 $s67 */ +#define K1C_SFR_SPS_PL0 68 /* Shadow PS PL 0 $sps_pl0 $s68 */ +#define K1C_SFR_SPS_PL1 69 /* Shadow PS PL 1 $sps_pl1 $s69 */ +#define K1C_SFR_SPS_PL2 70 /* Shadow PS PL 2 $sps_pl2 $s70 */ +#define K1C_SFR_SPS_PL3 71 /* Shadow PS PL 3 $sps_pl3 $s71 */ +#define K1C_SFR_EA_PL0 72 /* Effective Address PL0 $ea_pl0 $s72 */ +#define K1C_SFR_EA_PL1 73 /* Effective Address PL1 $ea_pl1 $s73 */ +#define K1C_SFR_EA_PL2 74 /* Effective Address PL2 $ea_pl2 $s74 */ +#define K1C_SFR_EA_PL3 75 /* Effective Address PL3 $ea_pl3 $s75 */ +#define K1C_SFR_EV_PL0 76 /* Exception Vector PL 0 $ev_pl0 $s76 */ +#define K1C_SFR_EV_PL1 77 /* Exception Vector PL 1 $ev_pl1 $s77 */ +#define K1C_SFR_EV_PL2 78 /* Exception Vector PL 2 $ev_pl2 $s78 */ +#define K1C_SFR_EV_PL3 79 /* Exception Vector PL 3 $ev_pl3 $s79 */ +#define K1C_SFR_SR_PL0 80 /* System Register PL 0 $sr_pl0 $s80 */ +#define K1C_SFR_SR_PL1 81 /* System Register PL 1 $sr_pl1 $s81 */ +#define K1C_SFR_SR_PL2 82 /* System Register PL 2 $sr_pl2 $s82 */ +#define K1C_SFR_SR_PL3 83 /* System Register PL 3 $sr_pl3 $s83 */ +#define K1C_SFR_ES_PL0 84 /* Exception Syndrome PL 0 $es_pl0 $s84 */ +#define K1C_SFR_ES_PL1 85 /* Exception Syndrome PL 1 $es_pl1 $s85 */ +#define K1C_SFR_ES_PL2 86 /* Exception Syndrome PL 2 $es_pl2 $s86 */ +#define K1C_SFR_ES_PL3 87 /* Exception Syndrome PL 3 $es_pl3 $s87 */ +#define K1C_SFR_SYOW 96 /* Alias to SYO register $syow $s96 */ +#define K1C_SFR_HTOW 97 /* Alias to HTO register $htow $s97 */ +#define K1C_SFR_ITOW 98 /* Alias to ITO register $itow $s98 */ +#define K1C_SFR_DOW 99 /* Alias to DO register $dow $s99 */ +#define K1C_SFR_MOW 100 /* Alias to MO register $mow $s100 */ +#define K1C_SFR_PSOW 101 /* Alias to PSO register $psow $s101 */ +#define K1C_SFR_SPC 128 /* Shadow PC alias on SPC_PL<i> $spc $s128 */ +#define K1C_SFR_SPS 132 /* Shadow PS alias on PS_PL<i> $sps $s132 */ +#define K1C_SFR_EA 136 /* Effective Address alias on EA_PL<i> $ea $s136 */ +#define K1C_SFR_EV 140 /* Exception Vector alias on EV_PL<i> $ev $s140 */ +#define K1C_SFR_SR 144 /* System Register alias on SR_PL<i> $sr $s144 */ +#define K1C_SFR_ES 148 /* Exception Syndrome alias on ES_PL<i> $es $s148 */ +#define K1C_SFR_VSFR0 256 /* Virtual SFR 0 $vsfr0 $s256 */ +#define K1C_SFR_VSFR1 257 /* Virtual SFR 1 $vsfr1 $s257 */ +#define K1C_SFR_VSFR2 258 /* Virtual SFR 2 $vsfr2 $s258 */ +#define K1C_SFR_VSFR3 259 /* Virtual SFR 3 $vsfr3 $s259 */ +#define K1C_SFR_VSFR4 260 /* Virtual SFR 4 $vsfr4 $s260 */ +#define K1C_SFR_VSFR5 261 /* Virtual SFR 5 $vsfr5 $s261 */ +#define K1C_SFR_VSFR6 262 /* Virtual SFR 6 $vsfr6 $s262 */ +#define K1C_SFR_VSFR7 263 /* Virtual SFR 7 $vsfr7 $s263 */ +#define K1C_SFR_VSFR8 264 /* Virtual SFR 8 $vsfr8 $s264 */ +#define K1C_SFR_VSFR9 265 /* Virtual SFR 9 $vsfr9 $s265 */ +#define K1C_SFR_VSFR10 266 /* Virtual SFR 10 $vsfr10 $s266 */ +#define K1C_SFR_VSFR11 267 /* Virtual SFR 11 $vsfr11 $s267 */ +#define K1C_SFR_VSFR12 268 /* Virtual SFR 12 $vsfr12 $s268 */ +#define K1C_SFR_VSFR13 269 /* Virtual SFR 13 $vsfr13 $s269 */ +#define K1C_SFR_VSFR14 270 /* Virtual SFR 14 $vsfr14 $s270 */ +#define K1C_SFR_VSFR15 271 /* Virtual SFR 15 $vsfr15 $s271 */ +#define K1C_SFR_VSFR16 272 /* Virtual SFR 16 $vsfr16 $s272 */ +#define K1C_SFR_VSFR17 273 /* Virtual SFR 17 $vsfr17 $s273 */ +#define K1C_SFR_VSFR18 274 /* Virtual SFR 18 $vsfr18 $s274 */ +#define K1C_SFR_VSFR19 275 /* Virtual SFR 19 $vsfr19 $s275 */ +#define K1C_SFR_VSFR20 276 /* Virtual SFR 20 $vsfr20 $s276 */ +#define K1C_SFR_VSFR21 277 /* Virtual SFR 21 $vsfr21 $s277 */ +#define K1C_SFR_VSFR22 278 /* Virtual SFR 22 $vsfr22 $s278 */ +#define K1C_SFR_VSFR23 279 /* Virtual SFR 23 $vsfr23 $s279 */ +#define K1C_SFR_VSFR24 280 /* Virtual SFR 24 $vsfr24 $s280 */ +#define K1C_SFR_VSFR25 281 /* Virtual SFR 25 $vsfr25 $s281 */ +#define K1C_SFR_VSFR26 282 /* Virtual SFR 26 $vsfr26 $s282 */ +#define K1C_SFR_VSFR27 283 /* Virtual SFR 27 $vsfr27 $s283 */ +#define K1C_SFR_VSFR28 284 /* Virtual SFR 28 $vsfr28 $s284 */ +#define K1C_SFR_VSFR29 285 /* Virtual SFR 29 $vsfr29 $s285 */ +#define K1C_SFR_VSFR30 286 /* Virtual SFR 30 $vsfr30 $s286 */ +#define K1C_SFR_VSFR31 287 /* Virtual SFR 31 $vsfr31 $s287 */ +#define K1C_SFR_VSFR32 288 /* Virtual SFR 32 $vsfr32 $s288 */ +#define K1C_SFR_VSFR33 289 /* Virtual SFR 33 $vsfr33 $s289 */ +#define K1C_SFR_VSFR34 290 /* Virtual SFR 34 $vsfr34 $s290 */ +#define K1C_SFR_VSFR35 291 /* Virtual SFR 35 $vsfr35 $s291 */ +#define K1C_SFR_VSFR36 292 /* Virtual SFR 36 $vsfr36 $s292 */ +#define K1C_SFR_VSFR37 293 /* Virtual SFR 37 $vsfr37 $s293 */ +#define K1C_SFR_VSFR38 294 /* Virtual SFR 38 $vsfr38 $s294 */ +#define K1C_SFR_VSFR39 295 /* Virtual SFR 39 $vsfr39 $s295 */ +#define K1C_SFR_VSFR40 296 /* Virtual SFR 40 $vsfr40 $s296 */ +#define K1C_SFR_VSFR41 297 /* Virtual SFR 41 $vsfr41 $s297 */ +#define K1C_SFR_VSFR42 298 /* Virtual SFR 42 $vsfr42 $s298 */ +#define K1C_SFR_VSFR43 299 /* Virtual SFR 43 $vsfr43 $s299 */ +#define K1C_SFR_VSFR44 300 /* Virtual SFR 44 $vsfr44 $s300 */ +#define K1C_SFR_VSFR45 301 /* Virtual SFR 45 $vsfr45 $s301 */ +#define K1C_SFR_VSFR46 302 /* Virtual SFR 46 $vsfr46 $s302 */ +#define K1C_SFR_VSFR47 303 /* Virtual SFR 47 $vsfr47 $s303 */ +#define K1C_SFR_VSFR48 304 /* Virtual SFR 48 $vsfr48 $s304 */ +#define K1C_SFR_VSFR49 305 /* Virtual SFR 49 $vsfr49 $s305 */ +#define K1C_SFR_VSFR50 306 /* Virtual SFR 50 $vsfr50 $s306 */ +#define K1C_SFR_VSFR51 307 /* Virtual SFR 51 $vsfr51 $s307 */ +#define K1C_SFR_VSFR52 308 /* Virtual SFR 52 $vsfr52 $s308 */ +#define K1C_SFR_VSFR53 309 /* Virtual SFR 53 $vsfr53 $s309 */ +#define K1C_SFR_VSFR54 310 /* Virtual SFR 54 $vsfr54 $s310 */ +#define K1C_SFR_VSFR55 311 /* Virtual SFR 55 $vsfr55 $s311 */ +#define K1C_SFR_VSFR56 312 /* Virtual SFR 56 $vsfr56 $s312 */ +#define K1C_SFR_VSFR57 313 /* Virtual SFR 57 $vsfr57 $s313 */ +#define K1C_SFR_VSFR58 314 /* Virtual SFR 58 $vsfr58 $s314 */ +#define K1C_SFR_VSFR59 315 /* Virtual SFR 59 $vsfr59 $s315 */ +#define K1C_SFR_VSFR60 316 /* Virtual SFR 60 $vsfr60 $s316 */ +#define K1C_SFR_VSFR61 317 /* Virtual SFR 61 $vsfr61 $s317 */ +#define K1C_SFR_VSFR62 318 /* Virtual SFR 62 $vsfr62 $s318 */ +#define K1C_SFR_VSFR63 319 /* Virtual SFR 63 $vsfr63 $s319 */ +#define K1C_SFR_VSFR64 320 /* Virtual SFR 64 $vsfr64 $s320 */ +#define K1C_SFR_VSFR65 321 /* Virtual SFR 65 $vsfr65 $s321 */ +#define K1C_SFR_VSFR66 322 /* Virtual SFR 66 $vsfr66 $s322 */ +#define K1C_SFR_VSFR67 323 /* Virtual SFR 67 $vsfr67 $s323 */ +#define K1C_SFR_VSFR68 324 /* Virtual SFR 68 $vsfr68 $s324 */ +#define K1C_SFR_VSFR69 325 /* Virtual SFR 69 $vsfr69 $s325 */ +#define K1C_SFR_VSFR70 326 /* Virtual SFR 70 $vsfr70 $s326 */ +#define K1C_SFR_VSFR71 327 /* Virtual SFR 71 $vsfr71 $s327 */ +#define K1C_SFR_VSFR72 328 /* Virtual SFR 72 $vsfr72 $s328 */ +#define K1C_SFR_VSFR73 329 /* Virtual SFR 73 $vsfr73 $s329 */ +#define K1C_SFR_VSFR74 330 /* Virtual SFR 74 $vsfr74 $s330 */ +#define K1C_SFR_VSFR75 331 /* Virtual SFR 75 $vsfr75 $s331 */ +#define K1C_SFR_VSFR76 332 /* Virtual SFR 76 $vsfr76 $s332 */ +#define K1C_SFR_VSFR77 333 /* Virtual SFR 77 $vsfr77 $s333 */ +#define K1C_SFR_VSFR78 334 /* Virtual SFR 78 $vsfr78 $s334 */ +#define K1C_SFR_VSFR79 335 /* Virtual SFR 79 $vsfr79 $s335 */ +#define K1C_SFR_VSFR80 336 /* Virtual SFR 80 $vsfr80 $s336 */ +#define K1C_SFR_VSFR81 337 /* Virtual SFR 81 $vsfr81 $s337 */ +#define K1C_SFR_VSFR82 338 /* Virtual SFR 82 $vsfr82 $s338 */ +#define K1C_SFR_VSFR83 339 /* Virtual SFR 83 $vsfr83 $s339 */ +#define K1C_SFR_VSFR84 340 /* Virtual SFR 84 $vsfr84 $s340 */ +#define K1C_SFR_VSFR85 341 /* Virtual SFR 85 $vsfr85 $s341 */ +#define K1C_SFR_VSFR86 342 /* Virtual SFR 86 $vsfr86 $s342 */ +#define K1C_SFR_VSFR87 343 /* Virtual SFR 87 $vsfr87 $s343 */ +#define K1C_SFR_VSFR88 344 /* Virtual SFR 88 $vsfr88 $s344 */ +#define K1C_SFR_VSFR89 345 /* Virtual SFR 89 $vsfr89 $s345 */ +#define K1C_SFR_VSFR90 346 /* Virtual SFR 90 $vsfr90 $s346 */ +#define K1C_SFR_VSFR91 347 /* Virtual SFR 91 $vsfr91 $s347 */ +#define K1C_SFR_VSFR92 348 /* Virtual SFR 92 $vsfr92 $s348 */ +#define K1C_SFR_VSFR93 349 /* Virtual SFR 93 $vsfr93 $s349 */ +#define K1C_SFR_VSFR94 350 /* Virtual SFR 94 $vsfr94 $s350 */ +#define K1C_SFR_VSFR95 351 /* Virtual SFR 95 $vsfr95 $s351 */ +#define K1C_SFR_VSFR96 352 /* Virtual SFR 96 $vsfr96 $s352 */ +#define K1C_SFR_VSFR97 353 /* Virtual SFR 97 $vsfr97 $s353 */ +#define K1C_SFR_VSFR98 354 /* Virtual SFR 98 $vsfr98 $s354 */ +#define K1C_SFR_VSFR99 355 /* Virtual SFR 99 $vsfr99 $s355 */ +#define K1C_SFR_VSFR100 356 /* Virtual SFR 100 $vsfr100 $s356 */ +#define K1C_SFR_VSFR101 357 /* Virtual SFR 101 $vsfr101 $s357 */ +#define K1C_SFR_VSFR102 358 /* Virtual SFR 102 $vsfr102 $s358 */ +#define K1C_SFR_VSFR103 359 /* Virtual SFR 103 $vsfr103 $s359 */ +#define K1C_SFR_VSFR104 360 /* Virtual SFR 104 $vsfr104 $s360 */ +#define K1C_SFR_VSFR105 361 /* Virtual SFR 105 $vsfr105 $s361 */ +#define K1C_SFR_VSFR106 362 /* Virtual SFR 106 $vsfr106 $s362 */ +#define K1C_SFR_VSFR107 363 /* Virtual SFR 107 $vsfr107 $s363 */ +#define K1C_SFR_VSFR108 364 /* Virtual SFR 108 $vsfr108 $s364 */ +#define K1C_SFR_VSFR109 365 /* Virtual SFR 109 $vsfr109 $s365 */ +#define K1C_SFR_VSFR110 366 /* Virtual SFR 110 $vsfr110 $s366 */ +#define K1C_SFR_VSFR111 367 /* Virtual SFR 111 $vsfr111 $s367 */ +#define K1C_SFR_VSFR112 368 /* Virtual SFR 112 $vsfr112 $s368 */ +#define K1C_SFR_VSFR113 369 /* Virtual SFR 113 $vsfr113 $s369 */ +#define K1C_SFR_VSFR114 370 /* Virtual SFR 114 $vsfr114 $s370 */ +#define K1C_SFR_VSFR115 371 /* Virtual SFR 115 $vsfr115 $s371 */ +#define K1C_SFR_VSFR116 372 /* Virtual SFR 116 $vsfr116 $s372 */ +#define K1C_SFR_VSFR117 373 /* Virtual SFR 117 $vsfr117 $s373 */ +#define K1C_SFR_VSFR118 374 /* Virtual SFR 118 $vsfr118 $s374 */ +#define K1C_SFR_VSFR119 375 /* Virtual SFR 119 $vsfr119 $s375 */ +#define K1C_SFR_VSFR120 376 /* Virtual SFR 120 $vsfr120 $s376 */ +#define K1C_SFR_VSFR121 377 /* Virtual SFR 121 $vsfr121 $s377 */ +#define K1C_SFR_VSFR122 378 /* Virtual SFR 122 $vsfr122 $s378 */ +#define K1C_SFR_VSFR123 379 /* Virtual SFR 123 $vsfr123 $s379 */ +#define K1C_SFR_VSFR124 380 /* Virtual SFR 124 $vsfr124 $s380 */ +#define K1C_SFR_VSFR125 381 /* Virtual SFR 125 $vsfr125 $s381 */ +#define K1C_SFR_VSFR126 382 /* Virtual SFR 126 $vsfr126 $s382 */ +#define K1C_SFR_VSFR127 383 /* Virtual SFR 127 $vsfr127 $s383 */ +#define K1C_SFR_VSFR128 384 /* Virtual SFR 128 $vsfr128 $s384 */ +#define K1C_SFR_VSFR129 385 /* Virtual SFR 129 $vsfr129 $s385 */ +#define K1C_SFR_VSFR130 386 /* Virtual SFR 130 $vsfr130 $s386 */ +#define K1C_SFR_VSFR131 387 /* Virtual SFR 131 $vsfr131 $s387 */ +#define K1C_SFR_VSFR132 388 /* Virtual SFR 132 $vsfr132 $s388 */ +#define K1C_SFR_VSFR133 389 /* Virtual SFR 133 $vsfr133 $s389 */ +#define K1C_SFR_VSFR134 390 /* Virtual SFR 134 $vsfr134 $s390 */ +#define K1C_SFR_VSFR135 391 /* Virtual SFR 135 $vsfr135 $s391 */ +#define K1C_SFR_VSFR136 392 /* Virtual SFR 136 $vsfr136 $s392 */ +#define K1C_SFR_VSFR137 393 /* Virtual SFR 137 $vsfr137 $s393 */ +#define K1C_SFR_VSFR138 394 /* Virtual SFR 138 $vsfr138 $s394 */ +#define K1C_SFR_VSFR139 395 /* Virtual SFR 139 $vsfr139 $s395 */ +#define K1C_SFR_VSFR140 396 /* Virtual SFR 140 $vsfr140 $s396 */ +#define K1C_SFR_VSFR141 397 /* Virtual SFR 141 $vsfr141 $s397 */ +#define K1C_SFR_VSFR142 398 /* Virtual SFR 142 $vsfr142 $s398 */ +#define K1C_SFR_VSFR143 399 /* Virtual SFR 143 $vsfr143 $s399 */ +#define K1C_SFR_VSFR144 400 /* Virtual SFR 144 $vsfr144 $s400 */ +#define K1C_SFR_VSFR145 401 /* Virtual SFR 145 $vsfr145 $s401 */ +#define K1C_SFR_VSFR146 402 /* Virtual SFR 146 $vsfr146 $s402 */ +#define K1C_SFR_VSFR147 403 /* Virtual SFR 147 $vsfr147 $s403 */ +#define K1C_SFR_VSFR148 404 /* Virtual SFR 148 $vsfr148 $s404 */ +#define K1C_SFR_VSFR149 405 /* Virtual SFR 149 $vsfr149 $s405 */ +#define K1C_SFR_VSFR150 406 /* Virtual SFR 150 $vsfr150 $s406 */ +#define K1C_SFR_VSFR151 407 /* Virtual SFR 151 $vsfr151 $s407 */ +#define K1C_SFR_VSFR152 408 /* Virtual SFR 152 $vsfr152 $s408 */ +#define K1C_SFR_VSFR153 409 /* Virtual SFR 153 $vsfr153 $s409 */ +#define K1C_SFR_VSFR154 410 /* Virtual SFR 154 $vsfr154 $s410 */ +#define K1C_SFR_VSFR155 411 /* Virtual SFR 155 $vsfr155 $s411 */ +#define K1C_SFR_VSFR156 412 /* Virtual SFR 156 $vsfr156 $s412 */ +#define K1C_SFR_VSFR157 413 /* Virtual SFR 157 $vsfr157 $s413 */ +#define K1C_SFR_VSFR158 414 /* Virtual SFR 158 $vsfr158 $s414 */ +#define K1C_SFR_VSFR159 415 /* Virtual SFR 159 $vsfr159 $s415 */ +#define K1C_SFR_VSFR160 416 /* Virtual SFR 160 $vsfr160 $s416 */ +#define K1C_SFR_VSFR161 417 /* Virtual SFR 161 $vsfr161 $s417 */ +#define K1C_SFR_VSFR162 418 /* Virtual SFR 162 $vsfr162 $s418 */ +#define K1C_SFR_VSFR163 419 /* Virtual SFR 163 $vsfr163 $s419 */ +#define K1C_SFR_VSFR164 420 /* Virtual SFR 164 $vsfr164 $s420 */ +#define K1C_SFR_VSFR165 421 /* Virtual SFR 165 $vsfr165 $s421 */ +#define K1C_SFR_VSFR166 422 /* Virtual SFR 166 $vsfr166 $s422 */ +#define K1C_SFR_VSFR167 423 /* Virtual SFR 167 $vsfr167 $s423 */ +#define K1C_SFR_VSFR168 424 /* Virtual SFR 168 $vsfr168 $s424 */ +#define K1C_SFR_VSFR169 425 /* Virtual SFR 169 $vsfr169 $s425 */ +#define K1C_SFR_VSFR170 426 /* Virtual SFR 170 $vsfr170 $s426 */ +#define K1C_SFR_VSFR171 427 /* Virtual SFR 171 $vsfr171 $s427 */ +#define K1C_SFR_VSFR172 428 /* Virtual SFR 172 $vsfr172 $s428 */ +#define K1C_SFR_VSFR173 429 /* Virtual SFR 173 $vsfr173 $s429 */ +#define K1C_SFR_VSFR174 430 /* Virtual SFR 174 $vsfr174 $s430 */ +#define K1C_SFR_VSFR175 431 /* Virtual SFR 175 $vsfr175 $s431 */ +#define K1C_SFR_VSFR176 432 /* Virtual SFR 176 $vsfr176 $s432 */ +#define K1C_SFR_VSFR177 433 /* Virtual SFR 177 $vsfr177 $s433 */ +#define K1C_SFR_VSFR178 434 /* Virtual SFR 178 $vsfr178 $s434 */ +#define K1C_SFR_VSFR179 435 /* Virtual SFR 179 $vsfr179 $s435 */ +#define K1C_SFR_VSFR180 436 /* Virtual SFR 180 $vsfr180 $s436 */ +#define K1C_SFR_VSFR181 437 /* Virtual SFR 181 $vsfr181 $s437 */ +#define K1C_SFR_VSFR182 438 /* Virtual SFR 182 $vsfr182 $s438 */ +#define K1C_SFR_VSFR183 439 /* Virtual SFR 183 $vsfr183 $s439 */ +#define K1C_SFR_VSFR184 440 /* Virtual SFR 184 $vsfr184 $s440 */ +#define K1C_SFR_VSFR185 441 /* Virtual SFR 185 $vsfr185 $s441 */ +#define K1C_SFR_VSFR186 442 /* Virtual SFR 186 $vsfr186 $s442 */ +#define K1C_SFR_VSFR187 443 /* Virtual SFR 187 $vsfr187 $s443 */ +#define K1C_SFR_VSFR188 444 /* Virtual SFR 188 $vsfr188 $s444 */ +#define K1C_SFR_VSFR189 445 /* Virtual SFR 189 $vsfr189 $s445 */ +#define K1C_SFR_VSFR190 446 /* Virtual SFR 190 $vsfr190 $s446 */ +#define K1C_SFR_VSFR191 447 /* Virtual SFR 191 $vsfr191 $s447 */ +#define K1C_SFR_VSFR192 448 /* Virtual SFR 192 $vsfr192 $s448 */ +#define K1C_SFR_VSFR193 449 /* Virtual SFR 193 $vsfr193 $s449 */ +#define K1C_SFR_VSFR194 450 /* Virtual SFR 194 $vsfr194 $s450 */ +#define K1C_SFR_VSFR195 451 /* Virtual SFR 195 $vsfr195 $s451 */ +#define K1C_SFR_VSFR196 452 /* Virtual SFR 196 $vsfr196 $s452 */ +#define K1C_SFR_VSFR197 453 /* Virtual SFR 197 $vsfr197 $s453 */ +#define K1C_SFR_VSFR198 454 /* Virtual SFR 198 $vsfr198 $s454 */ +#define K1C_SFR_VSFR199 455 /* Virtual SFR 199 $vsfr199 $s455 */ +#define K1C_SFR_VSFR200 456 /* Virtual SFR 200 $vsfr200 $s456 */ +#define K1C_SFR_VSFR201 457 /* Virtual SFR 201 $vsfr201 $s457 */ +#define K1C_SFR_VSFR202 458 /* Virtual SFR 202 $vsfr202 $s458 */ +#define K1C_SFR_VSFR203 459 /* Virtual SFR 203 $vsfr203 $s459 */ +#define K1C_SFR_VSFR204 460 /* Virtual SFR 204 $vsfr204 $s460 */ +#define K1C_SFR_VSFR205 461 /* Virtual SFR 205 $vsfr205 $s461 */ +#define K1C_SFR_VSFR206 462 /* Virtual SFR 206 $vsfr206 $s462 */ +#define K1C_SFR_VSFR207 463 /* Virtual SFR 207 $vsfr207 $s463 */ +#define K1C_SFR_VSFR208 464 /* Virtual SFR 208 $vsfr208 $s464 */ +#define K1C_SFR_VSFR209 465 /* Virtual SFR 209 $vsfr209 $s465 */ +#define K1C_SFR_VSFR210 466 /* Virtual SFR 210 $vsfr210 $s466 */ +#define K1C_SFR_VSFR211 467 /* Virtual SFR 211 $vsfr211 $s467 */ +#define K1C_SFR_VSFR212 468 /* Virtual SFR 212 $vsfr212 $s468 */ +#define K1C_SFR_VSFR213 469 /* Virtual SFR 213 $vsfr213 $s469 */ +#define K1C_SFR_VSFR214 470 /* Virtual SFR 214 $vsfr214 $s470 */ +#define K1C_SFR_VSFR215 471 /* Virtual SFR 215 $vsfr215 $s471 */ +#define K1C_SFR_VSFR216 472 /* Virtual SFR 216 $vsfr216 $s472 */ +#define K1C_SFR_VSFR217 473 /* Virtual SFR 217 $vsfr217 $s473 */ +#define K1C_SFR_VSFR218 474 /* Virtual SFR 218 $vsfr218 $s474 */ +#define K1C_SFR_VSFR219 475 /* Virtual SFR 219 $vsfr219 $s475 */ +#define K1C_SFR_VSFR220 476 /* Virtual SFR 220 $vsfr220 $s476 */ +#define K1C_SFR_VSFR221 477 /* Virtual SFR 221 $vsfr221 $s477 */ +#define K1C_SFR_VSFR222 478 /* Virtual SFR 222 $vsfr222 $s478 */ +#define K1C_SFR_VSFR223 479 /* Virtual SFR 223 $vsfr223 $s479 */ +#define K1C_SFR_VSFR224 480 /* Virtual SFR 224 $vsfr224 $s480 */ +#define K1C_SFR_VSFR225 481 /* Virtual SFR 225 $vsfr225 $s481 */ +#define K1C_SFR_VSFR226 482 /* Virtual SFR 226 $vsfr226 $s482 */ +#define K1C_SFR_VSFR227 483 /* Virtual SFR 227 $vsfr227 $s483 */ +#define K1C_SFR_VSFR228 484 /* Virtual SFR 228 $vsfr228 $s484 */ +#define K1C_SFR_VSFR229 485 /* Virtual SFR 229 $vsfr229 $s485 */ +#define K1C_SFR_VSFR230 486 /* Virtual SFR 230 $vsfr230 $s486 */ +#define K1C_SFR_VSFR231 487 /* Virtual SFR 231 $vsfr231 $s487 */ +#define K1C_SFR_VSFR232 488 /* Virtual SFR 232 $vsfr232 $s488 */ +#define K1C_SFR_VSFR233 489 /* Virtual SFR 233 $vsfr233 $s489 */ +#define K1C_SFR_VSFR234 490 /* Virtual SFR 234 $vsfr234 $s490 */ +#define K1C_SFR_VSFR235 491 /* Virtual SFR 235 $vsfr235 $s491 */ +#define K1C_SFR_VSFR236 492 /* Virtual SFR 236 $vsfr236 $s492 */ +#define K1C_SFR_VSFR237 493 /* Virtual SFR 237 $vsfr237 $s493 */ +#define K1C_SFR_VSFR238 494 /* Virtual SFR 238 $vsfr238 $s494 */ +#define K1C_SFR_VSFR239 495 /* Virtual SFR 239 $vsfr239 $s495 */ +#define K1C_SFR_VSFR240 496 /* Virtual SFR 240 $vsfr240 $s496 */ +#define K1C_SFR_VSFR241 497 /* Virtual SFR 241 $vsfr241 $s497 */ +#define K1C_SFR_VSFR242 498 /* Virtual SFR 242 $vsfr242 $s498 */ +#define K1C_SFR_VSFR243 499 /* Virtual SFR 243 $vsfr243 $s499 */ +#define K1C_SFR_VSFR244 500 /* Virtual SFR 244 $vsfr244 $s500 */ +#define K1C_SFR_VSFR245 501 /* Virtual SFR 245 $vsfr245 $s501 */ +#define K1C_SFR_VSFR246 502 /* Virtual SFR 246 $vsfr246 $s502 */ +#define K1C_SFR_VSFR247 503 /* Virtual SFR 247 $vsfr247 $s503 */ +#define K1C_SFR_VSFR248 504 /* Virtual SFR 248 $vsfr248 $s504 */ +#define K1C_SFR_VSFR249 505 /* Virtual SFR 249 $vsfr249 $s505 */ +#define K1C_SFR_VSFR250 506 /* Virtual SFR 250 $vsfr250 $s506 */ +#define K1C_SFR_VSFR251 507 /* Virtual SFR 251 $vsfr251 $s507 */ +#define K1C_SFR_VSFR252 508 /* Virtual SFR 252 $vsfr252 $s508 */ +#define K1C_SFR_VSFR253 509 /* Virtual SFR 253 $vsfr253 $s509 */ +#define K1C_SFR_VSFR254 510 /* Virtual SFR 254 $vsfr254 $s510 */ +#define K1C_SFR_VSFR255 511 /* Virtual SFR 255 $vsfr255 $s511 */ + +/* Register field masks */ + +#define K1C_SFR_MEN_MEN_MASK _ULL(0xffff) /* Miscellaneous External Notifications */ +#define K1C_SFR_MEN_MEN_SHIFT 0 +#define K1C_SFR_MEN_MEN_WIDTH 16 +#define K1C_SFR_MEN_MEN_WFXL_MASK _ULL(0xffff) +#define K1C_SFR_MEN_MEN_WFXL_CLEAR _ULL(0xffff) +#define K1C_SFR_MEN_MEN_WFXL_SET _ULL(0xffff00000000) + +#define K1C_SFR_SYO_Q0_MASK _ULL(0x3) /* Quarter 0 syscalls 0 to 1023 owner */ +#define K1C_SFR_SYO_Q0_SHIFT 0 +#define K1C_SFR_SYO_Q0_WIDTH 2 +#define K1C_SFR_SYO_Q0_WFXL_MASK _ULL(0x3) +#define K1C_SFR_SYO_Q0_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_SYO_Q0_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_SYO_Q1_MASK _ULL(0xc) /* Quarter 1 syscalls 1024 to 2047 owner */ +#define K1C_SFR_SYO_Q1_SHIFT 2 +#define K1C_SFR_SYO_Q1_WIDTH 2 +#define K1C_SFR_SYO_Q1_WFXL_MASK _ULL(0xc) +#define K1C_SFR_SYO_Q1_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_SYO_Q1_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_SYO_Q2_MASK _ULL(0x30) /* Quarter 2 syscalls 2048 to 3071 owner */ +#define K1C_SFR_SYO_Q2_SHIFT 4 +#define K1C_SFR_SYO_Q2_WIDTH 2 +#define K1C_SFR_SYO_Q2_WFXL_MASK _ULL(0x30) +#define K1C_SFR_SYO_Q2_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_SYO_Q2_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_SYO_Q3_MASK _ULL(0xc0) /* Quarter 3 syscalls 3072 to 4095 owner */ +#define K1C_SFR_SYO_Q3_SHIFT 6 +#define K1C_SFR_SYO_Q3_WIDTH 2 +#define K1C_SFR_SYO_Q3_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_SYO_Q3_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_SYO_Q3_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_SYOW_Q0_MASK _ULL(0x3) /* Quarter 0 syscalls 0 to 1023 owner */ +#define K1C_SFR_SYOW_Q0_SHIFT 0 +#define K1C_SFR_SYOW_Q0_WIDTH 2 +#define K1C_SFR_SYOW_Q0_WFXL_MASK _ULL(0x3) +#define K1C_SFR_SYOW_Q0_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_SYOW_Q0_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_SYOW_Q1_MASK _ULL(0xc) /* Quarter 1 syscalls 1024 to 2047 owner */ +#define K1C_SFR_SYOW_Q1_SHIFT 2 +#define K1C_SFR_SYOW_Q1_WIDTH 2 +#define K1C_SFR_SYOW_Q1_WFXL_MASK _ULL(0xc) +#define K1C_SFR_SYOW_Q1_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_SYOW_Q1_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_SYOW_Q2_MASK _ULL(0x30) /* Quarter 2 syscalls 2048 to 3071 owner */ +#define K1C_SFR_SYOW_Q2_SHIFT 4 +#define K1C_SFR_SYOW_Q2_WIDTH 2 +#define K1C_SFR_SYOW_Q2_WFXL_MASK _ULL(0x30) +#define K1C_SFR_SYOW_Q2_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_SYOW_Q2_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_SYOW_Q3_MASK _ULL(0xc0) /* Quarter 3 syscalls 3072 to 4095 owner */ +#define K1C_SFR_SYOW_Q3_SHIFT 6 +#define K1C_SFR_SYOW_Q3_WIDTH 2 +#define K1C_SFR_SYOW_Q3_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_SYOW_Q3_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_SYOW_Q3_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_HTO_OPC_MASK _ULL(0x3) /* OPCode trap owner */ +#define K1C_SFR_HTO_OPC_SHIFT 0 +#define K1C_SFR_HTO_OPC_WIDTH 2 +#define K1C_SFR_HTO_OPC_WFXL_MASK _ULL(0x3) +#define K1C_SFR_HTO_OPC_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_HTO_OPC_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_HTO_DMIS_MASK _ULL(0xc) /* Data MISalign access trap owner */ +#define K1C_SFR_HTO_DMIS_SHIFT 2 +#define K1C_SFR_HTO_DMIS_WIDTH 2 +#define K1C_SFR_HTO_DMIS_WFXL_MASK _ULL(0xc) +#define K1C_SFR_HTO_DMIS_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_HTO_DMIS_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_HTO_PSYS_MASK _ULL(0x30) /* Program System Error trap owner */ +#define K1C_SFR_HTO_PSYS_SHIFT 4 +#define K1C_SFR_HTO_PSYS_WIDTH 2 +#define K1C_SFR_HTO_PSYS_WFXL_MASK _ULL(0x30) +#define K1C_SFR_HTO_PSYS_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_HTO_PSYS_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_HTO_DSYS_MASK _ULL(0xc0) /* Data System Error trap owner */ +#define K1C_SFR_HTO_DSYS_SHIFT 6 +#define K1C_SFR_HTO_DSYS_WIDTH 2 +#define K1C_SFR_HTO_DSYS_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_HTO_DSYS_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_HTO_DSYS_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_HTO_DECCG_MASK _ULL(0x300) /* Double ECC traps group owner */ +#define K1C_SFR_HTO_DECCG_SHIFT 8 +#define K1C_SFR_HTO_DECCG_WIDTH 2 +#define K1C_SFR_HTO_DECCG_WFXL_MASK _ULL(0x300) +#define K1C_SFR_HTO_DECCG_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_HTO_DECCG_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_HTO_SECCG_MASK _ULL(0xc00) /* Single ECC traps group owner */ +#define K1C_SFR_HTO_SECCG_SHIFT 10 +#define K1C_SFR_HTO_SECCG_WIDTH 2 +#define K1C_SFR_HTO_SECCG_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_HTO_SECCG_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_HTO_SECCG_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_HTO_NOMAP_MASK _ULL(0x3000) /* No mapping trap owner */ +#define K1C_SFR_HTO_NOMAP_SHIFT 12 +#define K1C_SFR_HTO_NOMAP_WIDTH 2 +#define K1C_SFR_HTO_NOMAP_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_HTO_NOMAP_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_HTO_NOMAP_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_HTO_PROT_MASK _ULL(0xc000) /* PROTection trap owner */ +#define K1C_SFR_HTO_PROT_SHIFT 14 +#define K1C_SFR_HTO_PROT_WIDTH 2 +#define K1C_SFR_HTO_PROT_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_HTO_PROT_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_HTO_PROT_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_HTO_W2CL_MASK _ULL(0x30000) /* Write to clean trap owner */ +#define K1C_SFR_HTO_W2CL_SHIFT 16 +#define K1C_SFR_HTO_W2CL_WIDTH 2 +#define K1C_SFR_HTO_W2CL_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_HTO_W2CL_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_HTO_W2CL_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_HTO_A2CL_MASK _ULL(0xc0000) /* Atomic to clean trap owner */ +#define K1C_SFR_HTO_A2CL_SHIFT 18 +#define K1C_SFR_HTO_A2CL_WIDTH 2 +#define K1C_SFR_HTO_A2CL_WFXL_MASK _ULL(0xc0000) +#define K1C_SFR_HTO_A2CL_WFXL_CLEAR _ULL(0xc0000) +#define K1C_SFR_HTO_A2CL_WFXL_SET _ULL(0xc000000000000) + +#define K1C_SFR_HTO_DE_MASK _ULL(0x300000) /* Double Exception trap owner */ +#define K1C_SFR_HTO_DE_SHIFT 20 +#define K1C_SFR_HTO_DE_WIDTH 2 +#define K1C_SFR_HTO_DE_WFXL_MASK _ULL(0x300000) +#define K1C_SFR_HTO_DE_WFXL_CLEAR _ULL(0x300000) +#define K1C_SFR_HTO_DE_WFXL_SET _ULL(0x30000000000000) + +#define K1C_SFR_HTO_VSFR_MASK _ULL(0xc00000) /* Virtual SFR trap owner */ +#define K1C_SFR_HTO_VSFR_SHIFT 22 +#define K1C_SFR_HTO_VSFR_WIDTH 2 +#define K1C_SFR_HTO_VSFR_WFXL_MASK _ULL(0xc00000) +#define K1C_SFR_HTO_VSFR_WFXL_CLEAR _ULL(0xc00000) +#define K1C_SFR_HTO_VSFR_WFXL_SET _ULL(0xc0000000000000) + +#define K1C_SFR_HTO_PLO_MASK _ULL(0x3000000) /* Privilege Level Overflow trap owner */ +#define K1C_SFR_HTO_PLO_SHIFT 24 +#define K1C_SFR_HTO_PLO_WIDTH 2 +#define K1C_SFR_HTO_PLO_WFXL_MASK _ULL(0x3000000) +#define K1C_SFR_HTO_PLO_WFXL_CLEAR _ULL(0x3000000) +#define K1C_SFR_HTO_PLO_WFXL_SET _ULL(0x300000000000000) + +#define K1C_SFR_HTOW_OPC_MASK _ULL(0x3) /* OPCode trap owner */ +#define K1C_SFR_HTOW_OPC_SHIFT 0 +#define K1C_SFR_HTOW_OPC_WIDTH 2 +#define K1C_SFR_HTOW_OPC_WFXL_MASK _ULL(0x3) +#define K1C_SFR_HTOW_OPC_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_HTOW_OPC_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_HTOW_DMIS_MASK _ULL(0xc) /* Data MISalign access trap owner */ +#define K1C_SFR_HTOW_DMIS_SHIFT 2 +#define K1C_SFR_HTOW_DMIS_WIDTH 2 +#define K1C_SFR_HTOW_DMIS_WFXL_MASK _ULL(0xc) +#define K1C_SFR_HTOW_DMIS_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_HTOW_DMIS_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_HTOW_PSYS_MASK _ULL(0x30) /* Program System Error trap owner */ +#define K1C_SFR_HTOW_PSYS_SHIFT 4 +#define K1C_SFR_HTOW_PSYS_WIDTH 2 +#define K1C_SFR_HTOW_PSYS_WFXL_MASK _ULL(0x30) +#define K1C_SFR_HTOW_PSYS_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_HTOW_PSYS_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_HTOW_DSYS_MASK _ULL(0xc0) /* Data System Error trap owner */ +#define K1C_SFR_HTOW_DSYS_SHIFT 6 +#define K1C_SFR_HTOW_DSYS_WIDTH 2 +#define K1C_SFR_HTOW_DSYS_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_HTOW_DSYS_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_HTOW_DSYS_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_HTOW_DECCG_MASK _ULL(0x300) /* Double ECC traps group owner */ +#define K1C_SFR_HTOW_DECCG_SHIFT 8 +#define K1C_SFR_HTOW_DECCG_WIDTH 2 +#define K1C_SFR_HTOW_DECCG_WFXL_MASK _ULL(0x300) +#define K1C_SFR_HTOW_DECCG_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_HTOW_DECCG_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_HTOW_SECCG_MASK _ULL(0xc00) /* Single ECC traps group owner */ +#define K1C_SFR_HTOW_SECCG_SHIFT 10 +#define K1C_SFR_HTOW_SECCG_WIDTH 2 +#define K1C_SFR_HTOW_SECCG_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_HTOW_SECCG_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_HTOW_SECCG_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_HTOW_NOMAP_MASK _ULL(0x3000) /* No mapping trap owner */ +#define K1C_SFR_HTOW_NOMAP_SHIFT 12 +#define K1C_SFR_HTOW_NOMAP_WIDTH 2 +#define K1C_SFR_HTOW_NOMAP_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_HTOW_NOMAP_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_HTOW_NOMAP_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_HTOW_PROT_MASK _ULL(0xc000) /* PROTection trap owner */ +#define K1C_SFR_HTOW_PROT_SHIFT 14 +#define K1C_SFR_HTOW_PROT_WIDTH 2 +#define K1C_SFR_HTOW_PROT_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_HTOW_PROT_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_HTOW_PROT_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_HTOW_W2CL_MASK _ULL(0x30000) /* Write to clean trap owner */ +#define K1C_SFR_HTOW_W2CL_SHIFT 16 +#define K1C_SFR_HTOW_W2CL_WIDTH 2 +#define K1C_SFR_HTOW_W2CL_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_HTOW_W2CL_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_HTOW_W2CL_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_HTOW_A2CL_MASK _ULL(0xc0000) /* Atomic to clean trap owner */ +#define K1C_SFR_HTOW_A2CL_SHIFT 18 +#define K1C_SFR_HTOW_A2CL_WIDTH 2 +#define K1C_SFR_HTOW_A2CL_WFXL_MASK _ULL(0xc0000) +#define K1C_SFR_HTOW_A2CL_WFXL_CLEAR _ULL(0xc0000) +#define K1C_SFR_HTOW_A2CL_WFXL_SET _ULL(0xc000000000000) + +#define K1C_SFR_HTOW_DE_MASK _ULL(0x300000) /* Double Exception trap owner */ +#define K1C_SFR_HTOW_DE_SHIFT 20 +#define K1C_SFR_HTOW_DE_WIDTH 2 +#define K1C_SFR_HTOW_DE_WFXL_MASK _ULL(0x300000) +#define K1C_SFR_HTOW_DE_WFXL_CLEAR _ULL(0x300000) +#define K1C_SFR_HTOW_DE_WFXL_SET _ULL(0x30000000000000) + +#define K1C_SFR_HTOW_VSFR_MASK _ULL(0xc00000) /* Virtual SFR trap owner */ +#define K1C_SFR_HTOW_VSFR_SHIFT 22 +#define K1C_SFR_HTOW_VSFR_WIDTH 2 +#define K1C_SFR_HTOW_VSFR_WFXL_MASK _ULL(0xc00000) +#define K1C_SFR_HTOW_VSFR_WFXL_CLEAR _ULL(0xc00000) +#define K1C_SFR_HTOW_VSFR_WFXL_SET _ULL(0xc0000000000000) + +#define K1C_SFR_HTOW_PLO_MASK _ULL(0x3000000) /* Privilege Level Overflow trap owner */ +#define K1C_SFR_HTOW_PLO_SHIFT 24 +#define K1C_SFR_HTOW_PLO_WIDTH 2 +#define K1C_SFR_HTOW_PLO_WFXL_MASK _ULL(0x3000000) +#define K1C_SFR_HTOW_PLO_WFXL_CLEAR _ULL(0x3000000) +#define K1C_SFR_HTOW_PLO_WFXL_SET _ULL(0x300000000000000) + +#define K1C_SFR_ITO_IT0_MASK _ULL(0x3) /* Interrupt 0 owner */ +#define K1C_SFR_ITO_IT0_SHIFT 0 +#define K1C_SFR_ITO_IT0_WIDTH 2 +#define K1C_SFR_ITO_IT0_WFXL_MASK _ULL(0x3) +#define K1C_SFR_ITO_IT0_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_ITO_IT0_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_ITO_IT1_MASK _ULL(0xc) /* Interrupt 1 owner */ +#define K1C_SFR_ITO_IT1_SHIFT 2 +#define K1C_SFR_ITO_IT1_WIDTH 2 +#define K1C_SFR_ITO_IT1_WFXL_MASK _ULL(0xc) +#define K1C_SFR_ITO_IT1_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_ITO_IT1_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_ITO_IT2_MASK _ULL(0x30) /* Interrupt 2 owner */ +#define K1C_SFR_ITO_IT2_SHIFT 4 +#define K1C_SFR_ITO_IT2_WIDTH 2 +#define K1C_SFR_ITO_IT2_WFXL_MASK _ULL(0x30) +#define K1C_SFR_ITO_IT2_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_ITO_IT2_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_ITO_IT3_MASK _ULL(0xc0) /* Interrupt 3 owner */ +#define K1C_SFR_ITO_IT3_SHIFT 6 +#define K1C_SFR_ITO_IT3_WIDTH 2 +#define K1C_SFR_ITO_IT3_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_ITO_IT3_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_ITO_IT3_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_ITO_IT4_MASK _ULL(0x300) /* Interrupt 4 owner */ +#define K1C_SFR_ITO_IT4_SHIFT 8 +#define K1C_SFR_ITO_IT4_WIDTH 2 +#define K1C_SFR_ITO_IT4_WFXL_MASK _ULL(0x300) +#define K1C_SFR_ITO_IT4_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_ITO_IT4_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_ITO_IT5_MASK _ULL(0xc00) /* Interrupt 5 owner */ +#define K1C_SFR_ITO_IT5_SHIFT 10 +#define K1C_SFR_ITO_IT5_WIDTH 2 +#define K1C_SFR_ITO_IT5_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_ITO_IT5_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_ITO_IT5_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_ITO_IT6_MASK _ULL(0x3000) /* Interrupt 6 owner */ +#define K1C_SFR_ITO_IT6_SHIFT 12 +#define K1C_SFR_ITO_IT6_WIDTH 2 +#define K1C_SFR_ITO_IT6_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_ITO_IT6_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_ITO_IT6_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_ITO_IT7_MASK _ULL(0xc000) /* Interrupt 7 owner */ +#define K1C_SFR_ITO_IT7_SHIFT 14 +#define K1C_SFR_ITO_IT7_WIDTH 2 +#define K1C_SFR_ITO_IT7_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_ITO_IT7_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_ITO_IT7_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_ITO_IT8_MASK _ULL(0x30000) /* Interrupt 8 owner */ +#define K1C_SFR_ITO_IT8_SHIFT 16 +#define K1C_SFR_ITO_IT8_WIDTH 2 +#define K1C_SFR_ITO_IT8_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_ITO_IT8_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_ITO_IT8_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_ITO_IT9_MASK _ULL(0xc0000) /* Interrupt 9 owner */ +#define K1C_SFR_ITO_IT9_SHIFT 18 +#define K1C_SFR_ITO_IT9_WIDTH 2 +#define K1C_SFR_ITO_IT9_WFXL_MASK _ULL(0xc0000) +#define K1C_SFR_ITO_IT9_WFXL_CLEAR _ULL(0xc0000) +#define K1C_SFR_ITO_IT9_WFXL_SET _ULL(0xc000000000000) + +#define K1C_SFR_ITO_IT10_MASK _ULL(0x300000) /* Interrupt 10 owner */ +#define K1C_SFR_ITO_IT10_SHIFT 20 +#define K1C_SFR_ITO_IT10_WIDTH 2 +#define K1C_SFR_ITO_IT10_WFXL_MASK _ULL(0x300000) +#define K1C_SFR_ITO_IT10_WFXL_CLEAR _ULL(0x300000) +#define K1C_SFR_ITO_IT10_WFXL_SET _ULL(0x30000000000000) + +#define K1C_SFR_ITO_IT11_MASK _ULL(0xc00000) /* Interrupt 11 owner */ +#define K1C_SFR_ITO_IT11_SHIFT 22 +#define K1C_SFR_ITO_IT11_WIDTH 2 +#define K1C_SFR_ITO_IT11_WFXL_MASK _ULL(0xc00000) +#define K1C_SFR_ITO_IT11_WFXL_CLEAR _ULL(0xc00000) +#define K1C_SFR_ITO_IT11_WFXL_SET _ULL(0xc0000000000000) + +#define K1C_SFR_ITO_IT12_MASK _ULL(0x3000000) /* Interrupt 12 owner */ +#define K1C_SFR_ITO_IT12_SHIFT 24 +#define K1C_SFR_ITO_IT12_WIDTH 2 +#define K1C_SFR_ITO_IT12_WFXL_MASK _ULL(0x3000000) +#define K1C_SFR_ITO_IT12_WFXL_CLEAR _ULL(0x3000000) +#define K1C_SFR_ITO_IT12_WFXL_SET _ULL(0x300000000000000) + +#define K1C_SFR_ITO_IT13_MASK _ULL(0xc000000) /* Interrupt 13 owner */ +#define K1C_SFR_ITO_IT13_SHIFT 26 +#define K1C_SFR_ITO_IT13_WIDTH 2 +#define K1C_SFR_ITO_IT13_WFXL_MASK _ULL(0xc000000) +#define K1C_SFR_ITO_IT13_WFXL_CLEAR _ULL(0xc000000) +#define K1C_SFR_ITO_IT13_WFXL_SET _ULL(0xc00000000000000) + +#define K1C_SFR_ITO_IT14_MASK _ULL(0x30000000) /* Interrupt 14 owner */ +#define K1C_SFR_ITO_IT14_SHIFT 28 +#define K1C_SFR_ITO_IT14_WIDTH 2 +#define K1C_SFR_ITO_IT14_WFXL_MASK _ULL(0x30000000) +#define K1C_SFR_ITO_IT14_WFXL_CLEAR _ULL(0x30000000) +#define K1C_SFR_ITO_IT14_WFXL_SET _ULL(0x3000000000000000) + +#define K1C_SFR_ITO_IT15_MASK _ULL(0xc0000000) /* Interrupt 15 owner */ +#define K1C_SFR_ITO_IT15_SHIFT 30 +#define K1C_SFR_ITO_IT15_WIDTH 2 +#define K1C_SFR_ITO_IT15_WFXL_MASK _ULL(0xc0000000) +#define K1C_SFR_ITO_IT15_WFXL_CLEAR _ULL(0xc0000000) +#define K1C_SFR_ITO_IT15_WFXL_SET _ULL(0xc000000000000000) + +#define K1C_SFR_ITO_IT16_MASK _ULL(0x300000000) /* Interrupt 16 owner */ +#define K1C_SFR_ITO_IT16_SHIFT 32 +#define K1C_SFR_ITO_IT16_WIDTH 2 +#define K1C_SFR_ITO_IT16_WFXM_MASK _ULL(0x300000000) +#define K1C_SFR_ITO_IT16_WFXM_CLEAR _ULL(0x3) +#define K1C_SFR_ITO_IT16_WFXM_SET _ULL(0x300000000) + +#define K1C_SFR_ITO_IT17_MASK _ULL(0xc00000000) /* Interrupt 17 owner */ +#define K1C_SFR_ITO_IT17_SHIFT 34 +#define K1C_SFR_ITO_IT17_WIDTH 2 +#define K1C_SFR_ITO_IT17_WFXM_MASK _ULL(0xc00000000) +#define K1C_SFR_ITO_IT17_WFXM_CLEAR _ULL(0xc) +#define K1C_SFR_ITO_IT17_WFXM_SET _ULL(0xc00000000) + +#define K1C_SFR_ITO_IT18_MASK _ULL(0x3000000000) /* Interrupt 18 owner */ +#define K1C_SFR_ITO_IT18_SHIFT 36 +#define K1C_SFR_ITO_IT18_WIDTH 2 +#define K1C_SFR_ITO_IT18_WFXM_MASK _ULL(0x3000000000) +#define K1C_SFR_ITO_IT18_WFXM_CLEAR _ULL(0x30) +#define K1C_SFR_ITO_IT18_WFXM_SET _ULL(0x3000000000) + +#define K1C_SFR_ITO_IT19_MASK _ULL(0xc000000000) /* Interrupt 19 owner */ +#define K1C_SFR_ITO_IT19_SHIFT 38 +#define K1C_SFR_ITO_IT19_WIDTH 2 +#define K1C_SFR_ITO_IT19_WFXM_MASK _ULL(0xc000000000) +#define K1C_SFR_ITO_IT19_WFXM_CLEAR _ULL(0xc0) +#define K1C_SFR_ITO_IT19_WFXM_SET _ULL(0xc000000000) + +#define K1C_SFR_ITO_IT20_MASK _ULL(0x30000000000) /* Interrupt 20 owner */ +#define K1C_SFR_ITO_IT20_SHIFT 40 +#define K1C_SFR_ITO_IT20_WIDTH 2 +#define K1C_SFR_ITO_IT20_WFXM_MASK _ULL(0x30000000000) +#define K1C_SFR_ITO_IT20_WFXM_CLEAR _ULL(0x300) +#define K1C_SFR_ITO_IT20_WFXM_SET _ULL(0x30000000000) + +#define K1C_SFR_ITO_IT21_MASK _ULL(0xc0000000000) /* Interrupt 21 owner */ +#define K1C_SFR_ITO_IT21_SHIFT 42 +#define K1C_SFR_ITO_IT21_WIDTH 2 +#define K1C_SFR_ITO_IT21_WFXM_MASK _ULL(0xc0000000000) +#define K1C_SFR_ITO_IT21_WFXM_CLEAR _ULL(0xc00) +#define K1C_SFR_ITO_IT21_WFXM_SET _ULL(0xc0000000000) + +#define K1C_SFR_ITO_IT22_MASK _ULL(0x300000000000) /* Interrupt 22 owner */ +#define K1C_SFR_ITO_IT22_SHIFT 44 +#define K1C_SFR_ITO_IT22_WIDTH 2 +#define K1C_SFR_ITO_IT22_WFXM_MASK _ULL(0x300000000000) +#define K1C_SFR_ITO_IT22_WFXM_CLEAR _ULL(0x3000) +#define K1C_SFR_ITO_IT22_WFXM_SET _ULL(0x300000000000) + +#define K1C_SFR_ITO_IT23_MASK _ULL(0xc00000000000) /* Interrupt 23 owner */ +#define K1C_SFR_ITO_IT23_SHIFT 46 +#define K1C_SFR_ITO_IT23_WIDTH 2 +#define K1C_SFR_ITO_IT23_WFXM_MASK _ULL(0xc00000000000) +#define K1C_SFR_ITO_IT23_WFXM_CLEAR _ULL(0xc000) +#define K1C_SFR_ITO_IT23_WFXM_SET _ULL(0xc00000000000) + +#define K1C_SFR_ITO_IT24_MASK _ULL(0x3000000000000) /* Interrupt 24 owner */ +#define K1C_SFR_ITO_IT24_SHIFT 48 +#define K1C_SFR_ITO_IT24_WIDTH 2 +#define K1C_SFR_ITO_IT24_WFXM_MASK _ULL(0x3000000000000) +#define K1C_SFR_ITO_IT24_WFXM_CLEAR _ULL(0x30000) +#define K1C_SFR_ITO_IT24_WFXM_SET _ULL(0x3000000000000) + +#define K1C_SFR_ITO_IT25_MASK _ULL(0xc000000000000) /* Interrupt 25 owner */ +#define K1C_SFR_ITO_IT25_SHIFT 50 +#define K1C_SFR_ITO_IT25_WIDTH 2 +#define K1C_SFR_ITO_IT25_WFXM_MASK _ULL(0xc000000000000) +#define K1C_SFR_ITO_IT25_WFXM_CLEAR _ULL(0xc0000) +#define K1C_SFR_ITO_IT25_WFXM_SET _ULL(0xc000000000000) + +#define K1C_SFR_ITO_IT26_MASK _ULL(0x30000000000000) /* Interrupt 26 owner */ +#define K1C_SFR_ITO_IT26_SHIFT 52 +#define K1C_SFR_ITO_IT26_WIDTH 2 +#define K1C_SFR_ITO_IT26_WFXM_MASK _ULL(0x30000000000000) +#define K1C_SFR_ITO_IT26_WFXM_CLEAR _ULL(0x300000) +#define K1C_SFR_ITO_IT26_WFXM_SET _ULL(0x30000000000000) + +#define K1C_SFR_ITO_IT27_MASK _ULL(0xc0000000000000) /* Interrupt 27 owner */ +#define K1C_SFR_ITO_IT27_SHIFT 54 +#define K1C_SFR_ITO_IT27_WIDTH 2 +#define K1C_SFR_ITO_IT27_WFXM_MASK _ULL(0xc0000000000000) +#define K1C_SFR_ITO_IT27_WFXM_CLEAR _ULL(0xc00000) +#define K1C_SFR_ITO_IT27_WFXM_SET _ULL(0xc0000000000000) + +#define K1C_SFR_ITO_IT28_MASK _ULL(0x300000000000000) /* Interrupt 28 owner */ +#define K1C_SFR_ITO_IT28_SHIFT 56 +#define K1C_SFR_ITO_IT28_WIDTH 2 +#define K1C_SFR_ITO_IT28_WFXM_MASK _ULL(0x300000000000000) +#define K1C_SFR_ITO_IT28_WFXM_CLEAR _ULL(0x3000000) +#define K1C_SFR_ITO_IT28_WFXM_SET _ULL(0x300000000000000) + +#define K1C_SFR_ITO_IT29_MASK _ULL(0xc00000000000000) /* Interrupt 29 owner */ +#define K1C_SFR_ITO_IT29_SHIFT 58 +#define K1C_SFR_ITO_IT29_WIDTH 2 +#define K1C_SFR_ITO_IT29_WFXM_MASK _ULL(0xc00000000000000) +#define K1C_SFR_ITO_IT29_WFXM_CLEAR _ULL(0xc000000) +#define K1C_SFR_ITO_IT29_WFXM_SET _ULL(0xc00000000000000) + +#define K1C_SFR_ITO_IT30_MASK _ULL(0x3000000000000000) /* Interrupt 30 owner */ +#define K1C_SFR_ITO_IT30_SHIFT 60 +#define K1C_SFR_ITO_IT30_WIDTH 2 +#define K1C_SFR_ITO_IT30_WFXM_MASK _ULL(0x3000000000000000) +#define K1C_SFR_ITO_IT30_WFXM_CLEAR _ULL(0x30000000) +#define K1C_SFR_ITO_IT30_WFXM_SET _ULL(0x3000000000000000) + +#define K1C_SFR_ITO_IT31_MASK _ULL(0xc000000000000000) /* Interrupt 31 owner */ +#define K1C_SFR_ITO_IT31_SHIFT 62 +#define K1C_SFR_ITO_IT31_WIDTH 2 +#define K1C_SFR_ITO_IT31_WFXM_MASK _ULL(0xc000000000000000) +#define K1C_SFR_ITO_IT31_WFXM_CLEAR _ULL(0xc0000000) +#define K1C_SFR_ITO_IT31_WFXM_SET _ULL(0xc000000000000000) + +#define K1C_SFR_ILE_IT0_MASK _ULL(0x1) /* Interrupt 0 owner */ +#define K1C_SFR_ILE_IT0_SHIFT 0 +#define K1C_SFR_ILE_IT0_WIDTH 1 +#define K1C_SFR_ILE_IT0_WFXL_MASK _ULL(0x1) +#define K1C_SFR_ILE_IT0_WFXL_CLEAR _ULL(0x1) +#define K1C_SFR_ILE_IT0_WFXL_SET _ULL(0x100000000) + +#define K1C_SFR_ILE_IT1_MASK _ULL(0x2) /* Interrupt 1 owner */ +#define K1C_SFR_ILE_IT1_SHIFT 1 +#define K1C_SFR_ILE_IT1_WIDTH 1 +#define K1C_SFR_ILE_IT1_WFXL_MASK _ULL(0x2) +#define K1C_SFR_ILE_IT1_WFXL_CLEAR _ULL(0x2) +#define K1C_SFR_ILE_IT1_WFXL_SET _ULL(0x200000000) + +#define K1C_SFR_ILE_IT2_MASK _ULL(0x4) /* Interrupt 2 owner */ +#define K1C_SFR_ILE_IT2_SHIFT 2 +#define K1C_SFR_ILE_IT2_WIDTH 1 +#define K1C_SFR_ILE_IT2_WFXL_MASK _ULL(0x4) +#define K1C_SFR_ILE_IT2_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_ILE_IT2_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_ILE_IT3_MASK _ULL(0x8) /* Interrupt 3 owner */ +#define K1C_SFR_ILE_IT3_SHIFT 3 +#define K1C_SFR_ILE_IT3_WIDTH 1 +#define K1C_SFR_ILE_IT3_WFXL_MASK _ULL(0x8) +#define K1C_SFR_ILE_IT3_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_ILE_IT3_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_ILE_IT4_MASK _ULL(0x10) /* Interrupt 4 owner */ +#define K1C_SFR_ILE_IT4_SHIFT 4 +#define K1C_SFR_ILE_IT4_WIDTH 1 +#define K1C_SFR_ILE_IT4_WFXL_MASK _ULL(0x10) +#define K1C_SFR_ILE_IT4_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_ILE_IT4_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_ILE_IT5_MASK _ULL(0x20) /* Interrupt 5 owner */ +#define K1C_SFR_ILE_IT5_SHIFT 5 +#define K1C_SFR_ILE_IT5_WIDTH 1 +#define K1C_SFR_ILE_IT5_WFXL_MASK _ULL(0x20) +#define K1C_SFR_ILE_IT5_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_ILE_IT5_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_ILE_IT6_MASK _ULL(0x40) /* Interrupt 6 owner */ +#define K1C_SFR_ILE_IT6_SHIFT 6 +#define K1C_SFR_ILE_IT6_WIDTH 1 +#define K1C_SFR_ILE_IT6_WFXL_MASK _ULL(0x40) +#define K1C_SFR_ILE_IT6_WFXL_CLEAR _ULL(0x40) +#define K1C_SFR_ILE_IT6_WFXL_SET _ULL(0x4000000000) + +#define K1C_SFR_ILE_IT7_MASK _ULL(0x80) /* Interrupt 7 owner */ +#define K1C_SFR_ILE_IT7_SHIFT 7 +#define K1C_SFR_ILE_IT7_WIDTH 1 +#define K1C_SFR_ILE_IT7_WFXL_MASK _ULL(0x80) +#define K1C_SFR_ILE_IT7_WFXL_CLEAR _ULL(0x80) +#define K1C_SFR_ILE_IT7_WFXL_SET _ULL(0x8000000000) + +#define K1C_SFR_ILE_IT8_MASK _ULL(0x100) /* Interrupt 8 owner */ +#define K1C_SFR_ILE_IT8_SHIFT 8 +#define K1C_SFR_ILE_IT8_WIDTH 1 +#define K1C_SFR_ILE_IT8_WFXL_MASK _ULL(0x100) +#define K1C_SFR_ILE_IT8_WFXL_CLEAR _ULL(0x100) +#define K1C_SFR_ILE_IT8_WFXL_SET _ULL(0x10000000000) + +#define K1C_SFR_ILE_IT9_MASK _ULL(0x200) /* Interrupt 9 owner */ +#define K1C_SFR_ILE_IT9_SHIFT 9 +#define K1C_SFR_ILE_IT9_WIDTH 1 +#define K1C_SFR_ILE_IT9_WFXL_MASK _ULL(0x200) +#define K1C_SFR_ILE_IT9_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_ILE_IT9_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_ILE_IT10_MASK _ULL(0x400) /* Interrupt 10 owner */ +#define K1C_SFR_ILE_IT10_SHIFT 10 +#define K1C_SFR_ILE_IT10_WIDTH 1 +#define K1C_SFR_ILE_IT10_WFXL_MASK _ULL(0x400) +#define K1C_SFR_ILE_IT10_WFXL_CLEAR _ULL(0x400) +#define K1C_SFR_ILE_IT10_WFXL_SET _ULL(0x40000000000) + +#define K1C_SFR_ILE_IT11_MASK _ULL(0x800) /* Interrupt 11 owner */ +#define K1C_SFR_ILE_IT11_SHIFT 11 +#define K1C_SFR_ILE_IT11_WIDTH 1 +#define K1C_SFR_ILE_IT11_WFXL_MASK _ULL(0x800) +#define K1C_SFR_ILE_IT11_WFXL_CLEAR _ULL(0x800) +#define K1C_SFR_ILE_IT11_WFXL_SET _ULL(0x80000000000) + +#define K1C_SFR_ILE_IT12_MASK _ULL(0x1000) /* Interrupt 12 owner */ +#define K1C_SFR_ILE_IT12_SHIFT 12 +#define K1C_SFR_ILE_IT12_WIDTH 1 +#define K1C_SFR_ILE_IT12_WFXL_MASK _ULL(0x1000) +#define K1C_SFR_ILE_IT12_WFXL_CLEAR _ULL(0x1000) +#define K1C_SFR_ILE_IT12_WFXL_SET _ULL(0x100000000000) + +#define K1C_SFR_ILE_IT13_MASK _ULL(0x2000) /* Interrupt 13 owner */ +#define K1C_SFR_ILE_IT13_SHIFT 13 +#define K1C_SFR_ILE_IT13_WIDTH 1 +#define K1C_SFR_ILE_IT13_WFXL_MASK _ULL(0x2000) +#define K1C_SFR_ILE_IT13_WFXL_CLEAR _ULL(0x2000) +#define K1C_SFR_ILE_IT13_WFXL_SET _ULL(0x200000000000) + +#define K1C_SFR_ILE_IT14_MASK _ULL(0x4000) /* Interrupt 14 owner */ +#define K1C_SFR_ILE_IT14_SHIFT 14 +#define K1C_SFR_ILE_IT14_WIDTH 1 +#define K1C_SFR_ILE_IT14_WFXL_MASK _ULL(0x4000) +#define K1C_SFR_ILE_IT14_WFXL_CLEAR _ULL(0x4000) +#define K1C_SFR_ILE_IT14_WFXL_SET _ULL(0x400000000000) + +#define K1C_SFR_ILE_IT15_MASK _ULL(0x8000) /* Interrupt 15 owner */ +#define K1C_SFR_ILE_IT15_SHIFT 15 +#define K1C_SFR_ILE_IT15_WIDTH 1 +#define K1C_SFR_ILE_IT15_WFXL_MASK _ULL(0x8000) +#define K1C_SFR_ILE_IT15_WFXL_CLEAR _ULL(0x8000) +#define K1C_SFR_ILE_IT15_WFXL_SET _ULL(0x800000000000) + +#define K1C_SFR_ILE_IT16_MASK _ULL(0x10000) /* Interrupt 16 owner */ +#define K1C_SFR_ILE_IT16_SHIFT 16 +#define K1C_SFR_ILE_IT16_WIDTH 1 +#define K1C_SFR_ILE_IT16_WFXL_MASK _ULL(0x10000) +#define K1C_SFR_ILE_IT16_WFXL_CLEAR _ULL(0x10000) +#define K1C_SFR_ILE_IT16_WFXL_SET _ULL(0x1000000000000) + +#define K1C_SFR_ILE_IT17_MASK _ULL(0x20000) /* Interrupt 17 owner */ +#define K1C_SFR_ILE_IT17_SHIFT 17 +#define K1C_SFR_ILE_IT17_WIDTH 1 +#define K1C_SFR_ILE_IT17_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_ILE_IT17_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_ILE_IT17_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_ILE_IT18_MASK _ULL(0x40000) /* Interrupt 18 owner */ +#define K1C_SFR_ILE_IT18_SHIFT 18 +#define K1C_SFR_ILE_IT18_WIDTH 1 +#define K1C_SFR_ILE_IT18_WFXL_MASK _ULL(0x40000) +#define K1C_SFR_ILE_IT18_WFXL_CLEAR _ULL(0x40000) +#define K1C_SFR_ILE_IT18_WFXL_SET _ULL(0x4000000000000) + +#define K1C_SFR_ILE_IT19_MASK _ULL(0x80000) /* Interrupt 19 owner */ +#define K1C_SFR_ILE_IT19_SHIFT 19 +#define K1C_SFR_ILE_IT19_WIDTH 1 +#define K1C_SFR_ILE_IT19_WFXL_MASK _ULL(0x80000) +#define K1C_SFR_ILE_IT19_WFXL_CLEAR _ULL(0x80000) +#define K1C_SFR_ILE_IT19_WFXL_SET _ULL(0x8000000000000) + +#define K1C_SFR_ILE_IT20_MASK _ULL(0x100000) /* Interrupt 20 owner */ +#define K1C_SFR_ILE_IT20_SHIFT 20 +#define K1C_SFR_ILE_IT20_WIDTH 1 +#define K1C_SFR_ILE_IT20_WFXL_MASK _ULL(0x100000) +#define K1C_SFR_ILE_IT20_WFXL_CLEAR _ULL(0x100000) +#define K1C_SFR_ILE_IT20_WFXL_SET _ULL(0x10000000000000) + +#define K1C_SFR_ILE_IT21_MASK _ULL(0x200000) /* Interrupt 21 owner */ +#define K1C_SFR_ILE_IT21_SHIFT 21 +#define K1C_SFR_ILE_IT21_WIDTH 1 +#define K1C_SFR_ILE_IT21_WFXL_MASK _ULL(0x200000) +#define K1C_SFR_ILE_IT21_WFXL_CLEAR _ULL(0x200000) +#define K1C_SFR_ILE_IT21_WFXL_SET _ULL(0x20000000000000) + +#define K1C_SFR_ILE_IT22_MASK _ULL(0x400000) /* Interrupt 22 owner */ +#define K1C_SFR_ILE_IT22_SHIFT 22 +#define K1C_SFR_ILE_IT22_WIDTH 1 +#define K1C_SFR_ILE_IT22_WFXL_MASK _ULL(0x400000) +#define K1C_SFR_ILE_IT22_WFXL_CLEAR _ULL(0x400000) +#define K1C_SFR_ILE_IT22_WFXL_SET _ULL(0x40000000000000) + +#define K1C_SFR_ILE_IT23_MASK _ULL(0x800000) /* Interrupt 23 owner */ +#define K1C_SFR_ILE_IT23_SHIFT 23 +#define K1C_SFR_ILE_IT23_WIDTH 1 +#define K1C_SFR_ILE_IT23_WFXL_MASK _ULL(0x800000) +#define K1C_SFR_ILE_IT23_WFXL_CLEAR _ULL(0x800000) +#define K1C_SFR_ILE_IT23_WFXL_SET _ULL(0x80000000000000) + +#define K1C_SFR_ILE_IT24_MASK _ULL(0x1000000) /* Interrupt 24 owner */ +#define K1C_SFR_ILE_IT24_SHIFT 24 +#define K1C_SFR_ILE_IT24_WIDTH 1 +#define K1C_SFR_ILE_IT24_WFXL_MASK _ULL(0x1000000) +#define K1C_SFR_ILE_IT24_WFXL_CLEAR _ULL(0x1000000) +#define K1C_SFR_ILE_IT24_WFXL_SET _ULL(0x100000000000000) + +#define K1C_SFR_ILE_IT25_MASK _ULL(0x2000000) /* Interrupt 25 owner */ +#define K1C_SFR_ILE_IT25_SHIFT 25 +#define K1C_SFR_ILE_IT25_WIDTH 1 +#define K1C_SFR_ILE_IT25_WFXL_MASK _ULL(0x2000000) +#define K1C_SFR_ILE_IT25_WFXL_CLEAR _ULL(0x2000000) +#define K1C_SFR_ILE_IT25_WFXL_SET _ULL(0x200000000000000) + +#define K1C_SFR_ILE_IT26_MASK _ULL(0x4000000) /* Interrupt 26 owner */ +#define K1C_SFR_ILE_IT26_SHIFT 26 +#define K1C_SFR_ILE_IT26_WIDTH 1 +#define K1C_SFR_ILE_IT26_WFXL_MASK _ULL(0x4000000) +#define K1C_SFR_ILE_IT26_WFXL_CLEAR _ULL(0x4000000) +#define K1C_SFR_ILE_IT26_WFXL_SET _ULL(0x400000000000000) + +#define K1C_SFR_ILE_IT27_MASK _ULL(0x8000000) /* Interrupt 27 owner */ +#define K1C_SFR_ILE_IT27_SHIFT 27 +#define K1C_SFR_ILE_IT27_WIDTH 1 +#define K1C_SFR_ILE_IT27_WFXL_MASK _ULL(0x8000000) +#define K1C_SFR_ILE_IT27_WFXL_CLEAR _ULL(0x8000000) +#define K1C_SFR_ILE_IT27_WFXL_SET _ULL(0x800000000000000) + +#define K1C_SFR_ILE_IT28_MASK _ULL(0x10000000) /* Interrupt 28 owner */ +#define K1C_SFR_ILE_IT28_SHIFT 28 +#define K1C_SFR_ILE_IT28_WIDTH 1 +#define K1C_SFR_ILE_IT28_WFXL_MASK _ULL(0x10000000) +#define K1C_SFR_ILE_IT28_WFXL_CLEAR _ULL(0x10000000) +#define K1C_SFR_ILE_IT28_WFXL_SET _ULL(0x1000000000000000) + +#define K1C_SFR_ILE_IT29_MASK _ULL(0x20000000) /* Interrupt 29 owner */ +#define K1C_SFR_ILE_IT29_SHIFT 29 +#define K1C_SFR_ILE_IT29_WIDTH 1 +#define K1C_SFR_ILE_IT29_WFXL_MASK _ULL(0x20000000) +#define K1C_SFR_ILE_IT29_WFXL_CLEAR _ULL(0x20000000) +#define K1C_SFR_ILE_IT29_WFXL_SET _ULL(0x2000000000000000) + +#define K1C_SFR_ILE_IT30_MASK _ULL(0x40000000) /* Interrupt 30 owner */ +#define K1C_SFR_ILE_IT30_SHIFT 30 +#define K1C_SFR_ILE_IT30_WIDTH 1 +#define K1C_SFR_ILE_IT30_WFXL_MASK _ULL(0x40000000) +#define K1C_SFR_ILE_IT30_WFXL_CLEAR _ULL(0x40000000) +#define K1C_SFR_ILE_IT30_WFXL_SET _ULL(0x4000000000000000) + +#define K1C_SFR_ILE_IT31_MASK _ULL(0x80000000) /* Interrupt 31 owner */ +#define K1C_SFR_ILE_IT31_SHIFT 31 +#define K1C_SFR_ILE_IT31_WIDTH 1 +#define K1C_SFR_ILE_IT31_WFXL_MASK _ULL(0x80000000) +#define K1C_SFR_ILE_IT31_WFXL_CLEAR _ULL(0x80000000) +#define K1C_SFR_ILE_IT31_WFXL_SET _ULL(0x8000000000000000) + +#define K1C_SFR_ILL_IT0_MASK _ULL(0x3) /* Interrupt 0 owner */ +#define K1C_SFR_ILL_IT0_SHIFT 0 +#define K1C_SFR_ILL_IT0_WIDTH 2 +#define K1C_SFR_ILL_IT0_WFXL_MASK _ULL(0x3) +#define K1C_SFR_ILL_IT0_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_ILL_IT0_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_ILL_IT1_MASK _ULL(0xc) /* Interrupt 1 owner */ +#define K1C_SFR_ILL_IT1_SHIFT 2 +#define K1C_SFR_ILL_IT1_WIDTH 2 +#define K1C_SFR_ILL_IT1_WFXL_MASK _ULL(0xc) +#define K1C_SFR_ILL_IT1_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_ILL_IT1_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_ILL_IT2_MASK _ULL(0x30) /* Interrupt 2 owner */ +#define K1C_SFR_ILL_IT2_SHIFT 4 +#define K1C_SFR_ILL_IT2_WIDTH 2 +#define K1C_SFR_ILL_IT2_WFXL_MASK _ULL(0x30) +#define K1C_SFR_ILL_IT2_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_ILL_IT2_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_ILL_IT3_MASK _ULL(0xc0) /* Interrupt 3 owner */ +#define K1C_SFR_ILL_IT3_SHIFT 6 +#define K1C_SFR_ILL_IT3_WIDTH 2 +#define K1C_SFR_ILL_IT3_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_ILL_IT3_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_ILL_IT3_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_ILL_IT4_MASK _ULL(0x300) /* Interrupt 4 owner */ +#define K1C_SFR_ILL_IT4_SHIFT 8 +#define K1C_SFR_ILL_IT4_WIDTH 2 +#define K1C_SFR_ILL_IT4_WFXL_MASK _ULL(0x300) +#define K1C_SFR_ILL_IT4_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_ILL_IT4_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_ILL_IT5_MASK _ULL(0xc00) /* Interrupt 5 owner */ +#define K1C_SFR_ILL_IT5_SHIFT 10 +#define K1C_SFR_ILL_IT5_WIDTH 2 +#define K1C_SFR_ILL_IT5_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_ILL_IT5_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_ILL_IT5_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_ILL_IT6_MASK _ULL(0x3000) /* Interrupt 6 owner */ +#define K1C_SFR_ILL_IT6_SHIFT 12 +#define K1C_SFR_ILL_IT6_WIDTH 2 +#define K1C_SFR_ILL_IT6_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_ILL_IT6_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_ILL_IT6_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_ILL_IT7_MASK _ULL(0xc000) /* Interrupt 7 owner */ +#define K1C_SFR_ILL_IT7_SHIFT 14 +#define K1C_SFR_ILL_IT7_WIDTH 2 +#define K1C_SFR_ILL_IT7_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_ILL_IT7_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_ILL_IT7_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_ILL_IT8_MASK _ULL(0x30000) /* Interrupt 8 owner */ +#define K1C_SFR_ILL_IT8_SHIFT 16 +#define K1C_SFR_ILL_IT8_WIDTH 2 +#define K1C_SFR_ILL_IT8_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_ILL_IT8_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_ILL_IT8_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_ILL_IT9_MASK _ULL(0xc0000) /* Interrupt 9 owner */ +#define K1C_SFR_ILL_IT9_SHIFT 18 +#define K1C_SFR_ILL_IT9_WIDTH 2 +#define K1C_SFR_ILL_IT9_WFXL_MASK _ULL(0xc0000) +#define K1C_SFR_ILL_IT9_WFXL_CLEAR _ULL(0xc0000) +#define K1C_SFR_ILL_IT9_WFXL_SET _ULL(0xc000000000000) + +#define K1C_SFR_ILL_IT10_MASK _ULL(0x300000) /* Interrupt 10 owner */ +#define K1C_SFR_ILL_IT10_SHIFT 20 +#define K1C_SFR_ILL_IT10_WIDTH 2 +#define K1C_SFR_ILL_IT10_WFXL_MASK _ULL(0x300000) +#define K1C_SFR_ILL_IT10_WFXL_CLEAR _ULL(0x300000) +#define K1C_SFR_ILL_IT10_WFXL_SET _ULL(0x30000000000000) + +#define K1C_SFR_ILL_IT11_MASK _ULL(0xc00000) /* Interrupt 11 owner */ +#define K1C_SFR_ILL_IT11_SHIFT 22 +#define K1C_SFR_ILL_IT11_WIDTH 2 +#define K1C_SFR_ILL_IT11_WFXL_MASK _ULL(0xc00000) +#define K1C_SFR_ILL_IT11_WFXL_CLEAR _ULL(0xc00000) +#define K1C_SFR_ILL_IT11_WFXL_SET _ULL(0xc0000000000000) + +#define K1C_SFR_ILL_IT12_MASK _ULL(0x3000000) /* Interrupt 12 owner */ +#define K1C_SFR_ILL_IT12_SHIFT 24 +#define K1C_SFR_ILL_IT12_WIDTH 2 +#define K1C_SFR_ILL_IT12_WFXL_MASK _ULL(0x3000000) +#define K1C_SFR_ILL_IT12_WFXL_CLEAR _ULL(0x3000000) +#define K1C_SFR_ILL_IT12_WFXL_SET _ULL(0x300000000000000) + +#define K1C_SFR_ILL_IT13_MASK _ULL(0xc000000) /* Interrupt 13 owner */ +#define K1C_SFR_ILL_IT13_SHIFT 26 +#define K1C_SFR_ILL_IT13_WIDTH 2 +#define K1C_SFR_ILL_IT13_WFXL_MASK _ULL(0xc000000) +#define K1C_SFR_ILL_IT13_WFXL_CLEAR _ULL(0xc000000) +#define K1C_SFR_ILL_IT13_WFXL_SET _ULL(0xc00000000000000) + +#define K1C_SFR_ILL_IT14_MASK _ULL(0x30000000) /* Interrupt 14 owner */ +#define K1C_SFR_ILL_IT14_SHIFT 28 +#define K1C_SFR_ILL_IT14_WIDTH 2 +#define K1C_SFR_ILL_IT14_WFXL_MASK _ULL(0x30000000) +#define K1C_SFR_ILL_IT14_WFXL_CLEAR _ULL(0x30000000) +#define K1C_SFR_ILL_IT14_WFXL_SET _ULL(0x3000000000000000) + +#define K1C_SFR_ILL_IT15_MASK _ULL(0xc0000000) /* Interrupt 15 owner */ +#define K1C_SFR_ILL_IT15_SHIFT 30 +#define K1C_SFR_ILL_IT15_WIDTH 2 +#define K1C_SFR_ILL_IT15_WFXL_MASK _ULL(0xc0000000) +#define K1C_SFR_ILL_IT15_WFXL_CLEAR _ULL(0xc0000000) +#define K1C_SFR_ILL_IT15_WFXL_SET _ULL(0xc000000000000000) + +#define K1C_SFR_ILL_IT16_MASK _ULL(0x300000000) /* Interrupt 16 owner */ +#define K1C_SFR_ILL_IT16_SHIFT 32 +#define K1C_SFR_ILL_IT16_WIDTH 2 +#define K1C_SFR_ILL_IT16_WFXM_MASK _ULL(0x300000000) +#define K1C_SFR_ILL_IT16_WFXM_CLEAR _ULL(0x3) +#define K1C_SFR_ILL_IT16_WFXM_SET _ULL(0x300000000) + +#define K1C_SFR_ILL_IT17_MASK _ULL(0xc00000000) /* Interrupt 17 owner */ +#define K1C_SFR_ILL_IT17_SHIFT 34 +#define K1C_SFR_ILL_IT17_WIDTH 2 +#define K1C_SFR_ILL_IT17_WFXM_MASK _ULL(0xc00000000) +#define K1C_SFR_ILL_IT17_WFXM_CLEAR _ULL(0xc) +#define K1C_SFR_ILL_IT17_WFXM_SET _ULL(0xc00000000) + +#define K1C_SFR_ILL_IT18_MASK _ULL(0x3000000000) /* Interrupt 18 owner */ +#define K1C_SFR_ILL_IT18_SHIFT 36 +#define K1C_SFR_ILL_IT18_WIDTH 2 +#define K1C_SFR_ILL_IT18_WFXM_MASK _ULL(0x3000000000) +#define K1C_SFR_ILL_IT18_WFXM_CLEAR _ULL(0x30) +#define K1C_SFR_ILL_IT18_WFXM_SET _ULL(0x3000000000) + +#define K1C_SFR_ILL_IT19_MASK _ULL(0xc000000000) /* Interrupt 19 owner */ +#define K1C_SFR_ILL_IT19_SHIFT 38 +#define K1C_SFR_ILL_IT19_WIDTH 2 +#define K1C_SFR_ILL_IT19_WFXM_MASK _ULL(0xc000000000) +#define K1C_SFR_ILL_IT19_WFXM_CLEAR _ULL(0xc0) +#define K1C_SFR_ILL_IT19_WFXM_SET _ULL(0xc000000000) + +#define K1C_SFR_ILL_IT20_MASK _ULL(0x30000000000) /* Interrupt 20 owner */ +#define K1C_SFR_ILL_IT20_SHIFT 40 +#define K1C_SFR_ILL_IT20_WIDTH 2 +#define K1C_SFR_ILL_IT20_WFXM_MASK _ULL(0x30000000000) +#define K1C_SFR_ILL_IT20_WFXM_CLEAR _ULL(0x300) +#define K1C_SFR_ILL_IT20_WFXM_SET _ULL(0x30000000000) + +#define K1C_SFR_ILL_IT21_MASK _ULL(0xc0000000000) /* Interrupt 21 owner */ +#define K1C_SFR_ILL_IT21_SHIFT 42 +#define K1C_SFR_ILL_IT21_WIDTH 2 +#define K1C_SFR_ILL_IT21_WFXM_MASK _ULL(0xc0000000000) +#define K1C_SFR_ILL_IT21_WFXM_CLEAR _ULL(0xc00) +#define K1C_SFR_ILL_IT21_WFXM_SET _ULL(0xc0000000000) + +#define K1C_SFR_ILL_IT22_MASK _ULL(0x300000000000) /* Interrupt 22 owner */ +#define K1C_SFR_ILL_IT22_SHIFT 44 +#define K1C_SFR_ILL_IT22_WIDTH 2 +#define K1C_SFR_ILL_IT22_WFXM_MASK _ULL(0x300000000000) +#define K1C_SFR_ILL_IT22_WFXM_CLEAR _ULL(0x3000) +#define K1C_SFR_ILL_IT22_WFXM_SET _ULL(0x300000000000) + +#define K1C_SFR_ILL_IT23_MASK _ULL(0xc00000000000) /* Interrupt 23 owner */ +#define K1C_SFR_ILL_IT23_SHIFT 46 +#define K1C_SFR_ILL_IT23_WIDTH 2 +#define K1C_SFR_ILL_IT23_WFXM_MASK _ULL(0xc00000000000) +#define K1C_SFR_ILL_IT23_WFXM_CLEAR _ULL(0xc000) +#define K1C_SFR_ILL_IT23_WFXM_SET _ULL(0xc00000000000) + +#define K1C_SFR_ILL_IT24_MASK _ULL(0x3000000000000) /* Interrupt 24 owner */ +#define K1C_SFR_ILL_IT24_SHIFT 48 +#define K1C_SFR_ILL_IT24_WIDTH 2 +#define K1C_SFR_ILL_IT24_WFXM_MASK _ULL(0x3000000000000) +#define K1C_SFR_ILL_IT24_WFXM_CLEAR _ULL(0x30000) +#define K1C_SFR_ILL_IT24_WFXM_SET _ULL(0x3000000000000) + +#define K1C_SFR_ILL_IT25_MASK _ULL(0xc000000000000) /* Interrupt 25 owner */ +#define K1C_SFR_ILL_IT25_SHIFT 50 +#define K1C_SFR_ILL_IT25_WIDTH 2 +#define K1C_SFR_ILL_IT25_WFXM_MASK _ULL(0xc000000000000) +#define K1C_SFR_ILL_IT25_WFXM_CLEAR _ULL(0xc0000) +#define K1C_SFR_ILL_IT25_WFXM_SET _ULL(0xc000000000000) + +#define K1C_SFR_ILL_IT26_MASK _ULL(0x30000000000000) /* Interrupt 26 owner */ +#define K1C_SFR_ILL_IT26_SHIFT 52 +#define K1C_SFR_ILL_IT26_WIDTH 2 +#define K1C_SFR_ILL_IT26_WFXM_MASK _ULL(0x30000000000000) +#define K1C_SFR_ILL_IT26_WFXM_CLEAR _ULL(0x300000) +#define K1C_SFR_ILL_IT26_WFXM_SET _ULL(0x30000000000000) + +#define K1C_SFR_ILL_IT27_MASK _ULL(0xc0000000000000) /* Interrupt 27 owner */ +#define K1C_SFR_ILL_IT27_SHIFT 54 +#define K1C_SFR_ILL_IT27_WIDTH 2 +#define K1C_SFR_ILL_IT27_WFXM_MASK _ULL(0xc0000000000000) +#define K1C_SFR_ILL_IT27_WFXM_CLEAR _ULL(0xc00000) +#define K1C_SFR_ILL_IT27_WFXM_SET _ULL(0xc0000000000000) + +#define K1C_SFR_ILL_IT28_MASK _ULL(0x300000000000000) /* Interrupt 28 owner */ +#define K1C_SFR_ILL_IT28_SHIFT 56 +#define K1C_SFR_ILL_IT28_WIDTH 2 +#define K1C_SFR_ILL_IT28_WFXM_MASK _ULL(0x300000000000000) +#define K1C_SFR_ILL_IT28_WFXM_CLEAR _ULL(0x3000000) +#define K1C_SFR_ILL_IT28_WFXM_SET _ULL(0x300000000000000) + +#define K1C_SFR_ILL_IT29_MASK _ULL(0xc00000000000000) /* Interrupt 29 owner */ +#define K1C_SFR_ILL_IT29_SHIFT 58 +#define K1C_SFR_ILL_IT29_WIDTH 2 +#define K1C_SFR_ILL_IT29_WFXM_MASK _ULL(0xc00000000000000) +#define K1C_SFR_ILL_IT29_WFXM_CLEAR _ULL(0xc000000) +#define K1C_SFR_ILL_IT29_WFXM_SET _ULL(0xc00000000000000) + +#define K1C_SFR_ILL_IT30_MASK _ULL(0x3000000000000000) /* Interrupt 30 owner */ +#define K1C_SFR_ILL_IT30_SHIFT 60 +#define K1C_SFR_ILL_IT30_WIDTH 2 +#define K1C_SFR_ILL_IT30_WFXM_MASK _ULL(0x3000000000000000) +#define K1C_SFR_ILL_IT30_WFXM_CLEAR _ULL(0x30000000) +#define K1C_SFR_ILL_IT30_WFXM_SET _ULL(0x3000000000000000) + +#define K1C_SFR_ILL_IT31_MASK _ULL(0xc000000000000000) /* Interrupt 31 owner */ +#define K1C_SFR_ILL_IT31_SHIFT 62 +#define K1C_SFR_ILL_IT31_WIDTH 2 +#define K1C_SFR_ILL_IT31_WFXM_MASK _ULL(0xc000000000000000) +#define K1C_SFR_ILL_IT31_WFXM_CLEAR _ULL(0xc0000000) +#define K1C_SFR_ILL_IT31_WFXM_SET _ULL(0xc000000000000000) + +#define K1C_SFR_ILR_IT0_MASK _ULL(0x1) /* Interrupt 0 owner */ +#define K1C_SFR_ILR_IT0_SHIFT 0 +#define K1C_SFR_ILR_IT0_WIDTH 1 +#define K1C_SFR_ILR_IT0_WFXL_MASK _ULL(0x1) +#define K1C_SFR_ILR_IT0_WFXL_CLEAR _ULL(0x1) +#define K1C_SFR_ILR_IT0_WFXL_SET _ULL(0x100000000) + +#define K1C_SFR_ILR_IT1_MASK _ULL(0x2) /* Interrupt 1 owner */ +#define K1C_SFR_ILR_IT1_SHIFT 1 +#define K1C_SFR_ILR_IT1_WIDTH 1 +#define K1C_SFR_ILR_IT1_WFXL_MASK _ULL(0x2) +#define K1C_SFR_ILR_IT1_WFXL_CLEAR _ULL(0x2) +#define K1C_SFR_ILR_IT1_WFXL_SET _ULL(0x200000000) + +#define K1C_SFR_ILR_IT2_MASK _ULL(0x4) /* Interrupt 2 owner */ +#define K1C_SFR_ILR_IT2_SHIFT 2 +#define K1C_SFR_ILR_IT2_WIDTH 1 +#define K1C_SFR_ILR_IT2_WFXL_MASK _ULL(0x4) +#define K1C_SFR_ILR_IT2_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_ILR_IT2_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_ILR_IT3_MASK _ULL(0x8) /* Interrupt 3 owner */ +#define K1C_SFR_ILR_IT3_SHIFT 3 +#define K1C_SFR_ILR_IT3_WIDTH 1 +#define K1C_SFR_ILR_IT3_WFXL_MASK _ULL(0x8) +#define K1C_SFR_ILR_IT3_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_ILR_IT3_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_ILR_IT4_MASK _ULL(0x10) /* Interrupt 4 owner */ +#define K1C_SFR_ILR_IT4_SHIFT 4 +#define K1C_SFR_ILR_IT4_WIDTH 1 +#define K1C_SFR_ILR_IT4_WFXL_MASK _ULL(0x10) +#define K1C_SFR_ILR_IT4_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_ILR_IT4_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_ILR_IT5_MASK _ULL(0x20) /* Interrupt 5 owner */ +#define K1C_SFR_ILR_IT5_SHIFT 5 +#define K1C_SFR_ILR_IT5_WIDTH 1 +#define K1C_SFR_ILR_IT5_WFXL_MASK _ULL(0x20) +#define K1C_SFR_ILR_IT5_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_ILR_IT5_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_ILR_IT6_MASK _ULL(0x40) /* Interrupt 6 owner */ +#define K1C_SFR_ILR_IT6_SHIFT 6 +#define K1C_SFR_ILR_IT6_WIDTH 1 +#define K1C_SFR_ILR_IT6_WFXL_MASK _ULL(0x40) +#define K1C_SFR_ILR_IT6_WFXL_CLEAR _ULL(0x40) +#define K1C_SFR_ILR_IT6_WFXL_SET _ULL(0x4000000000) + +#define K1C_SFR_ILR_IT7_MASK _ULL(0x80) /* Interrupt 7 owner */ +#define K1C_SFR_ILR_IT7_SHIFT 7 +#define K1C_SFR_ILR_IT7_WIDTH 1 +#define K1C_SFR_ILR_IT7_WFXL_MASK _ULL(0x80) +#define K1C_SFR_ILR_IT7_WFXL_CLEAR _ULL(0x80) +#define K1C_SFR_ILR_IT7_WFXL_SET _ULL(0x8000000000) + +#define K1C_SFR_ILR_IT8_MASK _ULL(0x100) /* Interrupt 8 owner */ +#define K1C_SFR_ILR_IT8_SHIFT 8 +#define K1C_SFR_ILR_IT8_WIDTH 1 +#define K1C_SFR_ILR_IT8_WFXL_MASK _ULL(0x100) +#define K1C_SFR_ILR_IT8_WFXL_CLEAR _ULL(0x100) +#define K1C_SFR_ILR_IT8_WFXL_SET _ULL(0x10000000000) + +#define K1C_SFR_ILR_IT9_MASK _ULL(0x200) /* Interrupt 9 owner */ +#define K1C_SFR_ILR_IT9_SHIFT 9 +#define K1C_SFR_ILR_IT9_WIDTH 1 +#define K1C_SFR_ILR_IT9_WFXL_MASK _ULL(0x200) +#define K1C_SFR_ILR_IT9_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_ILR_IT9_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_ILR_IT10_MASK _ULL(0x400) /* Interrupt 10 owner */ +#define K1C_SFR_ILR_IT10_SHIFT 10 +#define K1C_SFR_ILR_IT10_WIDTH 1 +#define K1C_SFR_ILR_IT10_WFXL_MASK _ULL(0x400) +#define K1C_SFR_ILR_IT10_WFXL_CLEAR _ULL(0x400) +#define K1C_SFR_ILR_IT10_WFXL_SET _ULL(0x40000000000) + +#define K1C_SFR_ILR_IT11_MASK _ULL(0x800) /* Interrupt 11 owner */ +#define K1C_SFR_ILR_IT11_SHIFT 11 +#define K1C_SFR_ILR_IT11_WIDTH 1 +#define K1C_SFR_ILR_IT11_WFXL_MASK _ULL(0x800) +#define K1C_SFR_ILR_IT11_WFXL_CLEAR _ULL(0x800) +#define K1C_SFR_ILR_IT11_WFXL_SET _ULL(0x80000000000) + +#define K1C_SFR_ILR_IT12_MASK _ULL(0x1000) /* Interrupt 12 owner */ +#define K1C_SFR_ILR_IT12_SHIFT 12 +#define K1C_SFR_ILR_IT12_WIDTH 1 +#define K1C_SFR_ILR_IT12_WFXL_MASK _ULL(0x1000) +#define K1C_SFR_ILR_IT12_WFXL_CLEAR _ULL(0x1000) +#define K1C_SFR_ILR_IT12_WFXL_SET _ULL(0x100000000000) + +#define K1C_SFR_ILR_IT13_MASK _ULL(0x2000) /* Interrupt 13 owner */ +#define K1C_SFR_ILR_IT13_SHIFT 13 +#define K1C_SFR_ILR_IT13_WIDTH 1 +#define K1C_SFR_ILR_IT13_WFXL_MASK _ULL(0x2000) +#define K1C_SFR_ILR_IT13_WFXL_CLEAR _ULL(0x2000) +#define K1C_SFR_ILR_IT13_WFXL_SET _ULL(0x200000000000) + +#define K1C_SFR_ILR_IT14_MASK _ULL(0x4000) /* Interrupt 14 owner */ +#define K1C_SFR_ILR_IT14_SHIFT 14 +#define K1C_SFR_ILR_IT14_WIDTH 1 +#define K1C_SFR_ILR_IT14_WFXL_MASK _ULL(0x4000) +#define K1C_SFR_ILR_IT14_WFXL_CLEAR _ULL(0x4000) +#define K1C_SFR_ILR_IT14_WFXL_SET _ULL(0x400000000000) + +#define K1C_SFR_ILR_IT15_MASK _ULL(0x8000) /* Interrupt 15 owner */ +#define K1C_SFR_ILR_IT15_SHIFT 15 +#define K1C_SFR_ILR_IT15_WIDTH 1 +#define K1C_SFR_ILR_IT15_WFXL_MASK _ULL(0x8000) +#define K1C_SFR_ILR_IT15_WFXL_CLEAR _ULL(0x8000) +#define K1C_SFR_ILR_IT15_WFXL_SET _ULL(0x800000000000) + +#define K1C_SFR_ILR_IT16_MASK _ULL(0x10000) /* Interrupt 16 owner */ +#define K1C_SFR_ILR_IT16_SHIFT 16 +#define K1C_SFR_ILR_IT16_WIDTH 1 +#define K1C_SFR_ILR_IT16_WFXL_MASK _ULL(0x10000) +#define K1C_SFR_ILR_IT16_WFXL_CLEAR _ULL(0x10000) +#define K1C_SFR_ILR_IT16_WFXL_SET _ULL(0x1000000000000) + +#define K1C_SFR_ILR_IT17_MASK _ULL(0x20000) /* Interrupt 17 owner */ +#define K1C_SFR_ILR_IT17_SHIFT 17 +#define K1C_SFR_ILR_IT17_WIDTH 1 +#define K1C_SFR_ILR_IT17_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_ILR_IT17_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_ILR_IT17_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_ILR_IT18_MASK _ULL(0x40000) /* Interrupt 18 owner */ +#define K1C_SFR_ILR_IT18_SHIFT 18 +#define K1C_SFR_ILR_IT18_WIDTH 1 +#define K1C_SFR_ILR_IT18_WFXL_MASK _ULL(0x40000) +#define K1C_SFR_ILR_IT18_WFXL_CLEAR _ULL(0x40000) +#define K1C_SFR_ILR_IT18_WFXL_SET _ULL(0x4000000000000) + +#define K1C_SFR_ILR_IT19_MASK _ULL(0x80000) /* Interrupt 19 owner */ +#define K1C_SFR_ILR_IT19_SHIFT 19 +#define K1C_SFR_ILR_IT19_WIDTH 1 +#define K1C_SFR_ILR_IT19_WFXL_MASK _ULL(0x80000) +#define K1C_SFR_ILR_IT19_WFXL_CLEAR _ULL(0x80000) +#define K1C_SFR_ILR_IT19_WFXL_SET _ULL(0x8000000000000) + +#define K1C_SFR_ILR_IT20_MASK _ULL(0x100000) /* Interrupt 20 owner */ +#define K1C_SFR_ILR_IT20_SHIFT 20 +#define K1C_SFR_ILR_IT20_WIDTH 1 +#define K1C_SFR_ILR_IT20_WFXL_MASK _ULL(0x100000) +#define K1C_SFR_ILR_IT20_WFXL_CLEAR _ULL(0x100000) +#define K1C_SFR_ILR_IT20_WFXL_SET _ULL(0x10000000000000) + +#define K1C_SFR_ILR_IT21_MASK _ULL(0x200000) /* Interrupt 21 owner */ +#define K1C_SFR_ILR_IT21_SHIFT 21 +#define K1C_SFR_ILR_IT21_WIDTH 1 +#define K1C_SFR_ILR_IT21_WFXL_MASK _ULL(0x200000) +#define K1C_SFR_ILR_IT21_WFXL_CLEAR _ULL(0x200000) +#define K1C_SFR_ILR_IT21_WFXL_SET _ULL(0x20000000000000) + +#define K1C_SFR_ILR_IT22_MASK _ULL(0x400000) /* Interrupt 22 owner */ +#define K1C_SFR_ILR_IT22_SHIFT 22 +#define K1C_SFR_ILR_IT22_WIDTH 1 +#define K1C_SFR_ILR_IT22_WFXL_MASK _ULL(0x400000) +#define K1C_SFR_ILR_IT22_WFXL_CLEAR _ULL(0x400000) +#define K1C_SFR_ILR_IT22_WFXL_SET _ULL(0x40000000000000) + +#define K1C_SFR_ILR_IT23_MASK _ULL(0x800000) /* Interrupt 23 owner */ +#define K1C_SFR_ILR_IT23_SHIFT 23 +#define K1C_SFR_ILR_IT23_WIDTH 1 +#define K1C_SFR_ILR_IT23_WFXL_MASK _ULL(0x800000) +#define K1C_SFR_ILR_IT23_WFXL_CLEAR _ULL(0x800000) +#define K1C_SFR_ILR_IT23_WFXL_SET _ULL(0x80000000000000) + +#define K1C_SFR_ILR_IT24_MASK _ULL(0x1000000) /* Interrupt 24 owner */ +#define K1C_SFR_ILR_IT24_SHIFT 24 +#define K1C_SFR_ILR_IT24_WIDTH 1 +#define K1C_SFR_ILR_IT24_WFXL_MASK _ULL(0x1000000) +#define K1C_SFR_ILR_IT24_WFXL_CLEAR _ULL(0x1000000) +#define K1C_SFR_ILR_IT24_WFXL_SET _ULL(0x100000000000000) + +#define K1C_SFR_ILR_IT25_MASK _ULL(0x2000000) /* Interrupt 25 owner */ +#define K1C_SFR_ILR_IT25_SHIFT 25 +#define K1C_SFR_ILR_IT25_WIDTH 1 +#define K1C_SFR_ILR_IT25_WFXL_MASK _ULL(0x2000000) +#define K1C_SFR_ILR_IT25_WFXL_CLEAR _ULL(0x2000000) +#define K1C_SFR_ILR_IT25_WFXL_SET _ULL(0x200000000000000) + +#define K1C_SFR_ILR_IT26_MASK _ULL(0x4000000) /* Interrupt 26 owner */ +#define K1C_SFR_ILR_IT26_SHIFT 26 +#define K1C_SFR_ILR_IT26_WIDTH 1 +#define K1C_SFR_ILR_IT26_WFXL_MASK _ULL(0x4000000) +#define K1C_SFR_ILR_IT26_WFXL_CLEAR _ULL(0x4000000) +#define K1C_SFR_ILR_IT26_WFXL_SET _ULL(0x400000000000000) + +#define K1C_SFR_ILR_IT27_MASK _ULL(0x8000000) /* Interrupt 27 owner */ +#define K1C_SFR_ILR_IT27_SHIFT 27 +#define K1C_SFR_ILR_IT27_WIDTH 1 +#define K1C_SFR_ILR_IT27_WFXL_MASK _ULL(0x8000000) +#define K1C_SFR_ILR_IT27_WFXL_CLEAR _ULL(0x8000000) +#define K1C_SFR_ILR_IT27_WFXL_SET _ULL(0x800000000000000) + +#define K1C_SFR_ILR_IT28_MASK _ULL(0x10000000) /* Interrupt 28 owner */ +#define K1C_SFR_ILR_IT28_SHIFT 28 +#define K1C_SFR_ILR_IT28_WIDTH 1 +#define K1C_SFR_ILR_IT28_WFXL_MASK _ULL(0x10000000) +#define K1C_SFR_ILR_IT28_WFXL_CLEAR _ULL(0x10000000) +#define K1C_SFR_ILR_IT28_WFXL_SET _ULL(0x1000000000000000) + +#define K1C_SFR_ILR_IT29_MASK _ULL(0x20000000) /* Interrupt 29 owner */ +#define K1C_SFR_ILR_IT29_SHIFT 29 +#define K1C_SFR_ILR_IT29_WIDTH 1 +#define K1C_SFR_ILR_IT29_WFXL_MASK _ULL(0x20000000) +#define K1C_SFR_ILR_IT29_WFXL_CLEAR _ULL(0x20000000) +#define K1C_SFR_ILR_IT29_WFXL_SET _ULL(0x2000000000000000) + +#define K1C_SFR_ILR_IT30_MASK _ULL(0x40000000) /* Interrupt 30 owner */ +#define K1C_SFR_ILR_IT30_SHIFT 30 +#define K1C_SFR_ILR_IT30_WIDTH 1 +#define K1C_SFR_ILR_IT30_WFXL_MASK _ULL(0x40000000) +#define K1C_SFR_ILR_IT30_WFXL_CLEAR _ULL(0x40000000) +#define K1C_SFR_ILR_IT30_WFXL_SET _ULL(0x4000000000000000) + +#define K1C_SFR_ILR_IT31_MASK _ULL(0x80000000) /* Interrupt 31 owner */ +#define K1C_SFR_ILR_IT31_SHIFT 31 +#define K1C_SFR_ILR_IT31_WIDTH 1 +#define K1C_SFR_ILR_IT31_WFXL_MASK _ULL(0x80000000) +#define K1C_SFR_ILR_IT31_WFXL_CLEAR _ULL(0x80000000) +#define K1C_SFR_ILR_IT31_WFXL_SET _ULL(0x8000000000000000) + +#define K1C_SFR_ITOW_IT0_MASK _ULL(0x3) /* Interrupt 0 owner */ +#define K1C_SFR_ITOW_IT0_SHIFT 0 +#define K1C_SFR_ITOW_IT0_WIDTH 2 +#define K1C_SFR_ITOW_IT0_WFXL_MASK _ULL(0x3) +#define K1C_SFR_ITOW_IT0_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_ITOW_IT0_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_ITOW_IT1_MASK _ULL(0xc) /* Interrupt 1 owner */ +#define K1C_SFR_ITOW_IT1_SHIFT 2 +#define K1C_SFR_ITOW_IT1_WIDTH 2 +#define K1C_SFR_ITOW_IT1_WFXL_MASK _ULL(0xc) +#define K1C_SFR_ITOW_IT1_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_ITOW_IT1_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_ITOW_IT2_MASK _ULL(0x30) /* Interrupt 2 owner */ +#define K1C_SFR_ITOW_IT2_SHIFT 4 +#define K1C_SFR_ITOW_IT2_WIDTH 2 +#define K1C_SFR_ITOW_IT2_WFXL_MASK _ULL(0x30) +#define K1C_SFR_ITOW_IT2_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_ITOW_IT2_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_ITOW_IT3_MASK _ULL(0xc0) /* Interrupt 3 owner */ +#define K1C_SFR_ITOW_IT3_SHIFT 6 +#define K1C_SFR_ITOW_IT3_WIDTH 2 +#define K1C_SFR_ITOW_IT3_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_ITOW_IT3_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_ITOW_IT3_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_ITOW_IT4_MASK _ULL(0x300) /* Interrupt 4 owner */ +#define K1C_SFR_ITOW_IT4_SHIFT 8 +#define K1C_SFR_ITOW_IT4_WIDTH 2 +#define K1C_SFR_ITOW_IT4_WFXL_MASK _ULL(0x300) +#define K1C_SFR_ITOW_IT4_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_ITOW_IT4_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_ITOW_IT5_MASK _ULL(0xc00) /* Interrupt 5 owner */ +#define K1C_SFR_ITOW_IT5_SHIFT 10 +#define K1C_SFR_ITOW_IT5_WIDTH 2 +#define K1C_SFR_ITOW_IT5_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_ITOW_IT5_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_ITOW_IT5_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_ITOW_IT6_MASK _ULL(0x3000) /* Interrupt 6 owner */ +#define K1C_SFR_ITOW_IT6_SHIFT 12 +#define K1C_SFR_ITOW_IT6_WIDTH 2 +#define K1C_SFR_ITOW_IT6_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_ITOW_IT6_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_ITOW_IT6_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_ITOW_IT7_MASK _ULL(0xc000) /* Interrupt 7 owner */ +#define K1C_SFR_ITOW_IT7_SHIFT 14 +#define K1C_SFR_ITOW_IT7_WIDTH 2 +#define K1C_SFR_ITOW_IT7_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_ITOW_IT7_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_ITOW_IT7_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_ITOW_IT8_MASK _ULL(0x30000) /* Interrupt 8 owner */ +#define K1C_SFR_ITOW_IT8_SHIFT 16 +#define K1C_SFR_ITOW_IT8_WIDTH 2 +#define K1C_SFR_ITOW_IT8_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_ITOW_IT8_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_ITOW_IT8_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_ITOW_IT9_MASK _ULL(0xc0000) /* Interrupt 9 owner */ +#define K1C_SFR_ITOW_IT9_SHIFT 18 +#define K1C_SFR_ITOW_IT9_WIDTH 2 +#define K1C_SFR_ITOW_IT9_WFXL_MASK _ULL(0xc0000) +#define K1C_SFR_ITOW_IT9_WFXL_CLEAR _ULL(0xc0000) +#define K1C_SFR_ITOW_IT9_WFXL_SET _ULL(0xc000000000000) + +#define K1C_SFR_ITOW_IT10_MASK _ULL(0x300000) /* Interrupt 10 owner */ +#define K1C_SFR_ITOW_IT10_SHIFT 20 +#define K1C_SFR_ITOW_IT10_WIDTH 2 +#define K1C_SFR_ITOW_IT10_WFXL_MASK _ULL(0x300000) +#define K1C_SFR_ITOW_IT10_WFXL_CLEAR _ULL(0x300000) +#define K1C_SFR_ITOW_IT10_WFXL_SET _ULL(0x30000000000000) + +#define K1C_SFR_ITOW_IT11_MASK _ULL(0xc00000) /* Interrupt 11 owner */ +#define K1C_SFR_ITOW_IT11_SHIFT 22 +#define K1C_SFR_ITOW_IT11_WIDTH 2 +#define K1C_SFR_ITOW_IT11_WFXL_MASK _ULL(0xc00000) +#define K1C_SFR_ITOW_IT11_WFXL_CLEAR _ULL(0xc00000) +#define K1C_SFR_ITOW_IT11_WFXL_SET _ULL(0xc0000000000000) + +#define K1C_SFR_ITOW_IT12_MASK _ULL(0x3000000) /* Interrupt 12 owner */ +#define K1C_SFR_ITOW_IT12_SHIFT 24 +#define K1C_SFR_ITOW_IT12_WIDTH 2 +#define K1C_SFR_ITOW_IT12_WFXL_MASK _ULL(0x3000000) +#define K1C_SFR_ITOW_IT12_WFXL_CLEAR _ULL(0x3000000) +#define K1C_SFR_ITOW_IT12_WFXL_SET _ULL(0x300000000000000) + +#define K1C_SFR_ITOW_IT13_MASK _ULL(0xc000000) /* Interrupt 13 owner */ +#define K1C_SFR_ITOW_IT13_SHIFT 26 +#define K1C_SFR_ITOW_IT13_WIDTH 2 +#define K1C_SFR_ITOW_IT13_WFXL_MASK _ULL(0xc000000) +#define K1C_SFR_ITOW_IT13_WFXL_CLEAR _ULL(0xc000000) +#define K1C_SFR_ITOW_IT13_WFXL_SET _ULL(0xc00000000000000) + +#define K1C_SFR_ITOW_IT14_MASK _ULL(0x30000000) /* Interrupt 14 owner */ +#define K1C_SFR_ITOW_IT14_SHIFT 28 +#define K1C_SFR_ITOW_IT14_WIDTH 2 +#define K1C_SFR_ITOW_IT14_WFXL_MASK _ULL(0x30000000) +#define K1C_SFR_ITOW_IT14_WFXL_CLEAR _ULL(0x30000000) +#define K1C_SFR_ITOW_IT14_WFXL_SET _ULL(0x3000000000000000) + +#define K1C_SFR_ITOW_IT15_MASK _ULL(0xc0000000) /* Interrupt 15 owner */ +#define K1C_SFR_ITOW_IT15_SHIFT 30 +#define K1C_SFR_ITOW_IT15_WIDTH 2 +#define K1C_SFR_ITOW_IT15_WFXL_MASK _ULL(0xc0000000) +#define K1C_SFR_ITOW_IT15_WFXL_CLEAR _ULL(0xc0000000) +#define K1C_SFR_ITOW_IT15_WFXL_SET _ULL(0xc000000000000000) + +#define K1C_SFR_ITOW_IT16_MASK _ULL(0x300000000) /* Interrupt 16 owner */ +#define K1C_SFR_ITOW_IT16_SHIFT 32 +#define K1C_SFR_ITOW_IT16_WIDTH 2 +#define K1C_SFR_ITOW_IT16_WFXM_MASK _ULL(0x300000000) +#define K1C_SFR_ITOW_IT16_WFXM_CLEAR _ULL(0x3) +#define K1C_SFR_ITOW_IT16_WFXM_SET _ULL(0x300000000) + +#define K1C_SFR_ITOW_IT17_MASK _ULL(0xc00000000) /* Interrupt 17 owner */ +#define K1C_SFR_ITOW_IT17_SHIFT 34 +#define K1C_SFR_ITOW_IT17_WIDTH 2 +#define K1C_SFR_ITOW_IT17_WFXM_MASK _ULL(0xc00000000) +#define K1C_SFR_ITOW_IT17_WFXM_CLEAR _ULL(0xc) +#define K1C_SFR_ITOW_IT17_WFXM_SET _ULL(0xc00000000) + +#define K1C_SFR_ITOW_IT18_MASK _ULL(0x3000000000) /* Interrupt 18 owner */ +#define K1C_SFR_ITOW_IT18_SHIFT 36 +#define K1C_SFR_ITOW_IT18_WIDTH 2 +#define K1C_SFR_ITOW_IT18_WFXM_MASK _ULL(0x3000000000) +#define K1C_SFR_ITOW_IT18_WFXM_CLEAR _ULL(0x30) +#define K1C_SFR_ITOW_IT18_WFXM_SET _ULL(0x3000000000) + +#define K1C_SFR_ITOW_IT19_MASK _ULL(0xc000000000) /* Interrupt 19 owner */ +#define K1C_SFR_ITOW_IT19_SHIFT 38 +#define K1C_SFR_ITOW_IT19_WIDTH 2 +#define K1C_SFR_ITOW_IT19_WFXM_MASK _ULL(0xc000000000) +#define K1C_SFR_ITOW_IT19_WFXM_CLEAR _ULL(0xc0) +#define K1C_SFR_ITOW_IT19_WFXM_SET _ULL(0xc000000000) + +#define K1C_SFR_ITOW_IT20_MASK _ULL(0x30000000000) /* Interrupt 20 owner */ +#define K1C_SFR_ITOW_IT20_SHIFT 40 +#define K1C_SFR_ITOW_IT20_WIDTH 2 +#define K1C_SFR_ITOW_IT20_WFXM_MASK _ULL(0x30000000000) +#define K1C_SFR_ITOW_IT20_WFXM_CLEAR _ULL(0x300) +#define K1C_SFR_ITOW_IT20_WFXM_SET _ULL(0x30000000000) + +#define K1C_SFR_ITOW_IT21_MASK _ULL(0xc0000000000) /* Interrupt 21 owner */ +#define K1C_SFR_ITOW_IT21_SHIFT 42 +#define K1C_SFR_ITOW_IT21_WIDTH 2 +#define K1C_SFR_ITOW_IT21_WFXM_MASK _ULL(0xc0000000000) +#define K1C_SFR_ITOW_IT21_WFXM_CLEAR _ULL(0xc00) +#define K1C_SFR_ITOW_IT21_WFXM_SET _ULL(0xc0000000000) + +#define K1C_SFR_ITOW_IT22_MASK _ULL(0x300000000000) /* Interrupt 22 owner */ +#define K1C_SFR_ITOW_IT22_SHIFT 44 +#define K1C_SFR_ITOW_IT22_WIDTH 2 +#define K1C_SFR_ITOW_IT22_WFXM_MASK _ULL(0x300000000000) +#define K1C_SFR_ITOW_IT22_WFXM_CLEAR _ULL(0x3000) +#define K1C_SFR_ITOW_IT22_WFXM_SET _ULL(0x300000000000) + +#define K1C_SFR_ITOW_IT23_MASK _ULL(0xc00000000000) /* Interrupt 23 owner */ +#define K1C_SFR_ITOW_IT23_SHIFT 46 +#define K1C_SFR_ITOW_IT23_WIDTH 2 +#define K1C_SFR_ITOW_IT23_WFXM_MASK _ULL(0xc00000000000) +#define K1C_SFR_ITOW_IT23_WFXM_CLEAR _ULL(0xc000) +#define K1C_SFR_ITOW_IT23_WFXM_SET _ULL(0xc00000000000) + +#define K1C_SFR_ITOW_IT24_MASK _ULL(0x3000000000000) /* Interrupt 24 owner */ +#define K1C_SFR_ITOW_IT24_SHIFT 48 +#define K1C_SFR_ITOW_IT24_WIDTH 2 +#define K1C_SFR_ITOW_IT24_WFXM_MASK _ULL(0x3000000000000) +#define K1C_SFR_ITOW_IT24_WFXM_CLEAR _ULL(0x30000) +#define K1C_SFR_ITOW_IT24_WFXM_SET _ULL(0x3000000000000) + +#define K1C_SFR_ITOW_IT25_MASK _ULL(0xc000000000000) /* Interrupt 25 owner */ +#define K1C_SFR_ITOW_IT25_SHIFT 50 +#define K1C_SFR_ITOW_IT25_WIDTH 2 +#define K1C_SFR_ITOW_IT25_WFXM_MASK _ULL(0xc000000000000) +#define K1C_SFR_ITOW_IT25_WFXM_CLEAR _ULL(0xc0000) +#define K1C_SFR_ITOW_IT25_WFXM_SET _ULL(0xc000000000000) + +#define K1C_SFR_ITOW_IT26_MASK _ULL(0x30000000000000) /* Interrupt 26 owner */ +#define K1C_SFR_ITOW_IT26_SHIFT 52 +#define K1C_SFR_ITOW_IT26_WIDTH 2 +#define K1C_SFR_ITOW_IT26_WFXM_MASK _ULL(0x30000000000000) +#define K1C_SFR_ITOW_IT26_WFXM_CLEAR _ULL(0x300000) +#define K1C_SFR_ITOW_IT26_WFXM_SET _ULL(0x30000000000000) + +#define K1C_SFR_ITOW_IT27_MASK _ULL(0xc0000000000000) /* Interrupt 27 owner */ +#define K1C_SFR_ITOW_IT27_SHIFT 54 +#define K1C_SFR_ITOW_IT27_WIDTH 2 +#define K1C_SFR_ITOW_IT27_WFXM_MASK _ULL(0xc0000000000000) +#define K1C_SFR_ITOW_IT27_WFXM_CLEAR _ULL(0xc00000) +#define K1C_SFR_ITOW_IT27_WFXM_SET _ULL(0xc0000000000000) + +#define K1C_SFR_ITOW_IT28_MASK _ULL(0x300000000000000) /* Interrupt 28 owner */ +#define K1C_SFR_ITOW_IT28_SHIFT 56 +#define K1C_SFR_ITOW_IT28_WIDTH 2 +#define K1C_SFR_ITOW_IT28_WFXM_MASK _ULL(0x300000000000000) +#define K1C_SFR_ITOW_IT28_WFXM_CLEAR _ULL(0x3000000) +#define K1C_SFR_ITOW_IT28_WFXM_SET _ULL(0x300000000000000) + +#define K1C_SFR_ITOW_IT29_MASK _ULL(0xc00000000000000) /* Interrupt 29 owner */ +#define K1C_SFR_ITOW_IT29_SHIFT 58 +#define K1C_SFR_ITOW_IT29_WIDTH 2 +#define K1C_SFR_ITOW_IT29_WFXM_MASK _ULL(0xc00000000000000) +#define K1C_SFR_ITOW_IT29_WFXM_CLEAR _ULL(0xc000000) +#define K1C_SFR_ITOW_IT29_WFXM_SET _ULL(0xc00000000000000) + +#define K1C_SFR_ITOW_IT30_MASK _ULL(0x3000000000000000) /* Interrupt 30 owner */ +#define K1C_SFR_ITOW_IT30_SHIFT 60 +#define K1C_SFR_ITOW_IT30_WIDTH 2 +#define K1C_SFR_ITOW_IT30_WFXM_MASK _ULL(0x3000000000000000) +#define K1C_SFR_ITOW_IT30_WFXM_CLEAR _ULL(0x30000000) +#define K1C_SFR_ITOW_IT30_WFXM_SET _ULL(0x3000000000000000) + +#define K1C_SFR_ITOW_IT31_MASK _ULL(0xc000000000000000) /* Interrupt 31 owner */ +#define K1C_SFR_ITOW_IT31_SHIFT 62 +#define K1C_SFR_ITOW_IT31_WIDTH 2 +#define K1C_SFR_ITOW_IT31_WFXM_MASK _ULL(0xc000000000000000) +#define K1C_SFR_ITOW_IT31_WFXM_CLEAR _ULL(0xc0000000) +#define K1C_SFR_ITOW_IT31_WFXM_SET _ULL(0xc000000000000000) + +#define K1C_SFR_DO_B0_MASK _ULL(0x3) /* Breakpoint 0 owner. */ +#define K1C_SFR_DO_B0_SHIFT 0 +#define K1C_SFR_DO_B0_WIDTH 2 +#define K1C_SFR_DO_B0_WFXL_MASK _ULL(0x3) +#define K1C_SFR_DO_B0_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_DO_B0_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_DO_B1_MASK _ULL(0xc) /* Breakpoint 1 owner. */ +#define K1C_SFR_DO_B1_SHIFT 2 +#define K1C_SFR_DO_B1_WIDTH 2 +#define K1C_SFR_DO_B1_WFXL_MASK _ULL(0xc) +#define K1C_SFR_DO_B1_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_DO_B1_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_DO_W0_MASK _ULL(0x30) /* Watchpoint 0 owner. */ +#define K1C_SFR_DO_W0_SHIFT 4 +#define K1C_SFR_DO_W0_WIDTH 2 +#define K1C_SFR_DO_W0_WFXL_MASK _ULL(0x30) +#define K1C_SFR_DO_W0_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_DO_W0_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_DO_W1_MASK _ULL(0xc0) /* Watchpoint 1 owner. */ +#define K1C_SFR_DO_W1_SHIFT 6 +#define K1C_SFR_DO_W1_WIDTH 2 +#define K1C_SFR_DO_W1_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_DO_W1_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_DO_W1_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_DBA0_DBA0_MASK _ULL(0xffffffffffffffff) /* Debug Breakpoint Address 0 */ +#define K1C_SFR_DBA0_DBA0_SHIFT 0 +#define K1C_SFR_DBA0_DBA0_WIDTH 64 +#define K1C_SFR_DBA0_DBA0_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_DBA0_DBA0_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_DBA0_DBA0_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_DBA0_DBA0_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_DBA0_DBA0_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_DBA0_DBA0_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_DBA1_DBA1_MASK _ULL(0xffffffffffffffff) /* Debug Breakpoint Address 1 */ +#define K1C_SFR_DBA1_DBA1_SHIFT 0 +#define K1C_SFR_DBA1_DBA1_WIDTH 64 +#define K1C_SFR_DBA1_DBA1_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_DBA1_DBA1_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_DBA1_DBA1_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_DBA1_DBA1_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_DBA1_DBA1_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_DBA1_DBA1_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_DWA0_DWA0_MASK _ULL(0xffffffffffffffff) /* Debug Breakpoint Address 0 */ +#define K1C_SFR_DWA0_DWA0_SHIFT 0 +#define K1C_SFR_DWA0_DWA0_WIDTH 64 +#define K1C_SFR_DWA0_DWA0_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_DWA0_DWA0_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_DWA0_DWA0_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_DWA0_DWA0_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_DWA0_DWA0_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_DWA0_DWA0_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_DWA1_DWA1_MASK _ULL(0xffffffffffffffff) /* Debug Breakpoint Address 1 */ +#define K1C_SFR_DWA1_DWA1_SHIFT 0 +#define K1C_SFR_DWA1_DWA1_WIDTH 64 +#define K1C_SFR_DWA1_DWA1_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_DWA1_DWA1_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_DWA1_DWA1_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_DWA1_DWA1_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_DWA1_DWA1_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_DWA1_DWA1_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_DOW_B0_MASK _ULL(0x3) /* Breakpoint 0 owner. */ +#define K1C_SFR_DOW_B0_SHIFT 0 +#define K1C_SFR_DOW_B0_WIDTH 2 +#define K1C_SFR_DOW_B0_WFXL_MASK _ULL(0x3) +#define K1C_SFR_DOW_B0_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_DOW_B0_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_DOW_B1_MASK _ULL(0xc) /* Breakpoint 1 owner. */ +#define K1C_SFR_DOW_B1_SHIFT 2 +#define K1C_SFR_DOW_B1_WIDTH 2 +#define K1C_SFR_DOW_B1_WFXL_MASK _ULL(0xc) +#define K1C_SFR_DOW_B1_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_DOW_B1_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_DOW_W0_MASK _ULL(0x30) /* Watchpoint 0 owner. */ +#define K1C_SFR_DOW_W0_SHIFT 4 +#define K1C_SFR_DOW_W0_WIDTH 2 +#define K1C_SFR_DOW_W0_WFXL_MASK _ULL(0x30) +#define K1C_SFR_DOW_W0_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_DOW_W0_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_DOW_W1_MASK _ULL(0xc0) /* Watchpoint 1 owner. */ +#define K1C_SFR_DOW_W1_SHIFT 6 +#define K1C_SFR_DOW_W1_WIDTH 2 +#define K1C_SFR_DOW_W1_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_DOW_W1_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_DOW_W1_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_MO_MMI_MASK _ULL(0x3) /* Memory Management Instructions owner. */ +#define K1C_SFR_MO_MMI_SHIFT 0 +#define K1C_SFR_MO_MMI_WIDTH 2 +#define K1C_SFR_MO_MMI_WFXL_MASK _ULL(0x3) +#define K1C_SFR_MO_MMI_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_MO_MMI_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_MO_RFE_MASK _ULL(0xc) /* RFE instruction owner. */ +#define K1C_SFR_MO_RFE_SHIFT 2 +#define K1C_SFR_MO_RFE_WIDTH 2 +#define K1C_SFR_MO_RFE_WFXL_MASK _ULL(0xc) +#define K1C_SFR_MO_RFE_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_MO_RFE_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_MO_STOP_MASK _ULL(0x30) /* STOP instruction owner. */ +#define K1C_SFR_MO_STOP_SHIFT 4 +#define K1C_SFR_MO_STOP_WIDTH 2 +#define K1C_SFR_MO_STOP_WFXL_MASK _ULL(0x30) +#define K1C_SFR_MO_STOP_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_MO_STOP_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_MO_SYNC_MASK _ULL(0xc0) /* SYNCGROUP instruction owner. */ +#define K1C_SFR_MO_SYNC_SHIFT 6 +#define K1C_SFR_MO_SYNC_WIDTH 2 +#define K1C_SFR_MO_SYNC_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_MO_SYNC_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_MO_SYNC_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_MO_PCR_MASK _ULL(0x300) /* PCR register owner. */ +#define K1C_SFR_MO_PCR_SHIFT 8 +#define K1C_SFR_MO_PCR_WIDTH 2 +#define K1C_SFR_MO_PCR_WFXL_MASK _ULL(0x300) +#define K1C_SFR_MO_PCR_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_MO_PCR_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_MO_MSG_MASK _ULL(0xc00) /* MMU SFR GROUP registers owner. */ +#define K1C_SFR_MO_MSG_SHIFT 10 +#define K1C_SFR_MO_MSG_WIDTH 2 +#define K1C_SFR_MO_MSG_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_MO_MSG_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_MO_MSG_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_MO_MEN_MASK _ULL(0x3000) /* Miscellaneous External Notifications register owner. */ +#define K1C_SFR_MO_MEN_SHIFT 12 +#define K1C_SFR_MO_MEN_WIDTH 2 +#define K1C_SFR_MO_MEN_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_MO_MEN_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_MO_MEN_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_MO_MES_MASK _ULL(0xc000) /* Memory Error Status register owner. */ +#define K1C_SFR_MO_MES_SHIFT 14 +#define K1C_SFR_MO_MES_WIDTH 2 +#define K1C_SFR_MO_MES_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_MO_MES_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_MO_MES_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_MO_CSIT_MASK _ULL(0x30000) /* Compute Status Artithmetic Interrupt register owner. */ +#define K1C_SFR_MO_CSIT_SHIFT 16 +#define K1C_SFR_MO_CSIT_WIDTH 2 +#define K1C_SFR_MO_CSIT_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_MO_CSIT_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_MO_CSIT_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_MO_T0_MASK _ULL(0xc0000) /* Timer 0 register group owner */ +#define K1C_SFR_MO_T0_SHIFT 18 +#define K1C_SFR_MO_T0_WIDTH 2 +#define K1C_SFR_MO_T0_WFXL_MASK _ULL(0xc0000) +#define K1C_SFR_MO_T0_WFXL_CLEAR _ULL(0xc0000) +#define K1C_SFR_MO_T0_WFXL_SET _ULL(0xc000000000000) + +#define K1C_SFR_MO_T1_MASK _ULL(0x300000) /* Timer 1 register group owner */ +#define K1C_SFR_MO_T1_SHIFT 20 +#define K1C_SFR_MO_T1_WIDTH 2 +#define K1C_SFR_MO_T1_WFXL_MASK _ULL(0x300000) +#define K1C_SFR_MO_T1_WFXL_CLEAR _ULL(0x300000) +#define K1C_SFR_MO_T1_WFXL_SET _ULL(0x30000000000000) + +#define K1C_SFR_MO_WD_MASK _ULL(0xc00000) /* Watch Dog register group owner. */ +#define K1C_SFR_MO_WD_SHIFT 22 +#define K1C_SFR_MO_WD_WIDTH 2 +#define K1C_SFR_MO_WD_WFXL_MASK _ULL(0xc00000) +#define K1C_SFR_MO_WD_WFXL_CLEAR _ULL(0xc00000) +#define K1C_SFR_MO_WD_WFXL_SET _ULL(0xc0000000000000) + +#define K1C_SFR_MO_PM0_MASK _ULL(0x3000000) /* Performance Monitor 0 register owner. */ +#define K1C_SFR_MO_PM0_SHIFT 24 +#define K1C_SFR_MO_PM0_WIDTH 2 +#define K1C_SFR_MO_PM0_WFXL_MASK _ULL(0x3000000) +#define K1C_SFR_MO_PM0_WFXL_CLEAR _ULL(0x3000000) +#define K1C_SFR_MO_PM0_WFXL_SET _ULL(0x300000000000000) + +#define K1C_SFR_MO_PM1_MASK _ULL(0xc000000) /* Performance Monitor 1 register owner. */ +#define K1C_SFR_MO_PM1_SHIFT 26 +#define K1C_SFR_MO_PM1_WIDTH 2 +#define K1C_SFR_MO_PM1_WFXL_MASK _ULL(0xc000000) +#define K1C_SFR_MO_PM1_WFXL_CLEAR _ULL(0xc000000) +#define K1C_SFR_MO_PM1_WFXL_SET _ULL(0xc00000000000000) + +#define K1C_SFR_MO_PM2_MASK _ULL(0x30000000) /* Performance Monitor 2 register owner. */ +#define K1C_SFR_MO_PM2_SHIFT 28 +#define K1C_SFR_MO_PM2_WIDTH 2 +#define K1C_SFR_MO_PM2_WFXL_MASK _ULL(0x30000000) +#define K1C_SFR_MO_PM2_WFXL_CLEAR _ULL(0x30000000) +#define K1C_SFR_MO_PM2_WFXL_SET _ULL(0x3000000000000000) + +#define K1C_SFR_MO_PM3_MASK _ULL(0xc0000000) /* Performance Monitor 3 register owner. */ +#define K1C_SFR_MO_PM3_SHIFT 30 +#define K1C_SFR_MO_PM3_WIDTH 2 +#define K1C_SFR_MO_PM3_WFXL_MASK _ULL(0xc0000000) +#define K1C_SFR_MO_PM3_WFXL_CLEAR _ULL(0xc0000000) +#define K1C_SFR_MO_PM3_WFXL_SET _ULL(0xc000000000000000) + +#define K1C_SFR_MO_PMIT_MASK _ULL(0x300000000) /* Performance Monitor Interrupt register group owner. */ +#define K1C_SFR_MO_PMIT_SHIFT 32 +#define K1C_SFR_MO_PMIT_WIDTH 2 +#define K1C_SFR_MO_PMIT_WFXM_MASK _ULL(0x300000000) +#define K1C_SFR_MO_PMIT_WFXM_CLEAR _ULL(0x3) +#define K1C_SFR_MO_PMIT_WFXM_SET _ULL(0x300000000) + +#define K1C_SFR_MOW_MMI_MASK _ULL(0x3) /* Memory Management Instructions owner. */ +#define K1C_SFR_MOW_MMI_SHIFT 0 +#define K1C_SFR_MOW_MMI_WIDTH 2 +#define K1C_SFR_MOW_MMI_WFXL_MASK _ULL(0x3) +#define K1C_SFR_MOW_MMI_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_MOW_MMI_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_MOW_RFE_MASK _ULL(0xc) /* RFE instruction owner. */ +#define K1C_SFR_MOW_RFE_SHIFT 2 +#define K1C_SFR_MOW_RFE_WIDTH 2 +#define K1C_SFR_MOW_RFE_WFXL_MASK _ULL(0xc) +#define K1C_SFR_MOW_RFE_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_MOW_RFE_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_MOW_STOP_MASK _ULL(0x30) /* STOP instruction owner. */ +#define K1C_SFR_MOW_STOP_SHIFT 4 +#define K1C_SFR_MOW_STOP_WIDTH 2 +#define K1C_SFR_MOW_STOP_WFXL_MASK _ULL(0x30) +#define K1C_SFR_MOW_STOP_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_MOW_STOP_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_MOW_SYNC_MASK _ULL(0xc0) /* SYNCGROUP instruction owner. */ +#define K1C_SFR_MOW_SYNC_SHIFT 6 +#define K1C_SFR_MOW_SYNC_WIDTH 2 +#define K1C_SFR_MOW_SYNC_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_MOW_SYNC_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_MOW_SYNC_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_MOW_PCR_MASK _ULL(0x300) /* PCR register owner. */ +#define K1C_SFR_MOW_PCR_SHIFT 8 +#define K1C_SFR_MOW_PCR_WIDTH 2 +#define K1C_SFR_MOW_PCR_WFXL_MASK _ULL(0x300) +#define K1C_SFR_MOW_PCR_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_MOW_PCR_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_MOW_MSG_MASK _ULL(0xc00) /* MMU SFR GROUP registers owner. */ +#define K1C_SFR_MOW_MSG_SHIFT 10 +#define K1C_SFR_MOW_MSG_WIDTH 2 +#define K1C_SFR_MOW_MSG_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_MOW_MSG_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_MOW_MSG_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_MOW_MEN_MASK _ULL(0x3000) /* Miscellaneous External Notifications register owner. */ +#define K1C_SFR_MOW_MEN_SHIFT 12 +#define K1C_SFR_MOW_MEN_WIDTH 2 +#define K1C_SFR_MOW_MEN_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_MOW_MEN_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_MOW_MEN_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_MOW_MES_MASK _ULL(0xc000) /* Memory Error Status register owner. */ +#define K1C_SFR_MOW_MES_SHIFT 14 +#define K1C_SFR_MOW_MES_WIDTH 2 +#define K1C_SFR_MOW_MES_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_MOW_MES_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_MOW_MES_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_MOW_CSIT_MASK _ULL(0x30000) /* Compute Status Artithmetic Interrupt register owner. */ +#define K1C_SFR_MOW_CSIT_SHIFT 16 +#define K1C_SFR_MOW_CSIT_WIDTH 2 +#define K1C_SFR_MOW_CSIT_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_MOW_CSIT_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_MOW_CSIT_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_MOW_T0_MASK _ULL(0xc0000) /* Timer 0 register group owner */ +#define K1C_SFR_MOW_T0_SHIFT 18 +#define K1C_SFR_MOW_T0_WIDTH 2 +#define K1C_SFR_MOW_T0_WFXL_MASK _ULL(0xc0000) +#define K1C_SFR_MOW_T0_WFXL_CLEAR _ULL(0xc0000) +#define K1C_SFR_MOW_T0_WFXL_SET _ULL(0xc000000000000) + +#define K1C_SFR_MOW_T1_MASK _ULL(0x300000) /* Timer 1 register group owner */ +#define K1C_SFR_MOW_T1_SHIFT 20 +#define K1C_SFR_MOW_T1_WIDTH 2 +#define K1C_SFR_MOW_T1_WFXL_MASK _ULL(0x300000) +#define K1C_SFR_MOW_T1_WFXL_CLEAR _ULL(0x300000) +#define K1C_SFR_MOW_T1_WFXL_SET _ULL(0x30000000000000) + +#define K1C_SFR_MOW_WD_MASK _ULL(0xc00000) /* Watch Dog register group owner. */ +#define K1C_SFR_MOW_WD_SHIFT 22 +#define K1C_SFR_MOW_WD_WIDTH 2 +#define K1C_SFR_MOW_WD_WFXL_MASK _ULL(0xc00000) +#define K1C_SFR_MOW_WD_WFXL_CLEAR _ULL(0xc00000) +#define K1C_SFR_MOW_WD_WFXL_SET _ULL(0xc0000000000000) + +#define K1C_SFR_MOW_PM0_MASK _ULL(0x3000000) /* Performance Monitor 0 register owner. */ +#define K1C_SFR_MOW_PM0_SHIFT 24 +#define K1C_SFR_MOW_PM0_WIDTH 2 +#define K1C_SFR_MOW_PM0_WFXL_MASK _ULL(0x3000000) +#define K1C_SFR_MOW_PM0_WFXL_CLEAR _ULL(0x3000000) +#define K1C_SFR_MOW_PM0_WFXL_SET _ULL(0x300000000000000) + +#define K1C_SFR_MOW_PM1_MASK _ULL(0xc000000) /* Performance Monitor 1 register owner. */ +#define K1C_SFR_MOW_PM1_SHIFT 26 +#define K1C_SFR_MOW_PM1_WIDTH 2 +#define K1C_SFR_MOW_PM1_WFXL_MASK _ULL(0xc000000) +#define K1C_SFR_MOW_PM1_WFXL_CLEAR _ULL(0xc000000) +#define K1C_SFR_MOW_PM1_WFXL_SET _ULL(0xc00000000000000) + +#define K1C_SFR_MOW_PM2_MASK _ULL(0x30000000) /* Performance Monitor 2 register owner. */ +#define K1C_SFR_MOW_PM2_SHIFT 28 +#define K1C_SFR_MOW_PM2_WIDTH 2 +#define K1C_SFR_MOW_PM2_WFXL_MASK _ULL(0x30000000) +#define K1C_SFR_MOW_PM2_WFXL_CLEAR _ULL(0x30000000) +#define K1C_SFR_MOW_PM2_WFXL_SET _ULL(0x3000000000000000) + +#define K1C_SFR_MOW_PM3_MASK _ULL(0xc0000000) /* Performance Monitor 3 register owner. */ +#define K1C_SFR_MOW_PM3_SHIFT 30 +#define K1C_SFR_MOW_PM3_WIDTH 2 +#define K1C_SFR_MOW_PM3_WFXL_MASK _ULL(0xc0000000) +#define K1C_SFR_MOW_PM3_WFXL_CLEAR _ULL(0xc0000000) +#define K1C_SFR_MOW_PM3_WFXL_SET _ULL(0xc000000000000000) + +#define K1C_SFR_MOW_PMIT_MASK _ULL(0x300000000) /* Performance Monitor Interrupt register group owner. */ +#define K1C_SFR_MOW_PMIT_SHIFT 32 +#define K1C_SFR_MOW_PMIT_WIDTH 2 +#define K1C_SFR_MOW_PMIT_WFXM_MASK _ULL(0x300000000) +#define K1C_SFR_MOW_PMIT_WFXM_CLEAR _ULL(0x3) +#define K1C_SFR_MOW_PMIT_WFXM_SET _ULL(0x300000000) + +#define K1C_SFR_PS_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define K1C_SFR_PS_PL_SHIFT 0 +#define K1C_SFR_PS_PL_WIDTH 2 +#define K1C_SFR_PS_PL_WFXL_MASK _ULL(0x3) +#define K1C_SFR_PS_PL_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_PS_PL_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_PS_ET_MASK _ULL(0x4) /* Exception Taken */ +#define K1C_SFR_PS_ET_SHIFT 2 +#define K1C_SFR_PS_ET_WIDTH 1 +#define K1C_SFR_PS_ET_WFXL_MASK _ULL(0x4) +#define K1C_SFR_PS_ET_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_PS_ET_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_PS_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define K1C_SFR_PS_HTD_SHIFT 3 +#define K1C_SFR_PS_HTD_WIDTH 1 +#define K1C_SFR_PS_HTD_WFXL_MASK _ULL(0x8) +#define K1C_SFR_PS_HTD_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_PS_HTD_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_PS_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define K1C_SFR_PS_IE_SHIFT 4 +#define K1C_SFR_PS_IE_WIDTH 1 +#define K1C_SFR_PS_IE_WFXL_MASK _ULL(0x10) +#define K1C_SFR_PS_IE_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_PS_IE_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_PS_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define K1C_SFR_PS_HLE_SHIFT 5 +#define K1C_SFR_PS_HLE_WIDTH 1 +#define K1C_SFR_PS_HLE_WFXL_MASK _ULL(0x20) +#define K1C_SFR_PS_HLE_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_PS_HLE_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_PS_SRE_MASK _ULL(0x40) /* Software REserved */ +#define K1C_SFR_PS_SRE_SHIFT 6 +#define K1C_SFR_PS_SRE_WIDTH 1 +#define K1C_SFR_PS_SRE_WFXL_MASK _ULL(0x40) +#define K1C_SFR_PS_SRE_WFXL_CLEAR _ULL(0x40) +#define K1C_SFR_PS_SRE_WFXL_SET _ULL(0x4000000000) + +#define K1C_SFR_PS_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define K1C_SFR_PS_DAUS_SHIFT 7 +#define K1C_SFR_PS_DAUS_WIDTH 1 +#define K1C_SFR_PS_DAUS_WFXL_MASK _ULL(0x80) +#define K1C_SFR_PS_DAUS_WFXL_CLEAR _ULL(0x80) +#define K1C_SFR_PS_DAUS_WFXL_SET _ULL(0x8000000000) + +#define K1C_SFR_PS_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define K1C_SFR_PS_ICE_SHIFT 8 +#define K1C_SFR_PS_ICE_WIDTH 1 +#define K1C_SFR_PS_ICE_WFXL_MASK _ULL(0x100) +#define K1C_SFR_PS_ICE_WFXL_CLEAR _ULL(0x100) +#define K1C_SFR_PS_ICE_WFXL_SET _ULL(0x10000000000) + +#define K1C_SFR_PS_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define K1C_SFR_PS_USE_SHIFT 9 +#define K1C_SFR_PS_USE_WIDTH 1 +#define K1C_SFR_PS_USE_WFXL_MASK _ULL(0x200) +#define K1C_SFR_PS_USE_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_PS_USE_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_PS_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define K1C_SFR_PS_DCE_SHIFT 10 +#define K1C_SFR_PS_DCE_WIDTH 1 +#define K1C_SFR_PS_DCE_WFXL_MASK _ULL(0x400) +#define K1C_SFR_PS_DCE_WFXL_CLEAR _ULL(0x400) +#define K1C_SFR_PS_DCE_WFXL_SET _ULL(0x40000000000) + +#define K1C_SFR_PS_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define K1C_SFR_PS_MME_SHIFT 11 +#define K1C_SFR_PS_MME_WIDTH 1 +#define K1C_SFR_PS_MME_WFXL_MASK _ULL(0x800) +#define K1C_SFR_PS_MME_WFXL_CLEAR _ULL(0x800) +#define K1C_SFR_PS_MME_WFXL_SET _ULL(0x80000000000) + +#define K1C_SFR_PS_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define K1C_SFR_PS_IL_SHIFT 12 +#define K1C_SFR_PS_IL_WIDTH 2 +#define K1C_SFR_PS_IL_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_PS_IL_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_PS_IL_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_PS_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define K1C_SFR_PS_VS_SHIFT 14 +#define K1C_SFR_PS_VS_WIDTH 2 +#define K1C_SFR_PS_VS_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_PS_VS_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_PS_VS_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_PS_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define K1C_SFR_PS_V64_SHIFT 16 +#define K1C_SFR_PS_V64_WIDTH 1 +#define K1C_SFR_PS_V64_WFXL_MASK _ULL(0x10000) +#define K1C_SFR_PS_V64_WFXL_CLEAR _ULL(0x10000) +#define K1C_SFR_PS_V64_WFXL_SET _ULL(0x1000000000000) + +#define K1C_SFR_PS_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define K1C_SFR_PS_L2E_SHIFT 17 +#define K1C_SFR_PS_L2E_WIDTH 1 +#define K1C_SFR_PS_L2E_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_PS_L2E_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_PS_L2E_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_PS_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define K1C_SFR_PS_SME_SHIFT 18 +#define K1C_SFR_PS_SME_WIDTH 1 +#define K1C_SFR_PS_SME_WFXL_MASK _ULL(0x40000) +#define K1C_SFR_PS_SME_WFXL_CLEAR _ULL(0x40000) +#define K1C_SFR_PS_SME_WFXL_SET _ULL(0x4000000000000) + +#define K1C_SFR_PS_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define K1C_SFR_PS_SMR_SHIFT 19 +#define K1C_SFR_PS_SMR_WIDTH 1 +#define K1C_SFR_PS_SMR_WFXL_MASK _ULL(0x80000) +#define K1C_SFR_PS_SMR_WFXL_CLEAR _ULL(0x80000) +#define K1C_SFR_PS_SMR_WFXL_SET _ULL(0x8000000000000) + +#define K1C_SFR_PS_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define K1C_SFR_PS_PMJ_SHIFT 20 +#define K1C_SFR_PS_PMJ_WIDTH 4 +#define K1C_SFR_PS_PMJ_WFXL_MASK _ULL(0xf00000) +#define K1C_SFR_PS_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define K1C_SFR_PS_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define K1C_SFR_PS_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define K1C_SFR_PS_MMUP_SHIFT 24 +#define K1C_SFR_PS_MMUP_WIDTH 1 +#define K1C_SFR_PS_MMUP_WFXL_MASK _ULL(0x1000000) +#define K1C_SFR_PS_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define K1C_SFR_PS_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define K1C_SFR_SPS_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define K1C_SFR_SPS_PL_SHIFT 0 +#define K1C_SFR_SPS_PL_WIDTH 2 +#define K1C_SFR_SPS_PL_WFXL_MASK _ULL(0x3) +#define K1C_SFR_SPS_PL_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_SPS_PL_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_SPS_ET_MASK _ULL(0x4) /* Exception Taken */ +#define K1C_SFR_SPS_ET_SHIFT 2 +#define K1C_SFR_SPS_ET_WIDTH 1 +#define K1C_SFR_SPS_ET_WFXL_MASK _ULL(0x4) +#define K1C_SFR_SPS_ET_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_SPS_ET_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_SPS_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define K1C_SFR_SPS_HTD_SHIFT 3 +#define K1C_SFR_SPS_HTD_WIDTH 1 +#define K1C_SFR_SPS_HTD_WFXL_MASK _ULL(0x8) +#define K1C_SFR_SPS_HTD_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_SPS_HTD_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_SPS_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define K1C_SFR_SPS_IE_SHIFT 4 +#define K1C_SFR_SPS_IE_WIDTH 1 +#define K1C_SFR_SPS_IE_WFXL_MASK _ULL(0x10) +#define K1C_SFR_SPS_IE_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_SPS_IE_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_SPS_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define K1C_SFR_SPS_HLE_SHIFT 5 +#define K1C_SFR_SPS_HLE_WIDTH 1 +#define K1C_SFR_SPS_HLE_WFXL_MASK _ULL(0x20) +#define K1C_SFR_SPS_HLE_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_SPS_HLE_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_SPS_SRE_MASK _ULL(0x40) /* Software REserved */ +#define K1C_SFR_SPS_SRE_SHIFT 6 +#define K1C_SFR_SPS_SRE_WIDTH 1 +#define K1C_SFR_SPS_SRE_WFXL_MASK _ULL(0x40) +#define K1C_SFR_SPS_SRE_WFXL_CLEAR _ULL(0x40) +#define K1C_SFR_SPS_SRE_WFXL_SET _ULL(0x4000000000) + +#define K1C_SFR_SPS_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define K1C_SFR_SPS_DAUS_SHIFT 7 +#define K1C_SFR_SPS_DAUS_WIDTH 1 +#define K1C_SFR_SPS_DAUS_WFXL_MASK _ULL(0x80) +#define K1C_SFR_SPS_DAUS_WFXL_CLEAR _ULL(0x80) +#define K1C_SFR_SPS_DAUS_WFXL_SET _ULL(0x8000000000) + +#define K1C_SFR_SPS_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define K1C_SFR_SPS_ICE_SHIFT 8 +#define K1C_SFR_SPS_ICE_WIDTH 1 +#define K1C_SFR_SPS_ICE_WFXL_MASK _ULL(0x100) +#define K1C_SFR_SPS_ICE_WFXL_CLEAR _ULL(0x100) +#define K1C_SFR_SPS_ICE_WFXL_SET _ULL(0x10000000000) + +#define K1C_SFR_SPS_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define K1C_SFR_SPS_USE_SHIFT 9 +#define K1C_SFR_SPS_USE_WIDTH 1 +#define K1C_SFR_SPS_USE_WFXL_MASK _ULL(0x200) +#define K1C_SFR_SPS_USE_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_SPS_USE_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_SPS_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define K1C_SFR_SPS_DCE_SHIFT 10 +#define K1C_SFR_SPS_DCE_WIDTH 1 +#define K1C_SFR_SPS_DCE_WFXL_MASK _ULL(0x400) +#define K1C_SFR_SPS_DCE_WFXL_CLEAR _ULL(0x400) +#define K1C_SFR_SPS_DCE_WFXL_SET _ULL(0x40000000000) + +#define K1C_SFR_SPS_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define K1C_SFR_SPS_MME_SHIFT 11 +#define K1C_SFR_SPS_MME_WIDTH 1 +#define K1C_SFR_SPS_MME_WFXL_MASK _ULL(0x800) +#define K1C_SFR_SPS_MME_WFXL_CLEAR _ULL(0x800) +#define K1C_SFR_SPS_MME_WFXL_SET _ULL(0x80000000000) + +#define K1C_SFR_SPS_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define K1C_SFR_SPS_IL_SHIFT 12 +#define K1C_SFR_SPS_IL_WIDTH 2 +#define K1C_SFR_SPS_IL_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_SPS_IL_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_SPS_IL_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_SPS_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define K1C_SFR_SPS_VS_SHIFT 14 +#define K1C_SFR_SPS_VS_WIDTH 2 +#define K1C_SFR_SPS_VS_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_SPS_VS_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_SPS_VS_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_SPS_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define K1C_SFR_SPS_V64_SHIFT 16 +#define K1C_SFR_SPS_V64_WIDTH 1 +#define K1C_SFR_SPS_V64_WFXL_MASK _ULL(0x10000) +#define K1C_SFR_SPS_V64_WFXL_CLEAR _ULL(0x10000) +#define K1C_SFR_SPS_V64_WFXL_SET _ULL(0x1000000000000) + +#define K1C_SFR_SPS_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define K1C_SFR_SPS_L2E_SHIFT 17 +#define K1C_SFR_SPS_L2E_WIDTH 1 +#define K1C_SFR_SPS_L2E_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_SPS_L2E_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_SPS_L2E_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_SPS_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define K1C_SFR_SPS_SME_SHIFT 18 +#define K1C_SFR_SPS_SME_WIDTH 1 +#define K1C_SFR_SPS_SME_WFXL_MASK _ULL(0x40000) +#define K1C_SFR_SPS_SME_WFXL_CLEAR _ULL(0x40000) +#define K1C_SFR_SPS_SME_WFXL_SET _ULL(0x4000000000000) + +#define K1C_SFR_SPS_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define K1C_SFR_SPS_SMR_SHIFT 19 +#define K1C_SFR_SPS_SMR_WIDTH 1 +#define K1C_SFR_SPS_SMR_WFXL_MASK _ULL(0x80000) +#define K1C_SFR_SPS_SMR_WFXL_CLEAR _ULL(0x80000) +#define K1C_SFR_SPS_SMR_WFXL_SET _ULL(0x8000000000000) + +#define K1C_SFR_SPS_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define K1C_SFR_SPS_PMJ_SHIFT 20 +#define K1C_SFR_SPS_PMJ_WIDTH 4 +#define K1C_SFR_SPS_PMJ_WFXL_MASK _ULL(0xf00000) +#define K1C_SFR_SPS_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define K1C_SFR_SPS_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define K1C_SFR_SPS_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define K1C_SFR_SPS_MMUP_SHIFT 24 +#define K1C_SFR_SPS_MMUP_WIDTH 1 +#define K1C_SFR_SPS_MMUP_WFXL_MASK _ULL(0x1000000) +#define K1C_SFR_SPS_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define K1C_SFR_SPS_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define K1C_SFR_SPS_PL0_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define K1C_SFR_SPS_PL0_PL_SHIFT 0 +#define K1C_SFR_SPS_PL0_PL_WIDTH 2 +#define K1C_SFR_SPS_PL0_PL_WFXL_MASK _ULL(0x3) +#define K1C_SFR_SPS_PL0_PL_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_SPS_PL0_PL_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_SPS_PL0_ET_MASK _ULL(0x4) /* Exception Taken */ +#define K1C_SFR_SPS_PL0_ET_SHIFT 2 +#define K1C_SFR_SPS_PL0_ET_WIDTH 1 +#define K1C_SFR_SPS_PL0_ET_WFXL_MASK _ULL(0x4) +#define K1C_SFR_SPS_PL0_ET_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_SPS_PL0_ET_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_SPS_PL0_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define K1C_SFR_SPS_PL0_HTD_SHIFT 3 +#define K1C_SFR_SPS_PL0_HTD_WIDTH 1 +#define K1C_SFR_SPS_PL0_HTD_WFXL_MASK _ULL(0x8) +#define K1C_SFR_SPS_PL0_HTD_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_SPS_PL0_HTD_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_SPS_PL0_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define K1C_SFR_SPS_PL0_IE_SHIFT 4 +#define K1C_SFR_SPS_PL0_IE_WIDTH 1 +#define K1C_SFR_SPS_PL0_IE_WFXL_MASK _ULL(0x10) +#define K1C_SFR_SPS_PL0_IE_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_SPS_PL0_IE_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_SPS_PL0_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define K1C_SFR_SPS_PL0_HLE_SHIFT 5 +#define K1C_SFR_SPS_PL0_HLE_WIDTH 1 +#define K1C_SFR_SPS_PL0_HLE_WFXL_MASK _ULL(0x20) +#define K1C_SFR_SPS_PL0_HLE_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_SPS_PL0_HLE_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_SPS_PL0_SRE_MASK _ULL(0x40) /* Software REserved */ +#define K1C_SFR_SPS_PL0_SRE_SHIFT 6 +#define K1C_SFR_SPS_PL0_SRE_WIDTH 1 +#define K1C_SFR_SPS_PL0_SRE_WFXL_MASK _ULL(0x40) +#define K1C_SFR_SPS_PL0_SRE_WFXL_CLEAR _ULL(0x40) +#define K1C_SFR_SPS_PL0_SRE_WFXL_SET _ULL(0x4000000000) + +#define K1C_SFR_SPS_PL0_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define K1C_SFR_SPS_PL0_DAUS_SHIFT 7 +#define K1C_SFR_SPS_PL0_DAUS_WIDTH 1 +#define K1C_SFR_SPS_PL0_DAUS_WFXL_MASK _ULL(0x80) +#define K1C_SFR_SPS_PL0_DAUS_WFXL_CLEAR _ULL(0x80) +#define K1C_SFR_SPS_PL0_DAUS_WFXL_SET _ULL(0x8000000000) + +#define K1C_SFR_SPS_PL0_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define K1C_SFR_SPS_PL0_ICE_SHIFT 8 +#define K1C_SFR_SPS_PL0_ICE_WIDTH 1 +#define K1C_SFR_SPS_PL0_ICE_WFXL_MASK _ULL(0x100) +#define K1C_SFR_SPS_PL0_ICE_WFXL_CLEAR _ULL(0x100) +#define K1C_SFR_SPS_PL0_ICE_WFXL_SET _ULL(0x10000000000) + +#define K1C_SFR_SPS_PL0_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define K1C_SFR_SPS_PL0_USE_SHIFT 9 +#define K1C_SFR_SPS_PL0_USE_WIDTH 1 +#define K1C_SFR_SPS_PL0_USE_WFXL_MASK _ULL(0x200) +#define K1C_SFR_SPS_PL0_USE_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_SPS_PL0_USE_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_SPS_PL0_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define K1C_SFR_SPS_PL0_DCE_SHIFT 10 +#define K1C_SFR_SPS_PL0_DCE_WIDTH 1 +#define K1C_SFR_SPS_PL0_DCE_WFXL_MASK _ULL(0x400) +#define K1C_SFR_SPS_PL0_DCE_WFXL_CLEAR _ULL(0x400) +#define K1C_SFR_SPS_PL0_DCE_WFXL_SET _ULL(0x40000000000) + +#define K1C_SFR_SPS_PL0_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define K1C_SFR_SPS_PL0_MME_SHIFT 11 +#define K1C_SFR_SPS_PL0_MME_WIDTH 1 +#define K1C_SFR_SPS_PL0_MME_WFXL_MASK _ULL(0x800) +#define K1C_SFR_SPS_PL0_MME_WFXL_CLEAR _ULL(0x800) +#define K1C_SFR_SPS_PL0_MME_WFXL_SET _ULL(0x80000000000) + +#define K1C_SFR_SPS_PL0_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define K1C_SFR_SPS_PL0_IL_SHIFT 12 +#define K1C_SFR_SPS_PL0_IL_WIDTH 2 +#define K1C_SFR_SPS_PL0_IL_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_SPS_PL0_IL_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_SPS_PL0_IL_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_SPS_PL0_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define K1C_SFR_SPS_PL0_VS_SHIFT 14 +#define K1C_SFR_SPS_PL0_VS_WIDTH 2 +#define K1C_SFR_SPS_PL0_VS_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_SPS_PL0_VS_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_SPS_PL0_VS_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_SPS_PL0_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define K1C_SFR_SPS_PL0_V64_SHIFT 16 +#define K1C_SFR_SPS_PL0_V64_WIDTH 1 +#define K1C_SFR_SPS_PL0_V64_WFXL_MASK _ULL(0x10000) +#define K1C_SFR_SPS_PL0_V64_WFXL_CLEAR _ULL(0x10000) +#define K1C_SFR_SPS_PL0_V64_WFXL_SET _ULL(0x1000000000000) + +#define K1C_SFR_SPS_PL0_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define K1C_SFR_SPS_PL0_L2E_SHIFT 17 +#define K1C_SFR_SPS_PL0_L2E_WIDTH 1 +#define K1C_SFR_SPS_PL0_L2E_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_SPS_PL0_L2E_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_SPS_PL0_L2E_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_SPS_PL0_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define K1C_SFR_SPS_PL0_SME_SHIFT 18 +#define K1C_SFR_SPS_PL0_SME_WIDTH 1 +#define K1C_SFR_SPS_PL0_SME_WFXL_MASK _ULL(0x40000) +#define K1C_SFR_SPS_PL0_SME_WFXL_CLEAR _ULL(0x40000) +#define K1C_SFR_SPS_PL0_SME_WFXL_SET _ULL(0x4000000000000) + +#define K1C_SFR_SPS_PL0_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define K1C_SFR_SPS_PL0_SMR_SHIFT 19 +#define K1C_SFR_SPS_PL0_SMR_WIDTH 1 +#define K1C_SFR_SPS_PL0_SMR_WFXL_MASK _ULL(0x80000) +#define K1C_SFR_SPS_PL0_SMR_WFXL_CLEAR _ULL(0x80000) +#define K1C_SFR_SPS_PL0_SMR_WFXL_SET _ULL(0x8000000000000) + +#define K1C_SFR_SPS_PL0_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define K1C_SFR_SPS_PL0_PMJ_SHIFT 20 +#define K1C_SFR_SPS_PL0_PMJ_WIDTH 4 +#define K1C_SFR_SPS_PL0_PMJ_WFXL_MASK _ULL(0xf00000) +#define K1C_SFR_SPS_PL0_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define K1C_SFR_SPS_PL0_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define K1C_SFR_SPS_PL0_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define K1C_SFR_SPS_PL0_MMUP_SHIFT 24 +#define K1C_SFR_SPS_PL0_MMUP_WIDTH 1 +#define K1C_SFR_SPS_PL0_MMUP_WFXL_MASK _ULL(0x1000000) +#define K1C_SFR_SPS_PL0_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define K1C_SFR_SPS_PL0_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define K1C_SFR_SPS_PL1_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define K1C_SFR_SPS_PL1_PL_SHIFT 0 +#define K1C_SFR_SPS_PL1_PL_WIDTH 2 +#define K1C_SFR_SPS_PL1_PL_WFXL_MASK _ULL(0x3) +#define K1C_SFR_SPS_PL1_PL_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_SPS_PL1_PL_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_SPS_PL1_ET_MASK _ULL(0x4) /* Exception Taken */ +#define K1C_SFR_SPS_PL1_ET_SHIFT 2 +#define K1C_SFR_SPS_PL1_ET_WIDTH 1 +#define K1C_SFR_SPS_PL1_ET_WFXL_MASK _ULL(0x4) +#define K1C_SFR_SPS_PL1_ET_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_SPS_PL1_ET_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_SPS_PL1_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define K1C_SFR_SPS_PL1_HTD_SHIFT 3 +#define K1C_SFR_SPS_PL1_HTD_WIDTH 1 +#define K1C_SFR_SPS_PL1_HTD_WFXL_MASK _ULL(0x8) +#define K1C_SFR_SPS_PL1_HTD_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_SPS_PL1_HTD_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_SPS_PL1_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define K1C_SFR_SPS_PL1_IE_SHIFT 4 +#define K1C_SFR_SPS_PL1_IE_WIDTH 1 +#define K1C_SFR_SPS_PL1_IE_WFXL_MASK _ULL(0x10) +#define K1C_SFR_SPS_PL1_IE_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_SPS_PL1_IE_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_SPS_PL1_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define K1C_SFR_SPS_PL1_HLE_SHIFT 5 +#define K1C_SFR_SPS_PL1_HLE_WIDTH 1 +#define K1C_SFR_SPS_PL1_HLE_WFXL_MASK _ULL(0x20) +#define K1C_SFR_SPS_PL1_HLE_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_SPS_PL1_HLE_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_SPS_PL1_SRE_MASK _ULL(0x40) /* Software REserved */ +#define K1C_SFR_SPS_PL1_SRE_SHIFT 6 +#define K1C_SFR_SPS_PL1_SRE_WIDTH 1 +#define K1C_SFR_SPS_PL1_SRE_WFXL_MASK _ULL(0x40) +#define K1C_SFR_SPS_PL1_SRE_WFXL_CLEAR _ULL(0x40) +#define K1C_SFR_SPS_PL1_SRE_WFXL_SET _ULL(0x4000000000) + +#define K1C_SFR_SPS_PL1_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define K1C_SFR_SPS_PL1_DAUS_SHIFT 7 +#define K1C_SFR_SPS_PL1_DAUS_WIDTH 1 +#define K1C_SFR_SPS_PL1_DAUS_WFXL_MASK _ULL(0x80) +#define K1C_SFR_SPS_PL1_DAUS_WFXL_CLEAR _ULL(0x80) +#define K1C_SFR_SPS_PL1_DAUS_WFXL_SET _ULL(0x8000000000) + +#define K1C_SFR_SPS_PL1_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define K1C_SFR_SPS_PL1_ICE_SHIFT 8 +#define K1C_SFR_SPS_PL1_ICE_WIDTH 1 +#define K1C_SFR_SPS_PL1_ICE_WFXL_MASK _ULL(0x100) +#define K1C_SFR_SPS_PL1_ICE_WFXL_CLEAR _ULL(0x100) +#define K1C_SFR_SPS_PL1_ICE_WFXL_SET _ULL(0x10000000000) + +#define K1C_SFR_SPS_PL1_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define K1C_SFR_SPS_PL1_USE_SHIFT 9 +#define K1C_SFR_SPS_PL1_USE_WIDTH 1 +#define K1C_SFR_SPS_PL1_USE_WFXL_MASK _ULL(0x200) +#define K1C_SFR_SPS_PL1_USE_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_SPS_PL1_USE_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_SPS_PL1_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define K1C_SFR_SPS_PL1_DCE_SHIFT 10 +#define K1C_SFR_SPS_PL1_DCE_WIDTH 1 +#define K1C_SFR_SPS_PL1_DCE_WFXL_MASK _ULL(0x400) +#define K1C_SFR_SPS_PL1_DCE_WFXL_CLEAR _ULL(0x400) +#define K1C_SFR_SPS_PL1_DCE_WFXL_SET _ULL(0x40000000000) + +#define K1C_SFR_SPS_PL1_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define K1C_SFR_SPS_PL1_MME_SHIFT 11 +#define K1C_SFR_SPS_PL1_MME_WIDTH 1 +#define K1C_SFR_SPS_PL1_MME_WFXL_MASK _ULL(0x800) +#define K1C_SFR_SPS_PL1_MME_WFXL_CLEAR _ULL(0x800) +#define K1C_SFR_SPS_PL1_MME_WFXL_SET _ULL(0x80000000000) + +#define K1C_SFR_SPS_PL1_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define K1C_SFR_SPS_PL1_IL_SHIFT 12 +#define K1C_SFR_SPS_PL1_IL_WIDTH 2 +#define K1C_SFR_SPS_PL1_IL_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_SPS_PL1_IL_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_SPS_PL1_IL_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_SPS_PL1_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define K1C_SFR_SPS_PL1_VS_SHIFT 14 +#define K1C_SFR_SPS_PL1_VS_WIDTH 2 +#define K1C_SFR_SPS_PL1_VS_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_SPS_PL1_VS_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_SPS_PL1_VS_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_SPS_PL1_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define K1C_SFR_SPS_PL1_V64_SHIFT 16 +#define K1C_SFR_SPS_PL1_V64_WIDTH 1 +#define K1C_SFR_SPS_PL1_V64_WFXL_MASK _ULL(0x10000) +#define K1C_SFR_SPS_PL1_V64_WFXL_CLEAR _ULL(0x10000) +#define K1C_SFR_SPS_PL1_V64_WFXL_SET _ULL(0x1000000000000) + +#define K1C_SFR_SPS_PL1_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define K1C_SFR_SPS_PL1_L2E_SHIFT 17 +#define K1C_SFR_SPS_PL1_L2E_WIDTH 1 +#define K1C_SFR_SPS_PL1_L2E_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_SPS_PL1_L2E_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_SPS_PL1_L2E_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_SPS_PL1_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define K1C_SFR_SPS_PL1_SME_SHIFT 18 +#define K1C_SFR_SPS_PL1_SME_WIDTH 1 +#define K1C_SFR_SPS_PL1_SME_WFXL_MASK _ULL(0x40000) +#define K1C_SFR_SPS_PL1_SME_WFXL_CLEAR _ULL(0x40000) +#define K1C_SFR_SPS_PL1_SME_WFXL_SET _ULL(0x4000000000000) + +#define K1C_SFR_SPS_PL1_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define K1C_SFR_SPS_PL1_SMR_SHIFT 19 +#define K1C_SFR_SPS_PL1_SMR_WIDTH 1 +#define K1C_SFR_SPS_PL1_SMR_WFXL_MASK _ULL(0x80000) +#define K1C_SFR_SPS_PL1_SMR_WFXL_CLEAR _ULL(0x80000) +#define K1C_SFR_SPS_PL1_SMR_WFXL_SET _ULL(0x8000000000000) + +#define K1C_SFR_SPS_PL1_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define K1C_SFR_SPS_PL1_PMJ_SHIFT 20 +#define K1C_SFR_SPS_PL1_PMJ_WIDTH 4 +#define K1C_SFR_SPS_PL1_PMJ_WFXL_MASK _ULL(0xf00000) +#define K1C_SFR_SPS_PL1_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define K1C_SFR_SPS_PL1_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define K1C_SFR_SPS_PL1_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define K1C_SFR_SPS_PL1_MMUP_SHIFT 24 +#define K1C_SFR_SPS_PL1_MMUP_WIDTH 1 +#define K1C_SFR_SPS_PL1_MMUP_WFXL_MASK _ULL(0x1000000) +#define K1C_SFR_SPS_PL1_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define K1C_SFR_SPS_PL1_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define K1C_SFR_SPS_PL2_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define K1C_SFR_SPS_PL2_PL_SHIFT 0 +#define K1C_SFR_SPS_PL2_PL_WIDTH 2 +#define K1C_SFR_SPS_PL2_PL_WFXL_MASK _ULL(0x3) +#define K1C_SFR_SPS_PL2_PL_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_SPS_PL2_PL_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_SPS_PL2_ET_MASK _ULL(0x4) /* Exception Taken */ +#define K1C_SFR_SPS_PL2_ET_SHIFT 2 +#define K1C_SFR_SPS_PL2_ET_WIDTH 1 +#define K1C_SFR_SPS_PL2_ET_WFXL_MASK _ULL(0x4) +#define K1C_SFR_SPS_PL2_ET_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_SPS_PL2_ET_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_SPS_PL2_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define K1C_SFR_SPS_PL2_HTD_SHIFT 3 +#define K1C_SFR_SPS_PL2_HTD_WIDTH 1 +#define K1C_SFR_SPS_PL2_HTD_WFXL_MASK _ULL(0x8) +#define K1C_SFR_SPS_PL2_HTD_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_SPS_PL2_HTD_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_SPS_PL2_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define K1C_SFR_SPS_PL2_IE_SHIFT 4 +#define K1C_SFR_SPS_PL2_IE_WIDTH 1 +#define K1C_SFR_SPS_PL2_IE_WFXL_MASK _ULL(0x10) +#define K1C_SFR_SPS_PL2_IE_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_SPS_PL2_IE_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_SPS_PL2_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define K1C_SFR_SPS_PL2_HLE_SHIFT 5 +#define K1C_SFR_SPS_PL2_HLE_WIDTH 1 +#define K1C_SFR_SPS_PL2_HLE_WFXL_MASK _ULL(0x20) +#define K1C_SFR_SPS_PL2_HLE_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_SPS_PL2_HLE_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_SPS_PL2_SRE_MASK _ULL(0x40) /* Software REserved */ +#define K1C_SFR_SPS_PL2_SRE_SHIFT 6 +#define K1C_SFR_SPS_PL2_SRE_WIDTH 1 +#define K1C_SFR_SPS_PL2_SRE_WFXL_MASK _ULL(0x40) +#define K1C_SFR_SPS_PL2_SRE_WFXL_CLEAR _ULL(0x40) +#define K1C_SFR_SPS_PL2_SRE_WFXL_SET _ULL(0x4000000000) + +#define K1C_SFR_SPS_PL2_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define K1C_SFR_SPS_PL2_DAUS_SHIFT 7 +#define K1C_SFR_SPS_PL2_DAUS_WIDTH 1 +#define K1C_SFR_SPS_PL2_DAUS_WFXL_MASK _ULL(0x80) +#define K1C_SFR_SPS_PL2_DAUS_WFXL_CLEAR _ULL(0x80) +#define K1C_SFR_SPS_PL2_DAUS_WFXL_SET _ULL(0x8000000000) + +#define K1C_SFR_SPS_PL2_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define K1C_SFR_SPS_PL2_ICE_SHIFT 8 +#define K1C_SFR_SPS_PL2_ICE_WIDTH 1 +#define K1C_SFR_SPS_PL2_ICE_WFXL_MASK _ULL(0x100) +#define K1C_SFR_SPS_PL2_ICE_WFXL_CLEAR _ULL(0x100) +#define K1C_SFR_SPS_PL2_ICE_WFXL_SET _ULL(0x10000000000) + +#define K1C_SFR_SPS_PL2_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define K1C_SFR_SPS_PL2_USE_SHIFT 9 +#define K1C_SFR_SPS_PL2_USE_WIDTH 1 +#define K1C_SFR_SPS_PL2_USE_WFXL_MASK _ULL(0x200) +#define K1C_SFR_SPS_PL2_USE_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_SPS_PL2_USE_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_SPS_PL2_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define K1C_SFR_SPS_PL2_DCE_SHIFT 10 +#define K1C_SFR_SPS_PL2_DCE_WIDTH 1 +#define K1C_SFR_SPS_PL2_DCE_WFXL_MASK _ULL(0x400) +#define K1C_SFR_SPS_PL2_DCE_WFXL_CLEAR _ULL(0x400) +#define K1C_SFR_SPS_PL2_DCE_WFXL_SET _ULL(0x40000000000) + +#define K1C_SFR_SPS_PL2_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define K1C_SFR_SPS_PL2_MME_SHIFT 11 +#define K1C_SFR_SPS_PL2_MME_WIDTH 1 +#define K1C_SFR_SPS_PL2_MME_WFXL_MASK _ULL(0x800) +#define K1C_SFR_SPS_PL2_MME_WFXL_CLEAR _ULL(0x800) +#define K1C_SFR_SPS_PL2_MME_WFXL_SET _ULL(0x80000000000) + +#define K1C_SFR_SPS_PL2_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define K1C_SFR_SPS_PL2_IL_SHIFT 12 +#define K1C_SFR_SPS_PL2_IL_WIDTH 2 +#define K1C_SFR_SPS_PL2_IL_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_SPS_PL2_IL_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_SPS_PL2_IL_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_SPS_PL2_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define K1C_SFR_SPS_PL2_VS_SHIFT 14 +#define K1C_SFR_SPS_PL2_VS_WIDTH 2 +#define K1C_SFR_SPS_PL2_VS_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_SPS_PL2_VS_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_SPS_PL2_VS_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_SPS_PL2_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define K1C_SFR_SPS_PL2_V64_SHIFT 16 +#define K1C_SFR_SPS_PL2_V64_WIDTH 1 +#define K1C_SFR_SPS_PL2_V64_WFXL_MASK _ULL(0x10000) +#define K1C_SFR_SPS_PL2_V64_WFXL_CLEAR _ULL(0x10000) +#define K1C_SFR_SPS_PL2_V64_WFXL_SET _ULL(0x1000000000000) + +#define K1C_SFR_SPS_PL2_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define K1C_SFR_SPS_PL2_L2E_SHIFT 17 +#define K1C_SFR_SPS_PL2_L2E_WIDTH 1 +#define K1C_SFR_SPS_PL2_L2E_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_SPS_PL2_L2E_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_SPS_PL2_L2E_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_SPS_PL2_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define K1C_SFR_SPS_PL2_SME_SHIFT 18 +#define K1C_SFR_SPS_PL2_SME_WIDTH 1 +#define K1C_SFR_SPS_PL2_SME_WFXL_MASK _ULL(0x40000) +#define K1C_SFR_SPS_PL2_SME_WFXL_CLEAR _ULL(0x40000) +#define K1C_SFR_SPS_PL2_SME_WFXL_SET _ULL(0x4000000000000) + +#define K1C_SFR_SPS_PL2_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define K1C_SFR_SPS_PL2_SMR_SHIFT 19 +#define K1C_SFR_SPS_PL2_SMR_WIDTH 1 +#define K1C_SFR_SPS_PL2_SMR_WFXL_MASK _ULL(0x80000) +#define K1C_SFR_SPS_PL2_SMR_WFXL_CLEAR _ULL(0x80000) +#define K1C_SFR_SPS_PL2_SMR_WFXL_SET _ULL(0x8000000000000) + +#define K1C_SFR_SPS_PL2_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define K1C_SFR_SPS_PL2_PMJ_SHIFT 20 +#define K1C_SFR_SPS_PL2_PMJ_WIDTH 4 +#define K1C_SFR_SPS_PL2_PMJ_WFXL_MASK _ULL(0xf00000) +#define K1C_SFR_SPS_PL2_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define K1C_SFR_SPS_PL2_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define K1C_SFR_SPS_PL2_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define K1C_SFR_SPS_PL2_MMUP_SHIFT 24 +#define K1C_SFR_SPS_PL2_MMUP_WIDTH 1 +#define K1C_SFR_SPS_PL2_MMUP_WFXL_MASK _ULL(0x1000000) +#define K1C_SFR_SPS_PL2_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define K1C_SFR_SPS_PL2_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define K1C_SFR_SPS_PL3_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define K1C_SFR_SPS_PL3_PL_SHIFT 0 +#define K1C_SFR_SPS_PL3_PL_WIDTH 2 +#define K1C_SFR_SPS_PL3_PL_WFXL_MASK _ULL(0x3) +#define K1C_SFR_SPS_PL3_PL_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_SPS_PL3_PL_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_SPS_PL3_ET_MASK _ULL(0x4) /* Exception Taken */ +#define K1C_SFR_SPS_PL3_ET_SHIFT 2 +#define K1C_SFR_SPS_PL3_ET_WIDTH 1 +#define K1C_SFR_SPS_PL3_ET_WFXL_MASK _ULL(0x4) +#define K1C_SFR_SPS_PL3_ET_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_SPS_PL3_ET_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_SPS_PL3_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define K1C_SFR_SPS_PL3_HTD_SHIFT 3 +#define K1C_SFR_SPS_PL3_HTD_WIDTH 1 +#define K1C_SFR_SPS_PL3_HTD_WFXL_MASK _ULL(0x8) +#define K1C_SFR_SPS_PL3_HTD_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_SPS_PL3_HTD_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_SPS_PL3_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define K1C_SFR_SPS_PL3_IE_SHIFT 4 +#define K1C_SFR_SPS_PL3_IE_WIDTH 1 +#define K1C_SFR_SPS_PL3_IE_WFXL_MASK _ULL(0x10) +#define K1C_SFR_SPS_PL3_IE_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_SPS_PL3_IE_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_SPS_PL3_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define K1C_SFR_SPS_PL3_HLE_SHIFT 5 +#define K1C_SFR_SPS_PL3_HLE_WIDTH 1 +#define K1C_SFR_SPS_PL3_HLE_WFXL_MASK _ULL(0x20) +#define K1C_SFR_SPS_PL3_HLE_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_SPS_PL3_HLE_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_SPS_PL3_SRE_MASK _ULL(0x40) /* Software REserved */ +#define K1C_SFR_SPS_PL3_SRE_SHIFT 6 +#define K1C_SFR_SPS_PL3_SRE_WIDTH 1 +#define K1C_SFR_SPS_PL3_SRE_WFXL_MASK _ULL(0x40) +#define K1C_SFR_SPS_PL3_SRE_WFXL_CLEAR _ULL(0x40) +#define K1C_SFR_SPS_PL3_SRE_WFXL_SET _ULL(0x4000000000) + +#define K1C_SFR_SPS_PL3_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define K1C_SFR_SPS_PL3_DAUS_SHIFT 7 +#define K1C_SFR_SPS_PL3_DAUS_WIDTH 1 +#define K1C_SFR_SPS_PL3_DAUS_WFXL_MASK _ULL(0x80) +#define K1C_SFR_SPS_PL3_DAUS_WFXL_CLEAR _ULL(0x80) +#define K1C_SFR_SPS_PL3_DAUS_WFXL_SET _ULL(0x8000000000) + +#define K1C_SFR_SPS_PL3_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define K1C_SFR_SPS_PL3_ICE_SHIFT 8 +#define K1C_SFR_SPS_PL3_ICE_WIDTH 1 +#define K1C_SFR_SPS_PL3_ICE_WFXL_MASK _ULL(0x100) +#define K1C_SFR_SPS_PL3_ICE_WFXL_CLEAR _ULL(0x100) +#define K1C_SFR_SPS_PL3_ICE_WFXL_SET _ULL(0x10000000000) + +#define K1C_SFR_SPS_PL3_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define K1C_SFR_SPS_PL3_USE_SHIFT 9 +#define K1C_SFR_SPS_PL3_USE_WIDTH 1 +#define K1C_SFR_SPS_PL3_USE_WFXL_MASK _ULL(0x200) +#define K1C_SFR_SPS_PL3_USE_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_SPS_PL3_USE_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_SPS_PL3_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define K1C_SFR_SPS_PL3_DCE_SHIFT 10 +#define K1C_SFR_SPS_PL3_DCE_WIDTH 1 +#define K1C_SFR_SPS_PL3_DCE_WFXL_MASK _ULL(0x400) +#define K1C_SFR_SPS_PL3_DCE_WFXL_CLEAR _ULL(0x400) +#define K1C_SFR_SPS_PL3_DCE_WFXL_SET _ULL(0x40000000000) + +#define K1C_SFR_SPS_PL3_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define K1C_SFR_SPS_PL3_MME_SHIFT 11 +#define K1C_SFR_SPS_PL3_MME_WIDTH 1 +#define K1C_SFR_SPS_PL3_MME_WFXL_MASK _ULL(0x800) +#define K1C_SFR_SPS_PL3_MME_WFXL_CLEAR _ULL(0x800) +#define K1C_SFR_SPS_PL3_MME_WFXL_SET _ULL(0x80000000000) + +#define K1C_SFR_SPS_PL3_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define K1C_SFR_SPS_PL3_IL_SHIFT 12 +#define K1C_SFR_SPS_PL3_IL_WIDTH 2 +#define K1C_SFR_SPS_PL3_IL_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_SPS_PL3_IL_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_SPS_PL3_IL_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_SPS_PL3_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define K1C_SFR_SPS_PL3_VS_SHIFT 14 +#define K1C_SFR_SPS_PL3_VS_WIDTH 2 +#define K1C_SFR_SPS_PL3_VS_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_SPS_PL3_VS_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_SPS_PL3_VS_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_SPS_PL3_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define K1C_SFR_SPS_PL3_V64_SHIFT 16 +#define K1C_SFR_SPS_PL3_V64_WIDTH 1 +#define K1C_SFR_SPS_PL3_V64_WFXL_MASK _ULL(0x10000) +#define K1C_SFR_SPS_PL3_V64_WFXL_CLEAR _ULL(0x10000) +#define K1C_SFR_SPS_PL3_V64_WFXL_SET _ULL(0x1000000000000) + +#define K1C_SFR_SPS_PL3_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define K1C_SFR_SPS_PL3_L2E_SHIFT 17 +#define K1C_SFR_SPS_PL3_L2E_WIDTH 1 +#define K1C_SFR_SPS_PL3_L2E_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_SPS_PL3_L2E_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_SPS_PL3_L2E_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_SPS_PL3_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define K1C_SFR_SPS_PL3_SME_SHIFT 18 +#define K1C_SFR_SPS_PL3_SME_WIDTH 1 +#define K1C_SFR_SPS_PL3_SME_WFXL_MASK _ULL(0x40000) +#define K1C_SFR_SPS_PL3_SME_WFXL_CLEAR _ULL(0x40000) +#define K1C_SFR_SPS_PL3_SME_WFXL_SET _ULL(0x4000000000000) + +#define K1C_SFR_SPS_PL3_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define K1C_SFR_SPS_PL3_SMR_SHIFT 19 +#define K1C_SFR_SPS_PL3_SMR_WIDTH 1 +#define K1C_SFR_SPS_PL3_SMR_WFXL_MASK _ULL(0x80000) +#define K1C_SFR_SPS_PL3_SMR_WFXL_CLEAR _ULL(0x80000) +#define K1C_SFR_SPS_PL3_SMR_WFXL_SET _ULL(0x8000000000000) + +#define K1C_SFR_SPS_PL3_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define K1C_SFR_SPS_PL3_PMJ_SHIFT 20 +#define K1C_SFR_SPS_PL3_PMJ_WIDTH 4 +#define K1C_SFR_SPS_PL3_PMJ_WFXL_MASK _ULL(0xf00000) +#define K1C_SFR_SPS_PL3_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define K1C_SFR_SPS_PL3_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define K1C_SFR_SPS_PL3_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define K1C_SFR_SPS_PL3_MMUP_SHIFT 24 +#define K1C_SFR_SPS_PL3_MMUP_WIDTH 1 +#define K1C_SFR_SPS_PL3_MMUP_WFXL_MASK _ULL(0x1000000) +#define K1C_SFR_SPS_PL3_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define K1C_SFR_SPS_PL3_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define K1C_SFR_PSO_PL0_MASK _ULL(0x3) /* Current Privilege Level bit 0 owner */ +#define K1C_SFR_PSO_PL0_SHIFT 0 +#define K1C_SFR_PSO_PL0_WIDTH 2 +#define K1C_SFR_PSO_PL0_WFXL_MASK _ULL(0x3) +#define K1C_SFR_PSO_PL0_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_PSO_PL0_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_PSO_PL1_MASK _ULL(0xc) /* Current Privilege Level bit 1 owner */ +#define K1C_SFR_PSO_PL1_SHIFT 2 +#define K1C_SFR_PSO_PL1_WIDTH 2 +#define K1C_SFR_PSO_PL1_WFXL_MASK _ULL(0xc) +#define K1C_SFR_PSO_PL1_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_PSO_PL1_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_PSO_ET_MASK _ULL(0x30) /* Exception Taken owner */ +#define K1C_SFR_PSO_ET_SHIFT 4 +#define K1C_SFR_PSO_ET_WIDTH 2 +#define K1C_SFR_PSO_ET_WFXL_MASK _ULL(0x30) +#define K1C_SFR_PSO_ET_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_PSO_ET_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_PSO_HTD_MASK _ULL(0xc0) /* Hardware Trap Disable owner */ +#define K1C_SFR_PSO_HTD_SHIFT 6 +#define K1C_SFR_PSO_HTD_WIDTH 2 +#define K1C_SFR_PSO_HTD_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_PSO_HTD_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_PSO_HTD_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_PSO_IE_MASK _ULL(0x300) /* Interrupt Enable owner */ +#define K1C_SFR_PSO_IE_SHIFT 8 +#define K1C_SFR_PSO_IE_WIDTH 2 +#define K1C_SFR_PSO_IE_WFXL_MASK _ULL(0x300) +#define K1C_SFR_PSO_IE_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_PSO_IE_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_PSO_HLE_MASK _ULL(0xc00) /* Hardware Loop Enable owner */ +#define K1C_SFR_PSO_HLE_SHIFT 10 +#define K1C_SFR_PSO_HLE_WIDTH 2 +#define K1C_SFR_PSO_HLE_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_PSO_HLE_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_PSO_HLE_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_PSO_SRE_MASK _ULL(0x3000) /* Software REserved owner */ +#define K1C_SFR_PSO_SRE_SHIFT 12 +#define K1C_SFR_PSO_SRE_WIDTH 2 +#define K1C_SFR_PSO_SRE_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_PSO_SRE_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_PSO_SRE_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_PSO_DAUS_MASK _ULL(0xc000) /* Data Accesses Use SPS settings owner */ +#define K1C_SFR_PSO_DAUS_SHIFT 14 +#define K1C_SFR_PSO_DAUS_WIDTH 2 +#define K1C_SFR_PSO_DAUS_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_PSO_DAUS_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_PSO_DAUS_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_PSO_ICE_MASK _ULL(0x30000) /* Instruction Cache Enable owner */ +#define K1C_SFR_PSO_ICE_SHIFT 16 +#define K1C_SFR_PSO_ICE_WIDTH 2 +#define K1C_SFR_PSO_ICE_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_PSO_ICE_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_PSO_ICE_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_PSO_USE_MASK _ULL(0xc0000) /* Uncached Streaming Enable owner */ +#define K1C_SFR_PSO_USE_SHIFT 18 +#define K1C_SFR_PSO_USE_WIDTH 2 +#define K1C_SFR_PSO_USE_WFXL_MASK _ULL(0xc0000) +#define K1C_SFR_PSO_USE_WFXL_CLEAR _ULL(0xc0000) +#define K1C_SFR_PSO_USE_WFXL_SET _ULL(0xc000000000000) + +#define K1C_SFR_PSO_DCE_MASK _ULL(0x300000) /* Data Cache Enable owner */ +#define K1C_SFR_PSO_DCE_SHIFT 20 +#define K1C_SFR_PSO_DCE_WIDTH 2 +#define K1C_SFR_PSO_DCE_WFXL_MASK _ULL(0x300000) +#define K1C_SFR_PSO_DCE_WFXL_CLEAR _ULL(0x300000) +#define K1C_SFR_PSO_DCE_WFXL_SET _ULL(0x30000000000000) + +#define K1C_SFR_PSO_MME_MASK _ULL(0xc00000) /* Memory Management Enable owner */ +#define K1C_SFR_PSO_MME_SHIFT 22 +#define K1C_SFR_PSO_MME_WIDTH 2 +#define K1C_SFR_PSO_MME_WFXL_MASK _ULL(0xc00000) +#define K1C_SFR_PSO_MME_WFXL_CLEAR _ULL(0xc00000) +#define K1C_SFR_PSO_MME_WFXL_SET _ULL(0xc0000000000000) + +#define K1C_SFR_PSO_IL0_MASK _ULL(0x3000000) /* Interrupt Level bit 0 owner */ +#define K1C_SFR_PSO_IL0_SHIFT 24 +#define K1C_SFR_PSO_IL0_WIDTH 2 +#define K1C_SFR_PSO_IL0_WFXL_MASK _ULL(0x3000000) +#define K1C_SFR_PSO_IL0_WFXL_CLEAR _ULL(0x3000000) +#define K1C_SFR_PSO_IL0_WFXL_SET _ULL(0x300000000000000) + +#define K1C_SFR_PSO_IL1_MASK _ULL(0xc000000) /* Interrupt Level bit 1 owner */ +#define K1C_SFR_PSO_IL1_SHIFT 26 +#define K1C_SFR_PSO_IL1_WIDTH 2 +#define K1C_SFR_PSO_IL1_WFXL_MASK _ULL(0xc000000) +#define K1C_SFR_PSO_IL1_WFXL_CLEAR _ULL(0xc000000) +#define K1C_SFR_PSO_IL1_WFXL_SET _ULL(0xc00000000000000) + +#define K1C_SFR_PSO_VS0_MASK _ULL(0x30000000) /* Virtual Space bit 0 owner */ +#define K1C_SFR_PSO_VS0_SHIFT 28 +#define K1C_SFR_PSO_VS0_WIDTH 2 +#define K1C_SFR_PSO_VS0_WFXL_MASK _ULL(0x30000000) +#define K1C_SFR_PSO_VS0_WFXL_CLEAR _ULL(0x30000000) +#define K1C_SFR_PSO_VS0_WFXL_SET _ULL(0x3000000000000000) + +#define K1C_SFR_PSO_VS1_MASK _ULL(0xc0000000) /* Virtual Space bit 1 owner */ +#define K1C_SFR_PSO_VS1_SHIFT 30 +#define K1C_SFR_PSO_VS1_WIDTH 2 +#define K1C_SFR_PSO_VS1_WFXL_MASK _ULL(0xc0000000) +#define K1C_SFR_PSO_VS1_WFXL_CLEAR _ULL(0xc0000000) +#define K1C_SFR_PSO_VS1_WFXL_SET _ULL(0xc000000000000000) + +#define K1C_SFR_PSO_V64_MASK _ULL(0x300000000) /* Virtual 64 bits mode owner */ +#define K1C_SFR_PSO_V64_SHIFT 32 +#define K1C_SFR_PSO_V64_WIDTH 2 +#define K1C_SFR_PSO_V64_WFXM_MASK _ULL(0x300000000) +#define K1C_SFR_PSO_V64_WFXM_CLEAR _ULL(0x3) +#define K1C_SFR_PSO_V64_WFXM_SET _ULL(0x300000000) + +#define K1C_SFR_PSO_L2E_MASK _ULL(0xc00000000) /* L2 cache Enable owner */ +#define K1C_SFR_PSO_L2E_SHIFT 34 +#define K1C_SFR_PSO_L2E_WIDTH 2 +#define K1C_SFR_PSO_L2E_WFXM_MASK _ULL(0xc00000000) +#define K1C_SFR_PSO_L2E_WFXM_CLEAR _ULL(0xc) +#define K1C_SFR_PSO_L2E_WFXM_SET _ULL(0xc00000000) + +#define K1C_SFR_PSO_SME_MASK _ULL(0x3000000000) /* Step Mode Enabled owner */ +#define K1C_SFR_PSO_SME_SHIFT 36 +#define K1C_SFR_PSO_SME_WIDTH 2 +#define K1C_SFR_PSO_SME_WFXM_MASK _ULL(0x3000000000) +#define K1C_SFR_PSO_SME_WFXM_CLEAR _ULL(0x30) +#define K1C_SFR_PSO_SME_WFXM_SET _ULL(0x3000000000) + +#define K1C_SFR_PSO_SMR_MASK _ULL(0xc000000000) /* Step Mode Ready owner */ +#define K1C_SFR_PSO_SMR_SHIFT 38 +#define K1C_SFR_PSO_SMR_WIDTH 2 +#define K1C_SFR_PSO_SMR_WFXM_MASK _ULL(0xc000000000) +#define K1C_SFR_PSO_SMR_WFXM_CLEAR _ULL(0xc0) +#define K1C_SFR_PSO_SMR_WFXM_SET _ULL(0xc000000000) + +#define K1C_SFR_PSO_PMJ0_MASK _ULL(0x30000000000) /* Page Mask in JTLB bit 0 owner */ +#define K1C_SFR_PSO_PMJ0_SHIFT 40 +#define K1C_SFR_PSO_PMJ0_WIDTH 2 +#define K1C_SFR_PSO_PMJ0_WFXM_MASK _ULL(0x30000000000) +#define K1C_SFR_PSO_PMJ0_WFXM_CLEAR _ULL(0x300) +#define K1C_SFR_PSO_PMJ0_WFXM_SET _ULL(0x30000000000) + +#define K1C_SFR_PSO_PMJ1_MASK _ULL(0xc0000000000) /* Page Mask in JTLB bit 1 owner */ +#define K1C_SFR_PSO_PMJ1_SHIFT 42 +#define K1C_SFR_PSO_PMJ1_WIDTH 2 +#define K1C_SFR_PSO_PMJ1_WFXM_MASK _ULL(0xc0000000000) +#define K1C_SFR_PSO_PMJ1_WFXM_CLEAR _ULL(0xc00) +#define K1C_SFR_PSO_PMJ1_WFXM_SET _ULL(0xc0000000000) + +#define K1C_SFR_PSO_PMJ2_MASK _ULL(0x300000000000) /* Page Mask in JTLB bit 2 owner */ +#define K1C_SFR_PSO_PMJ2_SHIFT 44 +#define K1C_SFR_PSO_PMJ2_WIDTH 2 +#define K1C_SFR_PSO_PMJ2_WFXM_MASK _ULL(0x300000000000) +#define K1C_SFR_PSO_PMJ2_WFXM_CLEAR _ULL(0x3000) +#define K1C_SFR_PSO_PMJ2_WFXM_SET _ULL(0x300000000000) + +#define K1C_SFR_PSO_PMJ3_MASK _ULL(0xc00000000000) /* Page Mask in JTLB bit 3 owner */ +#define K1C_SFR_PSO_PMJ3_SHIFT 46 +#define K1C_SFR_PSO_PMJ3_WIDTH 2 +#define K1C_SFR_PSO_PMJ3_WFXM_MASK _ULL(0xc00000000000) +#define K1C_SFR_PSO_PMJ3_WFXM_CLEAR _ULL(0xc000) +#define K1C_SFR_PSO_PMJ3_WFXM_SET _ULL(0xc00000000000) + +#define K1C_SFR_PSO_MMUP_MASK _ULL(0x3000000000000) /* Privileged on MMU owner. */ +#define K1C_SFR_PSO_MMUP_SHIFT 48 +#define K1C_SFR_PSO_MMUP_WIDTH 2 +#define K1C_SFR_PSO_MMUP_WFXM_MASK _ULL(0x3000000000000) +#define K1C_SFR_PSO_MMUP_WFXM_CLEAR _ULL(0x30000) +#define K1C_SFR_PSO_MMUP_WFXM_SET _ULL(0x3000000000000) + +#define K1C_SFR_PSOW_PL0_MASK _ULL(0x3) /* Current Privilege Level bit 0 owner */ +#define K1C_SFR_PSOW_PL0_SHIFT 0 +#define K1C_SFR_PSOW_PL0_WIDTH 2 +#define K1C_SFR_PSOW_PL0_WFXL_MASK _ULL(0x3) +#define K1C_SFR_PSOW_PL0_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_PSOW_PL0_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_PSOW_PL1_MASK _ULL(0xc) /* Current Privilege Level bit 1 owner */ +#define K1C_SFR_PSOW_PL1_SHIFT 2 +#define K1C_SFR_PSOW_PL1_WIDTH 2 +#define K1C_SFR_PSOW_PL1_WFXL_MASK _ULL(0xc) +#define K1C_SFR_PSOW_PL1_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_PSOW_PL1_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_PSOW_ET_MASK _ULL(0x30) /* Exception Taken owner */ +#define K1C_SFR_PSOW_ET_SHIFT 4 +#define K1C_SFR_PSOW_ET_WIDTH 2 +#define K1C_SFR_PSOW_ET_WFXL_MASK _ULL(0x30) +#define K1C_SFR_PSOW_ET_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_PSOW_ET_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_PSOW_HTD_MASK _ULL(0xc0) /* Hardware Trap Disable owner */ +#define K1C_SFR_PSOW_HTD_SHIFT 6 +#define K1C_SFR_PSOW_HTD_WIDTH 2 +#define K1C_SFR_PSOW_HTD_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_PSOW_HTD_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_PSOW_HTD_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_PSOW_IE_MASK _ULL(0x300) /* Interrupt Enable owner */ +#define K1C_SFR_PSOW_IE_SHIFT 8 +#define K1C_SFR_PSOW_IE_WIDTH 2 +#define K1C_SFR_PSOW_IE_WFXL_MASK _ULL(0x300) +#define K1C_SFR_PSOW_IE_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_PSOW_IE_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_PSOW_HLE_MASK _ULL(0xc00) /* Hardware Loop Enable owner */ +#define K1C_SFR_PSOW_HLE_SHIFT 10 +#define K1C_SFR_PSOW_HLE_WIDTH 2 +#define K1C_SFR_PSOW_HLE_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_PSOW_HLE_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_PSOW_HLE_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_PSOW_SRE_MASK _ULL(0x3000) /* Software REserved owner */ +#define K1C_SFR_PSOW_SRE_SHIFT 12 +#define K1C_SFR_PSOW_SRE_WIDTH 2 +#define K1C_SFR_PSOW_SRE_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_PSOW_SRE_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_PSOW_SRE_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_PSOW_DAUS_MASK _ULL(0xc000) /* Data Accesses Use SPS settings owner */ +#define K1C_SFR_PSOW_DAUS_SHIFT 14 +#define K1C_SFR_PSOW_DAUS_WIDTH 2 +#define K1C_SFR_PSOW_DAUS_WFXL_MASK _ULL(0xc000) +#define K1C_SFR_PSOW_DAUS_WFXL_CLEAR _ULL(0xc000) +#define K1C_SFR_PSOW_DAUS_WFXL_SET _ULL(0xc00000000000) + +#define K1C_SFR_PSOW_ICE_MASK _ULL(0x30000) /* Instruction Cache Enable owner */ +#define K1C_SFR_PSOW_ICE_SHIFT 16 +#define K1C_SFR_PSOW_ICE_WIDTH 2 +#define K1C_SFR_PSOW_ICE_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_PSOW_ICE_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_PSOW_ICE_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_PSOW_USE_MASK _ULL(0xc0000) /* Uncached Streaming Enable owner */ +#define K1C_SFR_PSOW_USE_SHIFT 18 +#define K1C_SFR_PSOW_USE_WIDTH 2 +#define K1C_SFR_PSOW_USE_WFXL_MASK _ULL(0xc0000) +#define K1C_SFR_PSOW_USE_WFXL_CLEAR _ULL(0xc0000) +#define K1C_SFR_PSOW_USE_WFXL_SET _ULL(0xc000000000000) + +#define K1C_SFR_PSOW_DCE_MASK _ULL(0x300000) /* Data Cache Enable owner */ +#define K1C_SFR_PSOW_DCE_SHIFT 20 +#define K1C_SFR_PSOW_DCE_WIDTH 2 +#define K1C_SFR_PSOW_DCE_WFXL_MASK _ULL(0x300000) +#define K1C_SFR_PSOW_DCE_WFXL_CLEAR _ULL(0x300000) +#define K1C_SFR_PSOW_DCE_WFXL_SET _ULL(0x30000000000000) + +#define K1C_SFR_PSOW_MME_MASK _ULL(0xc00000) /* Memory Management Enable owner */ +#define K1C_SFR_PSOW_MME_SHIFT 22 +#define K1C_SFR_PSOW_MME_WIDTH 2 +#define K1C_SFR_PSOW_MME_WFXL_MASK _ULL(0xc00000) +#define K1C_SFR_PSOW_MME_WFXL_CLEAR _ULL(0xc00000) +#define K1C_SFR_PSOW_MME_WFXL_SET _ULL(0xc0000000000000) + +#define K1C_SFR_PSOW_IL0_MASK _ULL(0x3000000) /* Interrupt Level bit 0 owner */ +#define K1C_SFR_PSOW_IL0_SHIFT 24 +#define K1C_SFR_PSOW_IL0_WIDTH 2 +#define K1C_SFR_PSOW_IL0_WFXL_MASK _ULL(0x3000000) +#define K1C_SFR_PSOW_IL0_WFXL_CLEAR _ULL(0x3000000) +#define K1C_SFR_PSOW_IL0_WFXL_SET _ULL(0x300000000000000) + +#define K1C_SFR_PSOW_IL1_MASK _ULL(0xc000000) /* Interrupt Level bit 1 owner */ +#define K1C_SFR_PSOW_IL1_SHIFT 26 +#define K1C_SFR_PSOW_IL1_WIDTH 2 +#define K1C_SFR_PSOW_IL1_WFXL_MASK _ULL(0xc000000) +#define K1C_SFR_PSOW_IL1_WFXL_CLEAR _ULL(0xc000000) +#define K1C_SFR_PSOW_IL1_WFXL_SET _ULL(0xc00000000000000) + +#define K1C_SFR_PSOW_VS0_MASK _ULL(0x30000000) /* Virtual Space bit 0 owner */ +#define K1C_SFR_PSOW_VS0_SHIFT 28 +#define K1C_SFR_PSOW_VS0_WIDTH 2 +#define K1C_SFR_PSOW_VS0_WFXL_MASK _ULL(0x30000000) +#define K1C_SFR_PSOW_VS0_WFXL_CLEAR _ULL(0x30000000) +#define K1C_SFR_PSOW_VS0_WFXL_SET _ULL(0x3000000000000000) + +#define K1C_SFR_PSOW_VS1_MASK _ULL(0xc0000000) /* Virtual Space bit 1 owner */ +#define K1C_SFR_PSOW_VS1_SHIFT 30 +#define K1C_SFR_PSOW_VS1_WIDTH 2 +#define K1C_SFR_PSOW_VS1_WFXL_MASK _ULL(0xc0000000) +#define K1C_SFR_PSOW_VS1_WFXL_CLEAR _ULL(0xc0000000) +#define K1C_SFR_PSOW_VS1_WFXL_SET _ULL(0xc000000000000000) + +#define K1C_SFR_PSOW_V64_MASK _ULL(0x300000000) /* Virtual 64 bits mode owner */ +#define K1C_SFR_PSOW_V64_SHIFT 32 +#define K1C_SFR_PSOW_V64_WIDTH 2 +#define K1C_SFR_PSOW_V64_WFXM_MASK _ULL(0x300000000) +#define K1C_SFR_PSOW_V64_WFXM_CLEAR _ULL(0x3) +#define K1C_SFR_PSOW_V64_WFXM_SET _ULL(0x300000000) + +#define K1C_SFR_PSOW_L2E_MASK _ULL(0xc00000000) /* L2 cache Enable owner */ +#define K1C_SFR_PSOW_L2E_SHIFT 34 +#define K1C_SFR_PSOW_L2E_WIDTH 2 +#define K1C_SFR_PSOW_L2E_WFXM_MASK _ULL(0xc00000000) +#define K1C_SFR_PSOW_L2E_WFXM_CLEAR _ULL(0xc) +#define K1C_SFR_PSOW_L2E_WFXM_SET _ULL(0xc00000000) + +#define K1C_SFR_PSOW_SME_MASK _ULL(0x3000000000) /* Step Mode Enabled owner */ +#define K1C_SFR_PSOW_SME_SHIFT 36 +#define K1C_SFR_PSOW_SME_WIDTH 2 +#define K1C_SFR_PSOW_SME_WFXM_MASK _ULL(0x3000000000) +#define K1C_SFR_PSOW_SME_WFXM_CLEAR _ULL(0x30) +#define K1C_SFR_PSOW_SME_WFXM_SET _ULL(0x3000000000) + +#define K1C_SFR_PSOW_SMR_MASK _ULL(0xc000000000) /* Step Mode Ready owner */ +#define K1C_SFR_PSOW_SMR_SHIFT 38 +#define K1C_SFR_PSOW_SMR_WIDTH 2 +#define K1C_SFR_PSOW_SMR_WFXM_MASK _ULL(0xc000000000) +#define K1C_SFR_PSOW_SMR_WFXM_CLEAR _ULL(0xc0) +#define K1C_SFR_PSOW_SMR_WFXM_SET _ULL(0xc000000000) + +#define K1C_SFR_PSOW_PMJ0_MASK _ULL(0x30000000000) /* Page Mask in JTLB bit 0 owner */ +#define K1C_SFR_PSOW_PMJ0_SHIFT 40 +#define K1C_SFR_PSOW_PMJ0_WIDTH 2 +#define K1C_SFR_PSOW_PMJ0_WFXM_MASK _ULL(0x30000000000) +#define K1C_SFR_PSOW_PMJ0_WFXM_CLEAR _ULL(0x300) +#define K1C_SFR_PSOW_PMJ0_WFXM_SET _ULL(0x30000000000) + +#define K1C_SFR_PSOW_PMJ1_MASK _ULL(0xc0000000000) /* Page Mask in JTLB bit 1 owner */ +#define K1C_SFR_PSOW_PMJ1_SHIFT 42 +#define K1C_SFR_PSOW_PMJ1_WIDTH 2 +#define K1C_SFR_PSOW_PMJ1_WFXM_MASK _ULL(0xc0000000000) +#define K1C_SFR_PSOW_PMJ1_WFXM_CLEAR _ULL(0xc00) +#define K1C_SFR_PSOW_PMJ1_WFXM_SET _ULL(0xc0000000000) + +#define K1C_SFR_PSOW_PMJ2_MASK _ULL(0x300000000000) /* Page Mask in JTLB bit 2 owner */ +#define K1C_SFR_PSOW_PMJ2_SHIFT 44 +#define K1C_SFR_PSOW_PMJ2_WIDTH 2 +#define K1C_SFR_PSOW_PMJ2_WFXM_MASK _ULL(0x300000000000) +#define K1C_SFR_PSOW_PMJ2_WFXM_CLEAR _ULL(0x3000) +#define K1C_SFR_PSOW_PMJ2_WFXM_SET _ULL(0x300000000000) + +#define K1C_SFR_PSOW_PMJ3_MASK _ULL(0xc00000000000) /* Page Mask in JTLB bit 3 owner */ +#define K1C_SFR_PSOW_PMJ3_SHIFT 46 +#define K1C_SFR_PSOW_PMJ3_WIDTH 2 +#define K1C_SFR_PSOW_PMJ3_WFXM_MASK _ULL(0xc00000000000) +#define K1C_SFR_PSOW_PMJ3_WFXM_CLEAR _ULL(0xc000) +#define K1C_SFR_PSOW_PMJ3_WFXM_SET _ULL(0xc00000000000) + +#define K1C_SFR_PSOW_MMUP_MASK _ULL(0x3000000000000) /* Privileged on MMU owner. */ +#define K1C_SFR_PSOW_MMUP_SHIFT 48 +#define K1C_SFR_PSOW_MMUP_WIDTH 2 +#define K1C_SFR_PSOW_MMUP_WFXM_MASK _ULL(0x3000000000000) +#define K1C_SFR_PSOW_MMUP_WFXM_CLEAR _ULL(0x30000) +#define K1C_SFR_PSOW_MMUP_WFXM_SET _ULL(0x3000000000000) + +#define K1C_SFR_CS_IC_MASK _ULL(0x1) /* Integer Carry */ +#define K1C_SFR_CS_IC_SHIFT 0 +#define K1C_SFR_CS_IC_WIDTH 1 +#define K1C_SFR_CS_IC_WFXL_MASK _ULL(0x1) +#define K1C_SFR_CS_IC_WFXL_CLEAR _ULL(0x1) +#define K1C_SFR_CS_IC_WFXL_SET _ULL(0x100000000) + +#define K1C_SFR_CS_IO_MASK _ULL(0x2) /* IEEE 754 Invalid Operation */ +#define K1C_SFR_CS_IO_SHIFT 1 +#define K1C_SFR_CS_IO_WIDTH 1 +#define K1C_SFR_CS_IO_WFXL_MASK _ULL(0x2) +#define K1C_SFR_CS_IO_WFXL_CLEAR _ULL(0x2) +#define K1C_SFR_CS_IO_WFXL_SET _ULL(0x200000000) + +#define K1C_SFR_CS_DZ_MASK _ULL(0x4) /* IEEE 754 Divide by Zero */ +#define K1C_SFR_CS_DZ_SHIFT 2 +#define K1C_SFR_CS_DZ_WIDTH 1 +#define K1C_SFR_CS_DZ_WFXL_MASK _ULL(0x4) +#define K1C_SFR_CS_DZ_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_CS_DZ_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_CS_OV_MASK _ULL(0x8) /* IEEE 754 Overflow */ +#define K1C_SFR_CS_OV_SHIFT 3 +#define K1C_SFR_CS_OV_WIDTH 1 +#define K1C_SFR_CS_OV_WFXL_MASK _ULL(0x8) +#define K1C_SFR_CS_OV_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_CS_OV_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_CS_UN_MASK _ULL(0x10) /* IEEE 754 Underflow */ +#define K1C_SFR_CS_UN_SHIFT 4 +#define K1C_SFR_CS_UN_WIDTH 1 +#define K1C_SFR_CS_UN_WFXL_MASK _ULL(0x10) +#define K1C_SFR_CS_UN_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_CS_UN_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_CS_IN_MASK _ULL(0x20) /* IEEE 754 Inexact */ +#define K1C_SFR_CS_IN_SHIFT 5 +#define K1C_SFR_CS_IN_WIDTH 1 +#define K1C_SFR_CS_IN_WFXL_MASK _ULL(0x20) +#define K1C_SFR_CS_IN_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_CS_IN_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_CS_XIO_MASK _ULL(0x200) /* Extension IEEE 754 Invalid Operation */ +#define K1C_SFR_CS_XIO_SHIFT 9 +#define K1C_SFR_CS_XIO_WIDTH 1 +#define K1C_SFR_CS_XIO_WFXL_MASK _ULL(0x200) +#define K1C_SFR_CS_XIO_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_CS_XIO_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_CS_XDZ_MASK _ULL(0x400) /* Extension IEEE 754 Divide by Zero */ +#define K1C_SFR_CS_XDZ_SHIFT 10 +#define K1C_SFR_CS_XDZ_WIDTH 1 +#define K1C_SFR_CS_XDZ_WFXL_MASK _ULL(0x400) +#define K1C_SFR_CS_XDZ_WFXL_CLEAR _ULL(0x400) +#define K1C_SFR_CS_XDZ_WFXL_SET _ULL(0x40000000000) + +#define K1C_SFR_CS_XOV_MASK _ULL(0x800) /* Extension IEEE 754 Overflow */ +#define K1C_SFR_CS_XOV_SHIFT 11 +#define K1C_SFR_CS_XOV_WIDTH 1 +#define K1C_SFR_CS_XOV_WFXL_MASK _ULL(0x800) +#define K1C_SFR_CS_XOV_WFXL_CLEAR _ULL(0x800) +#define K1C_SFR_CS_XOV_WFXL_SET _ULL(0x80000000000) + +#define K1C_SFR_CS_XUN_MASK _ULL(0x1000) /* Extension IEEE 754 Underflow */ +#define K1C_SFR_CS_XUN_SHIFT 12 +#define K1C_SFR_CS_XUN_WIDTH 1 +#define K1C_SFR_CS_XUN_WFXL_MASK _ULL(0x1000) +#define K1C_SFR_CS_XUN_WFXL_CLEAR _ULL(0x1000) +#define K1C_SFR_CS_XUN_WFXL_SET _ULL(0x100000000000) + +#define K1C_SFR_CS_XIN_MASK _ULL(0x2000) /* Extension IEEE 754 Inexact */ +#define K1C_SFR_CS_XIN_SHIFT 13 +#define K1C_SFR_CS_XIN_WIDTH 1 +#define K1C_SFR_CS_XIN_WFXL_MASK _ULL(0x2000) +#define K1C_SFR_CS_XIN_WFXL_CLEAR _ULL(0x2000) +#define K1C_SFR_CS_XIN_WFXL_SET _ULL(0x200000000000) + +#define K1C_SFR_CS_RM_MASK _ULL(0x30000) /* IEEE 754 Rounding Mode */ +#define K1C_SFR_CS_RM_SHIFT 16 +#define K1C_SFR_CS_RM_WIDTH 2 +#define K1C_SFR_CS_RM_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_CS_RM_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_CS_RM_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_CS_XRM_MASK _ULL(0x300000) /* Extension IEEE 754 Rounding Mode */ +#define K1C_SFR_CS_XRM_SHIFT 20 +#define K1C_SFR_CS_XRM_WIDTH 2 +#define K1C_SFR_CS_XRM_WFXL_MASK _ULL(0x300000) +#define K1C_SFR_CS_XRM_WFXL_CLEAR _ULL(0x300000) +#define K1C_SFR_CS_XRM_WFXL_SET _ULL(0x30000000000000) + +#define K1C_SFR_CS_XMF_MASK _ULL(0x1000000) /* eXtension ModiFied */ +#define K1C_SFR_CS_XMF_SHIFT 24 +#define K1C_SFR_CS_XMF_WIDTH 1 +#define K1C_SFR_CS_XMF_WFXL_MASK _ULL(0x1000000) +#define K1C_SFR_CS_XMF_WFXL_CLEAR _ULL(0x1000000) +#define K1C_SFR_CS_XMF_WFXL_SET _ULL(0x100000000000000) + +#define K1C_SFR_CS_CC_MASK _ULL(0xffff00000000) /* Carry Counter */ +#define K1C_SFR_CS_CC_SHIFT 32 +#define K1C_SFR_CS_CC_WIDTH 16 +#define K1C_SFR_CS_CC_WFXM_MASK _ULL(0xffff00000000) +#define K1C_SFR_CS_CC_WFXM_CLEAR _ULL(0xffff) +#define K1C_SFR_CS_CC_WFXM_SET _ULL(0xffff00000000) + +#define K1C_SFR_CS_XDROP_MASK _ULL(0x3f000000000000) /* Extension Conversion Drop Bits */ +#define K1C_SFR_CS_XDROP_SHIFT 48 +#define K1C_SFR_CS_XDROP_WIDTH 6 +#define K1C_SFR_CS_XDROP_WFXM_MASK _ULL(0x3f000000000000) +#define K1C_SFR_CS_XDROP_WFXM_CLEAR _ULL(0x3f0000) +#define K1C_SFR_CS_XDROP_WFXM_SET _ULL(0x3f000000000000) + +#define K1C_SFR_CS_XPOW2_MASK _ULL(0xfc0000000000000) /* Extension FScale Power of Two */ +#define K1C_SFR_CS_XPOW2_SHIFT 54 +#define K1C_SFR_CS_XPOW2_WIDTH 6 +#define K1C_SFR_CS_XPOW2_WFXM_MASK _ULL(0xfc0000000000000) +#define K1C_SFR_CS_XPOW2_WFXM_CLEAR _ULL(0xfc00000) +#define K1C_SFR_CS_XPOW2_WFXM_SET _ULL(0xfc0000000000000) + +#define K1C_SFR_AESPC_AESPC_MASK _ULL(0xffffffffffffffff) /* Arithmetic Exception Saved PC */ +#define K1C_SFR_AESPC_AESPC_SHIFT 0 +#define K1C_SFR_AESPC_AESPC_WIDTH 64 +#define K1C_SFR_AESPC_AESPC_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_AESPC_AESPC_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_AESPC_AESPC_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_AESPC_AESPC_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_AESPC_AESPC_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_AESPC_AESPC_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_CSIT_ICIE_MASK _ULL(0x1) /* Integer Carry Interrupt Enable */ +#define K1C_SFR_CSIT_ICIE_SHIFT 0 +#define K1C_SFR_CSIT_ICIE_WIDTH 1 +#define K1C_SFR_CSIT_ICIE_WFXL_MASK _ULL(0x1) +#define K1C_SFR_CSIT_ICIE_WFXL_CLEAR _ULL(0x1) +#define K1C_SFR_CSIT_ICIE_WFXL_SET _ULL(0x100000000) + +#define K1C_SFR_CSIT_IOIE_MASK _ULL(0x2) /* IEEE 754 Invalid Operation Interrupt Enable */ +#define K1C_SFR_CSIT_IOIE_SHIFT 1 +#define K1C_SFR_CSIT_IOIE_WIDTH 1 +#define K1C_SFR_CSIT_IOIE_WFXL_MASK _ULL(0x2) +#define K1C_SFR_CSIT_IOIE_WFXL_CLEAR _ULL(0x2) +#define K1C_SFR_CSIT_IOIE_WFXL_SET _ULL(0x200000000) + +#define K1C_SFR_CSIT_DZIE_MASK _ULL(0x4) /* IEEE 754 Divide by Zero Interrupt Enable */ +#define K1C_SFR_CSIT_DZIE_SHIFT 2 +#define K1C_SFR_CSIT_DZIE_WIDTH 1 +#define K1C_SFR_CSIT_DZIE_WFXL_MASK _ULL(0x4) +#define K1C_SFR_CSIT_DZIE_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_CSIT_DZIE_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_CSIT_OVIE_MASK _ULL(0x8) /* IEEE 754 Overflow Interrupt Enable */ +#define K1C_SFR_CSIT_OVIE_SHIFT 3 +#define K1C_SFR_CSIT_OVIE_WIDTH 1 +#define K1C_SFR_CSIT_OVIE_WFXL_MASK _ULL(0x8) +#define K1C_SFR_CSIT_OVIE_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_CSIT_OVIE_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_CSIT_UNIE_MASK _ULL(0x10) /* IEEE 754 Underflow Interrupt Enable */ +#define K1C_SFR_CSIT_UNIE_SHIFT 4 +#define K1C_SFR_CSIT_UNIE_WIDTH 1 +#define K1C_SFR_CSIT_UNIE_WFXL_MASK _ULL(0x10) +#define K1C_SFR_CSIT_UNIE_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_CSIT_UNIE_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_CSIT_INIE_MASK _ULL(0x20) /* IEEE 754 Inexact Interrupt Enable */ +#define K1C_SFR_CSIT_INIE_SHIFT 5 +#define K1C_SFR_CSIT_INIE_WIDTH 1 +#define K1C_SFR_CSIT_INIE_WFXL_MASK _ULL(0x20) +#define K1C_SFR_CSIT_INIE_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_CSIT_INIE_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_CSIT_XIOIE_MASK _ULL(0x200) /* Extension IEEE 754 Invalid Operation Interrupt Enable */ +#define K1C_SFR_CSIT_XIOIE_SHIFT 9 +#define K1C_SFR_CSIT_XIOIE_WIDTH 1 +#define K1C_SFR_CSIT_XIOIE_WFXL_MASK _ULL(0x200) +#define K1C_SFR_CSIT_XIOIE_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_CSIT_XIOIE_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_CSIT_XDZIE_MASK _ULL(0x400) /* Extension IEEE 754 Divide by Zero Interrupt Enable */ +#define K1C_SFR_CSIT_XDZIE_SHIFT 10 +#define K1C_SFR_CSIT_XDZIE_WIDTH 1 +#define K1C_SFR_CSIT_XDZIE_WFXL_MASK _ULL(0x400) +#define K1C_SFR_CSIT_XDZIE_WFXL_CLEAR _ULL(0x400) +#define K1C_SFR_CSIT_XDZIE_WFXL_SET _ULL(0x40000000000) + +#define K1C_SFR_CSIT_XOVIE_MASK _ULL(0x800) /* Extension IEEE 754 Overflow Interrupt Enable */ +#define K1C_SFR_CSIT_XOVIE_SHIFT 11 +#define K1C_SFR_CSIT_XOVIE_WIDTH 1 +#define K1C_SFR_CSIT_XOVIE_WFXL_MASK _ULL(0x800) +#define K1C_SFR_CSIT_XOVIE_WFXL_CLEAR _ULL(0x800) +#define K1C_SFR_CSIT_XOVIE_WFXL_SET _ULL(0x80000000000) + +#define K1C_SFR_CSIT_XUNIE_MASK _ULL(0x1000) /* Extension IEEE 754 Underflow Interrupt Enable */ +#define K1C_SFR_CSIT_XUNIE_SHIFT 12 +#define K1C_SFR_CSIT_XUNIE_WIDTH 1 +#define K1C_SFR_CSIT_XUNIE_WFXL_MASK _ULL(0x1000) +#define K1C_SFR_CSIT_XUNIE_WFXL_CLEAR _ULL(0x1000) +#define K1C_SFR_CSIT_XUNIE_WFXL_SET _ULL(0x100000000000) + +#define K1C_SFR_CSIT_XINIE_MASK _ULL(0x2000) /* Extension IEEE 754 Inexact Interrupt Enable */ +#define K1C_SFR_CSIT_XINIE_SHIFT 13 +#define K1C_SFR_CSIT_XINIE_WIDTH 1 +#define K1C_SFR_CSIT_XINIE_WFXL_MASK _ULL(0x2000) +#define K1C_SFR_CSIT_XINIE_WFXL_CLEAR _ULL(0x2000) +#define K1C_SFR_CSIT_XINIE_WFXL_SET _ULL(0x200000000000) + +#define K1C_SFR_CSIT_AEIR_MASK _ULL(0x10000) /* Arithmetic Exception Interrupt Raised */ +#define K1C_SFR_CSIT_AEIR_SHIFT 16 +#define K1C_SFR_CSIT_AEIR_WIDTH 1 +#define K1C_SFR_CSIT_AEIR_WFXL_MASK _ULL(0x10000) +#define K1C_SFR_CSIT_AEIR_WFXL_CLEAR _ULL(0x10000) +#define K1C_SFR_CSIT_AEIR_WFXL_SET _ULL(0x1000000000000) + +#define K1C_SFR_CSIT_AEC_MASK _ULL(0xe0000) /* Arithmetic Exception Code */ +#define K1C_SFR_CSIT_AEC_SHIFT 17 +#define K1C_SFR_CSIT_AEC_WIDTH 3 +#define K1C_SFR_CSIT_AEC_WFXL_MASK _ULL(0xe0000) +#define K1C_SFR_CSIT_AEC_WFXL_CLEAR _ULL(0xe0000) +#define K1C_SFR_CSIT_AEC_WFXL_SET _ULL(0xe000000000000) + +#define K1C_SFR_CSIT_SPCV_MASK _ULL(0x100000) /* SPC Valid */ +#define K1C_SFR_CSIT_SPCV_SHIFT 20 +#define K1C_SFR_CSIT_SPCV_WIDTH 1 +#define K1C_SFR_CSIT_SPCV_WFXL_MASK _ULL(0x100000) +#define K1C_SFR_CSIT_SPCV_WFXL_CLEAR _ULL(0x100000) +#define K1C_SFR_CSIT_SPCV_WFXL_SET _ULL(0x10000000000000) + +#define K1C_SFR_ES_EC_MASK _ULL(0xf) /* Exception Class */ +#define K1C_SFR_ES_EC_SHIFT 0 +#define K1C_SFR_ES_EC_WIDTH 4 +#define K1C_SFR_ES_EC_WFXL_MASK _ULL(0xf) +#define K1C_SFR_ES_EC_WFXL_CLEAR _ULL(0xf) +#define K1C_SFR_ES_EC_WFXL_SET _ULL(0xf00000000) + +#define K1C_SFR_ES_ED_MASK _ULL(0xfffffffffffffff0) /* Exception Details */ +#define K1C_SFR_ES_ED_SHIFT 4 +#define K1C_SFR_ES_ED_WIDTH 60 +#define K1C_SFR_ES_ED_WFXL_MASK _ULL(0xfffffff0) +#define K1C_SFR_ES_ED_WFXL_CLEAR _ULL(0xfffffff0) +#define K1C_SFR_ES_ED_WFXL_SET _ULL(0xfffffff000000000) +#define K1C_SFR_ES_ED_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_ES_ED_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_ES_ED_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_ES_OAPL_MASK _ULL(0x30) /* Origin Absolute PL */ +#define K1C_SFR_ES_OAPL_SHIFT 4 +#define K1C_SFR_ES_OAPL_WIDTH 2 +#define K1C_SFR_ES_OAPL_WFXL_MASK _ULL(0x30) +#define K1C_SFR_ES_OAPL_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_ES_OAPL_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_ES_ORPL_MASK _ULL(0xc0) /* Origin Relative PL */ +#define K1C_SFR_ES_ORPL_SHIFT 6 +#define K1C_SFR_ES_ORPL_WIDTH 2 +#define K1C_SFR_ES_ORPL_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_ES_ORPL_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_ES_ORPL_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_ES_PTAPL_MASK _ULL(0x300) /* Primary Target Absolute PL */ +#define K1C_SFR_ES_PTAPL_SHIFT 8 +#define K1C_SFR_ES_PTAPL_WIDTH 2 +#define K1C_SFR_ES_PTAPL_WFXL_MASK _ULL(0x300) +#define K1C_SFR_ES_PTAPL_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_ES_PTAPL_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_ES_PTRPL_MASK _ULL(0xc00) /* Primary Target Relative PL */ +#define K1C_SFR_ES_PTRPL_SHIFT 10 +#define K1C_SFR_ES_PTRPL_WIDTH 2 +#define K1C_SFR_ES_PTRPL_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_ES_PTRPL_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_ES_PTRPL_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_ES_ITN_MASK _ULL(0x1f000) /* InTerrupt Number */ +#define K1C_SFR_ES_ITN_SHIFT 12 +#define K1C_SFR_ES_ITN_WIDTH 5 +#define K1C_SFR_ES_ITN_WFXL_MASK _ULL(0x1f000) +#define K1C_SFR_ES_ITN_WFXL_CLEAR _ULL(0x1f000) +#define K1C_SFR_ES_ITN_WFXL_SET _ULL(0x1f00000000000) + +#define K1C_SFR_ES_ITL_MASK _ULL(0x60000) /* InTerrupt Level */ +#define K1C_SFR_ES_ITL_SHIFT 17 +#define K1C_SFR_ES_ITL_WIDTH 2 +#define K1C_SFR_ES_ITL_WFXL_MASK _ULL(0x60000) +#define K1C_SFR_ES_ITL_WFXL_CLEAR _ULL(0x60000) +#define K1C_SFR_ES_ITL_WFXL_SET _ULL(0x6000000000000) + +#define K1C_SFR_ES_ITI_MASK _ULL(0x1ff80000) /* InTerrupt Info */ +#define K1C_SFR_ES_ITI_SHIFT 19 +#define K1C_SFR_ES_ITI_WIDTH 10 +#define K1C_SFR_ES_ITI_WFXL_MASK _ULL(0x1ff80000) +#define K1C_SFR_ES_ITI_WFXL_CLEAR _ULL(0x1ff80000) +#define K1C_SFR_ES_ITI_WFXL_SET _ULL(0x1ff8000000000000) + +#define K1C_SFR_ES_SN_MASK _ULL(0xfff000) /* Syscall Number */ +#define K1C_SFR_ES_SN_SHIFT 12 +#define K1C_SFR_ES_SN_WIDTH 12 +#define K1C_SFR_ES_SN_WFXL_MASK _ULL(0xfff000) +#define K1C_SFR_ES_SN_WFXL_CLEAR _ULL(0xfff000) +#define K1C_SFR_ES_SN_WFXL_SET _ULL(0xfff00000000000) + +#define K1C_SFR_ES_HTC_MASK _ULL(0x1f000) /* Hardware Trap Cause */ +#define K1C_SFR_ES_HTC_SHIFT 12 +#define K1C_SFR_ES_HTC_WIDTH 5 +#define K1C_SFR_ES_HTC_WFXL_MASK _ULL(0x1f000) +#define K1C_SFR_ES_HTC_WFXL_CLEAR _ULL(0x1f000) +#define K1C_SFR_ES_HTC_WFXL_SET _ULL(0x1f00000000000) + +#define K1C_SFR_ES_SFRT_MASK _ULL(0x20000) /* SFR Trap */ +#define K1C_SFR_ES_SFRT_SHIFT 17 +#define K1C_SFR_ES_SFRT_WIDTH 1 +#define K1C_SFR_ES_SFRT_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_ES_SFRT_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_ES_SFRT_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_ES_SFRI_MASK _ULL(0x1c0000) /* SFR Instruction */ +#define K1C_SFR_ES_SFRI_SHIFT 18 +#define K1C_SFR_ES_SFRI_WIDTH 3 +#define K1C_SFR_ES_SFRI_WFXL_MASK _ULL(0x1c0000) +#define K1C_SFR_ES_SFRI_WFXL_CLEAR _ULL(0x1c0000) +#define K1C_SFR_ES_SFRI_WFXL_SET _ULL(0x1c000000000000) + +#define K1C_SFR_ES_GPRP_MASK _ULL(0x7e00000) /* GPR Pointer */ +#define K1C_SFR_ES_GPRP_SHIFT 21 +#define K1C_SFR_ES_GPRP_WIDTH 6 +#define K1C_SFR_ES_GPRP_WFXL_MASK _ULL(0x7e00000) +#define K1C_SFR_ES_GPRP_WFXL_CLEAR _ULL(0x7e00000) +#define K1C_SFR_ES_GPRP_WFXL_SET _ULL(0x7e0000000000000) + +#define K1C_SFR_ES_SFRP_MASK _ULL(0xff8000000) /* SFR Pointer */ +#define K1C_SFR_ES_SFRP_SHIFT 27 +#define K1C_SFR_ES_SFRP_WIDTH 9 +#define K1C_SFR_ES_SFRP_WFXL_MASK _ULL(0xf8000000) +#define K1C_SFR_ES_SFRP_WFXL_CLEAR _ULL(0xf8000000) +#define K1C_SFR_ES_SFRP_WFXL_SET _ULL(0xf800000000000000) +#define K1C_SFR_ES_SFRP_WFXM_MASK _ULL(0xf00000000) +#define K1C_SFR_ES_SFRP_WFXM_CLEAR _ULL(0xf) +#define K1C_SFR_ES_SFRP_WFXM_SET _ULL(0xf00000000) + +#define K1C_SFR_ES_DHT_MASK _ULL(0x1000000000) /* Disabled Hardware Trap */ +#define K1C_SFR_ES_DHT_SHIFT 36 +#define K1C_SFR_ES_DHT_WIDTH 1 +#define K1C_SFR_ES_DHT_WFXM_MASK _ULL(0x1000000000) +#define K1C_SFR_ES_DHT_WFXM_CLEAR _ULL(0x10) +#define K1C_SFR_ES_DHT_WFXM_SET _ULL(0x1000000000) + +#define K1C_SFR_ES_RWX_MASK _ULL(0x38000000000) /* Read Write Execute */ +#define K1C_SFR_ES_RWX_SHIFT 39 +#define K1C_SFR_ES_RWX_WIDTH 3 +#define K1C_SFR_ES_RWX_WFXM_MASK _ULL(0x38000000000) +#define K1C_SFR_ES_RWX_WFXM_CLEAR _ULL(0x380) +#define K1C_SFR_ES_RWX_WFXM_SET _ULL(0x38000000000) + +#define K1C_SFR_ES_NTA_MASK _ULL(0x40000000000) /* Non-Trapping Access */ +#define K1C_SFR_ES_NTA_SHIFT 42 +#define K1C_SFR_ES_NTA_WIDTH 1 +#define K1C_SFR_ES_NTA_WFXM_MASK _ULL(0x40000000000) +#define K1C_SFR_ES_NTA_WFXM_CLEAR _ULL(0x400) +#define K1C_SFR_ES_NTA_WFXM_SET _ULL(0x40000000000) + +#define K1C_SFR_ES_UCA_MASK _ULL(0x80000000000) /* Un-Cached Access */ +#define K1C_SFR_ES_UCA_SHIFT 43 +#define K1C_SFR_ES_UCA_WIDTH 1 +#define K1C_SFR_ES_UCA_WFXM_MASK _ULL(0x80000000000) +#define K1C_SFR_ES_UCA_WFXM_CLEAR _ULL(0x800) +#define K1C_SFR_ES_UCA_WFXM_SET _ULL(0x80000000000) + +#define K1C_SFR_ES_AS_MASK _ULL(0x3f00000000000) /* Access Size */ +#define K1C_SFR_ES_AS_SHIFT 44 +#define K1C_SFR_ES_AS_WIDTH 6 +#define K1C_SFR_ES_AS_WFXM_MASK _ULL(0x3f00000000000) +#define K1C_SFR_ES_AS_WFXM_CLEAR _ULL(0x3f000) +#define K1C_SFR_ES_AS_WFXM_SET _ULL(0x3f00000000000) + +#define K1C_SFR_ES_BS_MASK _ULL(0x3c000000000000) /* Bundle Size */ +#define K1C_SFR_ES_BS_SHIFT 50 +#define K1C_SFR_ES_BS_WIDTH 4 +#define K1C_SFR_ES_BS_WFXM_MASK _ULL(0x3c000000000000) +#define K1C_SFR_ES_BS_WFXM_CLEAR _ULL(0x3c0000) +#define K1C_SFR_ES_BS_WFXM_SET _ULL(0x3c000000000000) + +#define K1C_SFR_ES_DRI_MASK _ULL(0xfc0000000000000) /* Data Register Index */ +#define K1C_SFR_ES_DRI_SHIFT 54 +#define K1C_SFR_ES_DRI_WIDTH 6 +#define K1C_SFR_ES_DRI_WFXM_MASK _ULL(0xfc0000000000000) +#define K1C_SFR_ES_DRI_WFXM_CLEAR _ULL(0xfc00000) +#define K1C_SFR_ES_DRI_WFXM_SET _ULL(0xfc0000000000000) + +#define K1C_SFR_ES_PIC_MASK _ULL(0xf000000000000000) /* Privileged Instruction Code */ +#define K1C_SFR_ES_PIC_SHIFT 60 +#define K1C_SFR_ES_PIC_WIDTH 4 +#define K1C_SFR_ES_PIC_WFXM_MASK _ULL(0xf000000000000000) +#define K1C_SFR_ES_PIC_WFXM_CLEAR _ULL(0xf0000000) +#define K1C_SFR_ES_PIC_WFXM_SET _ULL(0xf000000000000000) + +#define K1C_SFR_ES_DC_MASK _ULL(0x3000) /* Debug Cause */ +#define K1C_SFR_ES_DC_SHIFT 12 +#define K1C_SFR_ES_DC_WIDTH 2 +#define K1C_SFR_ES_DC_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_ES_DC_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_ES_DC_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_ES_BN_MASK _ULL(0x4000) /* Breakpoint Number */ +#define K1C_SFR_ES_BN_SHIFT 14 +#define K1C_SFR_ES_BN_WIDTH 1 +#define K1C_SFR_ES_BN_WFXL_MASK _ULL(0x4000) +#define K1C_SFR_ES_BN_WFXL_CLEAR _ULL(0x4000) +#define K1C_SFR_ES_BN_WFXL_SET _ULL(0x400000000000) + +#define K1C_SFR_ES_WN_MASK _ULL(0x8000) /* Watchpoint Number */ +#define K1C_SFR_ES_WN_SHIFT 15 +#define K1C_SFR_ES_WN_WIDTH 1 +#define K1C_SFR_ES_WN_WFXL_MASK _ULL(0x8000) +#define K1C_SFR_ES_WN_WFXL_CLEAR _ULL(0x8000) +#define K1C_SFR_ES_WN_WFXL_SET _ULL(0x800000000000) + +#define K1C_SFR_ES_PL0_EC_MASK _ULL(0xf) /* Exception Class */ +#define K1C_SFR_ES_PL0_EC_SHIFT 0 +#define K1C_SFR_ES_PL0_EC_WIDTH 4 +#define K1C_SFR_ES_PL0_EC_WFXL_MASK _ULL(0xf) +#define K1C_SFR_ES_PL0_EC_WFXL_CLEAR _ULL(0xf) +#define K1C_SFR_ES_PL0_EC_WFXL_SET _ULL(0xf00000000) + +#define K1C_SFR_ES_PL0_ED_MASK _ULL(0xfffffffffffffff0) /* Exception Details */ +#define K1C_SFR_ES_PL0_ED_SHIFT 4 +#define K1C_SFR_ES_PL0_ED_WIDTH 60 +#define K1C_SFR_ES_PL0_ED_WFXL_MASK _ULL(0xfffffff0) +#define K1C_SFR_ES_PL0_ED_WFXL_CLEAR _ULL(0xfffffff0) +#define K1C_SFR_ES_PL0_ED_WFXL_SET _ULL(0xfffffff000000000) +#define K1C_SFR_ES_PL0_ED_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_ES_PL0_ED_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_ES_PL0_ED_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_ES_PL0_OAPL_MASK _ULL(0x30) /* Origin Absolute PL */ +#define K1C_SFR_ES_PL0_OAPL_SHIFT 4 +#define K1C_SFR_ES_PL0_OAPL_WIDTH 2 +#define K1C_SFR_ES_PL0_OAPL_WFXL_MASK _ULL(0x30) +#define K1C_SFR_ES_PL0_OAPL_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_ES_PL0_OAPL_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_ES_PL0_ORPL_MASK _ULL(0xc0) /* Origin Relative PL */ +#define K1C_SFR_ES_PL0_ORPL_SHIFT 6 +#define K1C_SFR_ES_PL0_ORPL_WIDTH 2 +#define K1C_SFR_ES_PL0_ORPL_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_ES_PL0_ORPL_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_ES_PL0_ORPL_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_ES_PL0_PTAPL_MASK _ULL(0x300) /* Target Absolute PL */ +#define K1C_SFR_ES_PL0_PTAPL_SHIFT 8 +#define K1C_SFR_ES_PL0_PTAPL_WIDTH 2 +#define K1C_SFR_ES_PL0_PTAPL_WFXL_MASK _ULL(0x300) +#define K1C_SFR_ES_PL0_PTAPL_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_ES_PL0_PTAPL_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_ES_PL0_PTRPL_MASK _ULL(0xc00) /* Target Relative PL */ +#define K1C_SFR_ES_PL0_PTRPL_SHIFT 10 +#define K1C_SFR_ES_PL0_PTRPL_WIDTH 2 +#define K1C_SFR_ES_PL0_PTRPL_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_ES_PL0_PTRPL_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_ES_PL0_PTRPL_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_ES_PL0_ITN_MASK _ULL(0x1f000) /* InTerrupt Number */ +#define K1C_SFR_ES_PL0_ITN_SHIFT 12 +#define K1C_SFR_ES_PL0_ITN_WIDTH 5 +#define K1C_SFR_ES_PL0_ITN_WFXL_MASK _ULL(0x1f000) +#define K1C_SFR_ES_PL0_ITN_WFXL_CLEAR _ULL(0x1f000) +#define K1C_SFR_ES_PL0_ITN_WFXL_SET _ULL(0x1f00000000000) + +#define K1C_SFR_ES_PL0_ITL_MASK _ULL(0x60000) /* InTerrupt Level */ +#define K1C_SFR_ES_PL0_ITL_SHIFT 17 +#define K1C_SFR_ES_PL0_ITL_WIDTH 2 +#define K1C_SFR_ES_PL0_ITL_WFXL_MASK _ULL(0x60000) +#define K1C_SFR_ES_PL0_ITL_WFXL_CLEAR _ULL(0x60000) +#define K1C_SFR_ES_PL0_ITL_WFXL_SET _ULL(0x6000000000000) + +#define K1C_SFR_ES_PL0_ITI_MASK _ULL(0x1ff80000) /* InTerrupt Info */ +#define K1C_SFR_ES_PL0_ITI_SHIFT 19 +#define K1C_SFR_ES_PL0_ITI_WIDTH 10 +#define K1C_SFR_ES_PL0_ITI_WFXL_MASK _ULL(0x1ff80000) +#define K1C_SFR_ES_PL0_ITI_WFXL_CLEAR _ULL(0x1ff80000) +#define K1C_SFR_ES_PL0_ITI_WFXL_SET _ULL(0x1ff8000000000000) + +#define K1C_SFR_ES_PL0_SN_MASK _ULL(0xfff000) /* Syscall Number */ +#define K1C_SFR_ES_PL0_SN_SHIFT 12 +#define K1C_SFR_ES_PL0_SN_WIDTH 12 +#define K1C_SFR_ES_PL0_SN_WFXL_MASK _ULL(0xfff000) +#define K1C_SFR_ES_PL0_SN_WFXL_CLEAR _ULL(0xfff000) +#define K1C_SFR_ES_PL0_SN_WFXL_SET _ULL(0xfff00000000000) + +#define K1C_SFR_ES_PL0_HTC_MASK _ULL(0x1f000) /* Hardware Trap Cause */ +#define K1C_SFR_ES_PL0_HTC_SHIFT 12 +#define K1C_SFR_ES_PL0_HTC_WIDTH 5 +#define K1C_SFR_ES_PL0_HTC_WFXL_MASK _ULL(0x1f000) +#define K1C_SFR_ES_PL0_HTC_WFXL_CLEAR _ULL(0x1f000) +#define K1C_SFR_ES_PL0_HTC_WFXL_SET _ULL(0x1f00000000000) + +#define K1C_SFR_ES_PL0_SFRT_MASK _ULL(0x20000) /* SFR Trap */ +#define K1C_SFR_ES_PL0_SFRT_SHIFT 17 +#define K1C_SFR_ES_PL0_SFRT_WIDTH 1 +#define K1C_SFR_ES_PL0_SFRT_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_ES_PL0_SFRT_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_ES_PL0_SFRT_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_ES_PL0_SFRI_MASK _ULL(0x1c0000) /* SFR Instruction */ +#define K1C_SFR_ES_PL0_SFRI_SHIFT 18 +#define K1C_SFR_ES_PL0_SFRI_WIDTH 3 +#define K1C_SFR_ES_PL0_SFRI_WFXL_MASK _ULL(0x1c0000) +#define K1C_SFR_ES_PL0_SFRI_WFXL_CLEAR _ULL(0x1c0000) +#define K1C_SFR_ES_PL0_SFRI_WFXL_SET _ULL(0x1c000000000000) + +#define K1C_SFR_ES_PL0_GPRP_MASK _ULL(0x7e00000) /* GPR Pointer */ +#define K1C_SFR_ES_PL0_GPRP_SHIFT 21 +#define K1C_SFR_ES_PL0_GPRP_WIDTH 6 +#define K1C_SFR_ES_PL0_GPRP_WFXL_MASK _ULL(0x7e00000) +#define K1C_SFR_ES_PL0_GPRP_WFXL_CLEAR _ULL(0x7e00000) +#define K1C_SFR_ES_PL0_GPRP_WFXL_SET _ULL(0x7e0000000000000) + +#define K1C_SFR_ES_PL0_SFRP_MASK _ULL(0xff8000000) /* SFR Pointer */ +#define K1C_SFR_ES_PL0_SFRP_SHIFT 27 +#define K1C_SFR_ES_PL0_SFRP_WIDTH 9 +#define K1C_SFR_ES_PL0_SFRP_WFXL_MASK _ULL(0xf8000000) +#define K1C_SFR_ES_PL0_SFRP_WFXL_CLEAR _ULL(0xf8000000) +#define K1C_SFR_ES_PL0_SFRP_WFXL_SET _ULL(0xf800000000000000) +#define K1C_SFR_ES_PL0_SFRP_WFXM_MASK _ULL(0xf00000000) +#define K1C_SFR_ES_PL0_SFRP_WFXM_CLEAR _ULL(0xf) +#define K1C_SFR_ES_PL0_SFRP_WFXM_SET _ULL(0xf00000000) + +#define K1C_SFR_ES_PL0_DHT_MASK _ULL(0x1000000000) /* Disabled Hardware Trap */ +#define K1C_SFR_ES_PL0_DHT_SHIFT 36 +#define K1C_SFR_ES_PL0_DHT_WIDTH 1 +#define K1C_SFR_ES_PL0_DHT_WFXM_MASK _ULL(0x1000000000) +#define K1C_SFR_ES_PL0_DHT_WFXM_CLEAR _ULL(0x10) +#define K1C_SFR_ES_PL0_DHT_WFXM_SET _ULL(0x1000000000) + +#define K1C_SFR_ES_PL0_RWX_MASK _ULL(0x38000000000) /* Read Write Execute */ +#define K1C_SFR_ES_PL0_RWX_SHIFT 39 +#define K1C_SFR_ES_PL0_RWX_WIDTH 3 +#define K1C_SFR_ES_PL0_RWX_WFXM_MASK _ULL(0x38000000000) +#define K1C_SFR_ES_PL0_RWX_WFXM_CLEAR _ULL(0x380) +#define K1C_SFR_ES_PL0_RWX_WFXM_SET _ULL(0x38000000000) + +#define K1C_SFR_ES_PL0_NTA_MASK _ULL(0x40000000000) /* Non-Trapping Access */ +#define K1C_SFR_ES_PL0_NTA_SHIFT 42 +#define K1C_SFR_ES_PL0_NTA_WIDTH 1 +#define K1C_SFR_ES_PL0_NTA_WFXM_MASK _ULL(0x40000000000) +#define K1C_SFR_ES_PL0_NTA_WFXM_CLEAR _ULL(0x400) +#define K1C_SFR_ES_PL0_NTA_WFXM_SET _ULL(0x40000000000) + +#define K1C_SFR_ES_PL0_UCA_MASK _ULL(0x80000000000) /* Un-Cached Access */ +#define K1C_SFR_ES_PL0_UCA_SHIFT 43 +#define K1C_SFR_ES_PL0_UCA_WIDTH 1 +#define K1C_SFR_ES_PL0_UCA_WFXM_MASK _ULL(0x80000000000) +#define K1C_SFR_ES_PL0_UCA_WFXM_CLEAR _ULL(0x800) +#define K1C_SFR_ES_PL0_UCA_WFXM_SET _ULL(0x80000000000) + +#define K1C_SFR_ES_PL0_AS_MASK _ULL(0x3f00000000000) /* Access Size */ +#define K1C_SFR_ES_PL0_AS_SHIFT 44 +#define K1C_SFR_ES_PL0_AS_WIDTH 6 +#define K1C_SFR_ES_PL0_AS_WFXM_MASK _ULL(0x3f00000000000) +#define K1C_SFR_ES_PL0_AS_WFXM_CLEAR _ULL(0x3f000) +#define K1C_SFR_ES_PL0_AS_WFXM_SET _ULL(0x3f00000000000) + +#define K1C_SFR_ES_PL0_BS_MASK _ULL(0x3c000000000000) /* Bundle Size */ +#define K1C_SFR_ES_PL0_BS_SHIFT 50 +#define K1C_SFR_ES_PL0_BS_WIDTH 4 +#define K1C_SFR_ES_PL0_BS_WFXM_MASK _ULL(0x3c000000000000) +#define K1C_SFR_ES_PL0_BS_WFXM_CLEAR _ULL(0x3c0000) +#define K1C_SFR_ES_PL0_BS_WFXM_SET _ULL(0x3c000000000000) + +#define K1C_SFR_ES_PL0_DRI_MASK _ULL(0xfc0000000000000) /* Data Register Index */ +#define K1C_SFR_ES_PL0_DRI_SHIFT 54 +#define K1C_SFR_ES_PL0_DRI_WIDTH 6 +#define K1C_SFR_ES_PL0_DRI_WFXM_MASK _ULL(0xfc0000000000000) +#define K1C_SFR_ES_PL0_DRI_WFXM_CLEAR _ULL(0xfc00000) +#define K1C_SFR_ES_PL0_DRI_WFXM_SET _ULL(0xfc0000000000000) + +#define K1C_SFR_ES_PL0_PIC_MASK _ULL(0xf000000000000000) /* Privileged Instruction Code */ +#define K1C_SFR_ES_PL0_PIC_SHIFT 60 +#define K1C_SFR_ES_PL0_PIC_WIDTH 4 +#define K1C_SFR_ES_PL0_PIC_WFXM_MASK _ULL(0xf000000000000000) +#define K1C_SFR_ES_PL0_PIC_WFXM_CLEAR _ULL(0xf0000000) +#define K1C_SFR_ES_PL0_PIC_WFXM_SET _ULL(0xf000000000000000) + +#define K1C_SFR_ES_PL0_DC_MASK _ULL(0x3000) /* Debug Cause */ +#define K1C_SFR_ES_PL0_DC_SHIFT 12 +#define K1C_SFR_ES_PL0_DC_WIDTH 2 +#define K1C_SFR_ES_PL0_DC_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_ES_PL0_DC_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_ES_PL0_DC_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_ES_PL0_BN_MASK _ULL(0x4000) /* Breakpoint Number */ +#define K1C_SFR_ES_PL0_BN_SHIFT 14 +#define K1C_SFR_ES_PL0_BN_WIDTH 1 +#define K1C_SFR_ES_PL0_BN_WFXL_MASK _ULL(0x4000) +#define K1C_SFR_ES_PL0_BN_WFXL_CLEAR _ULL(0x4000) +#define K1C_SFR_ES_PL0_BN_WFXL_SET _ULL(0x400000000000) + +#define K1C_SFR_ES_PL0_WN_MASK _ULL(0x8000) /* Watchpoint Number */ +#define K1C_SFR_ES_PL0_WN_SHIFT 15 +#define K1C_SFR_ES_PL0_WN_WIDTH 1 +#define K1C_SFR_ES_PL0_WN_WFXL_MASK _ULL(0x8000) +#define K1C_SFR_ES_PL0_WN_WFXL_CLEAR _ULL(0x8000) +#define K1C_SFR_ES_PL0_WN_WFXL_SET _ULL(0x800000000000) + +#define K1C_SFR_ES_PL1_EC_MASK _ULL(0xf) /* Exception Class */ +#define K1C_SFR_ES_PL1_EC_SHIFT 0 +#define K1C_SFR_ES_PL1_EC_WIDTH 4 +#define K1C_SFR_ES_PL1_EC_WFXL_MASK _ULL(0xf) +#define K1C_SFR_ES_PL1_EC_WFXL_CLEAR _ULL(0xf) +#define K1C_SFR_ES_PL1_EC_WFXL_SET _ULL(0xf00000000) + +#define K1C_SFR_ES_PL1_ED_MASK _ULL(0xfffffffffffffff0) /* Exception Details */ +#define K1C_SFR_ES_PL1_ED_SHIFT 4 +#define K1C_SFR_ES_PL1_ED_WIDTH 60 +#define K1C_SFR_ES_PL1_ED_WFXL_MASK _ULL(0xfffffff0) +#define K1C_SFR_ES_PL1_ED_WFXL_CLEAR _ULL(0xfffffff0) +#define K1C_SFR_ES_PL1_ED_WFXL_SET _ULL(0xfffffff000000000) +#define K1C_SFR_ES_PL1_ED_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_ES_PL1_ED_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_ES_PL1_ED_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_ES_PL1_OAPL_MASK _ULL(0x30) /* Origin Absolute PL */ +#define K1C_SFR_ES_PL1_OAPL_SHIFT 4 +#define K1C_SFR_ES_PL1_OAPL_WIDTH 2 +#define K1C_SFR_ES_PL1_OAPL_WFXL_MASK _ULL(0x30) +#define K1C_SFR_ES_PL1_OAPL_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_ES_PL1_OAPL_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_ES_PL1_ORPL_MASK _ULL(0xc0) /* Origin Relative PL */ +#define K1C_SFR_ES_PL1_ORPL_SHIFT 6 +#define K1C_SFR_ES_PL1_ORPL_WIDTH 2 +#define K1C_SFR_ES_PL1_ORPL_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_ES_PL1_ORPL_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_ES_PL1_ORPL_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_ES_PL1_PTAPL_MASK _ULL(0x300) /* Target Absolute PL */ +#define K1C_SFR_ES_PL1_PTAPL_SHIFT 8 +#define K1C_SFR_ES_PL1_PTAPL_WIDTH 2 +#define K1C_SFR_ES_PL1_PTAPL_WFXL_MASK _ULL(0x300) +#define K1C_SFR_ES_PL1_PTAPL_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_ES_PL1_PTAPL_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_ES_PL1_PTRPL_MASK _ULL(0xc00) /* Target Relative PL */ +#define K1C_SFR_ES_PL1_PTRPL_SHIFT 10 +#define K1C_SFR_ES_PL1_PTRPL_WIDTH 2 +#define K1C_SFR_ES_PL1_PTRPL_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_ES_PL1_PTRPL_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_ES_PL1_PTRPL_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_ES_PL1_ITN_MASK _ULL(0x1f000) /* InTerrupt Number */ +#define K1C_SFR_ES_PL1_ITN_SHIFT 12 +#define K1C_SFR_ES_PL1_ITN_WIDTH 5 +#define K1C_SFR_ES_PL1_ITN_WFXL_MASK _ULL(0x1f000) +#define K1C_SFR_ES_PL1_ITN_WFXL_CLEAR _ULL(0x1f000) +#define K1C_SFR_ES_PL1_ITN_WFXL_SET _ULL(0x1f00000000000) + +#define K1C_SFR_ES_PL1_ITL_MASK _ULL(0x60000) /* InTerrupt Level */ +#define K1C_SFR_ES_PL1_ITL_SHIFT 17 +#define K1C_SFR_ES_PL1_ITL_WIDTH 2 +#define K1C_SFR_ES_PL1_ITL_WFXL_MASK _ULL(0x60000) +#define K1C_SFR_ES_PL1_ITL_WFXL_CLEAR _ULL(0x60000) +#define K1C_SFR_ES_PL1_ITL_WFXL_SET _ULL(0x6000000000000) + +#define K1C_SFR_ES_PL1_ITI_MASK _ULL(0x1ff80000) /* InTerrupt Info */ +#define K1C_SFR_ES_PL1_ITI_SHIFT 19 +#define K1C_SFR_ES_PL1_ITI_WIDTH 10 +#define K1C_SFR_ES_PL1_ITI_WFXL_MASK _ULL(0x1ff80000) +#define K1C_SFR_ES_PL1_ITI_WFXL_CLEAR _ULL(0x1ff80000) +#define K1C_SFR_ES_PL1_ITI_WFXL_SET _ULL(0x1ff8000000000000) + +#define K1C_SFR_ES_PL1_SN_MASK _ULL(0xfff000) /* Syscall Number */ +#define K1C_SFR_ES_PL1_SN_SHIFT 12 +#define K1C_SFR_ES_PL1_SN_WIDTH 12 +#define K1C_SFR_ES_PL1_SN_WFXL_MASK _ULL(0xfff000) +#define K1C_SFR_ES_PL1_SN_WFXL_CLEAR _ULL(0xfff000) +#define K1C_SFR_ES_PL1_SN_WFXL_SET _ULL(0xfff00000000000) + +#define K1C_SFR_ES_PL1_HTC_MASK _ULL(0x1f000) /* Hardware Trap Cause */ +#define K1C_SFR_ES_PL1_HTC_SHIFT 12 +#define K1C_SFR_ES_PL1_HTC_WIDTH 5 +#define K1C_SFR_ES_PL1_HTC_WFXL_MASK _ULL(0x1f000) +#define K1C_SFR_ES_PL1_HTC_WFXL_CLEAR _ULL(0x1f000) +#define K1C_SFR_ES_PL1_HTC_WFXL_SET _ULL(0x1f00000000000) + +#define K1C_SFR_ES_PL1_SFRT_MASK _ULL(0x20000) /* SFR Trap */ +#define K1C_SFR_ES_PL1_SFRT_SHIFT 17 +#define K1C_SFR_ES_PL1_SFRT_WIDTH 1 +#define K1C_SFR_ES_PL1_SFRT_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_ES_PL1_SFRT_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_ES_PL1_SFRT_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_ES_PL1_SFRI_MASK _ULL(0x1c0000) /* SFR Instruction */ +#define K1C_SFR_ES_PL1_SFRI_SHIFT 18 +#define K1C_SFR_ES_PL1_SFRI_WIDTH 3 +#define K1C_SFR_ES_PL1_SFRI_WFXL_MASK _ULL(0x1c0000) +#define K1C_SFR_ES_PL1_SFRI_WFXL_CLEAR _ULL(0x1c0000) +#define K1C_SFR_ES_PL1_SFRI_WFXL_SET _ULL(0x1c000000000000) + +#define K1C_SFR_ES_PL1_GPRP_MASK _ULL(0x7e00000) /* GPR Pointer */ +#define K1C_SFR_ES_PL1_GPRP_SHIFT 21 +#define K1C_SFR_ES_PL1_GPRP_WIDTH 6 +#define K1C_SFR_ES_PL1_GPRP_WFXL_MASK _ULL(0x7e00000) +#define K1C_SFR_ES_PL1_GPRP_WFXL_CLEAR _ULL(0x7e00000) +#define K1C_SFR_ES_PL1_GPRP_WFXL_SET _ULL(0x7e0000000000000) + +#define K1C_SFR_ES_PL1_SFRP_MASK _ULL(0xff8000000) /* SFR Pointer */ +#define K1C_SFR_ES_PL1_SFRP_SHIFT 27 +#define K1C_SFR_ES_PL1_SFRP_WIDTH 9 +#define K1C_SFR_ES_PL1_SFRP_WFXL_MASK _ULL(0xf8000000) +#define K1C_SFR_ES_PL1_SFRP_WFXL_CLEAR _ULL(0xf8000000) +#define K1C_SFR_ES_PL1_SFRP_WFXL_SET _ULL(0xf800000000000000) +#define K1C_SFR_ES_PL1_SFRP_WFXM_MASK _ULL(0xf00000000) +#define K1C_SFR_ES_PL1_SFRP_WFXM_CLEAR _ULL(0xf) +#define K1C_SFR_ES_PL1_SFRP_WFXM_SET _ULL(0xf00000000) + +#define K1C_SFR_ES_PL1_DHT_MASK _ULL(0x1000000000) /* Disabled Hardware Trap */ +#define K1C_SFR_ES_PL1_DHT_SHIFT 36 +#define K1C_SFR_ES_PL1_DHT_WIDTH 1 +#define K1C_SFR_ES_PL1_DHT_WFXM_MASK _ULL(0x1000000000) +#define K1C_SFR_ES_PL1_DHT_WFXM_CLEAR _ULL(0x10) +#define K1C_SFR_ES_PL1_DHT_WFXM_SET _ULL(0x1000000000) + +#define K1C_SFR_ES_PL1_RWX_MASK _ULL(0x38000000000) /* Read Write Execute */ +#define K1C_SFR_ES_PL1_RWX_SHIFT 39 +#define K1C_SFR_ES_PL1_RWX_WIDTH 3 +#define K1C_SFR_ES_PL1_RWX_WFXM_MASK _ULL(0x38000000000) +#define K1C_SFR_ES_PL1_RWX_WFXM_CLEAR _ULL(0x380) +#define K1C_SFR_ES_PL1_RWX_WFXM_SET _ULL(0x38000000000) + +#define K1C_SFR_ES_PL1_NTA_MASK _ULL(0x40000000000) /* Non-Trapping Access */ +#define K1C_SFR_ES_PL1_NTA_SHIFT 42 +#define K1C_SFR_ES_PL1_NTA_WIDTH 1 +#define K1C_SFR_ES_PL1_NTA_WFXM_MASK _ULL(0x40000000000) +#define K1C_SFR_ES_PL1_NTA_WFXM_CLEAR _ULL(0x400) +#define K1C_SFR_ES_PL1_NTA_WFXM_SET _ULL(0x40000000000) + +#define K1C_SFR_ES_PL1_UCA_MASK _ULL(0x80000000000) /* Un-Cached Access */ +#define K1C_SFR_ES_PL1_UCA_SHIFT 43 +#define K1C_SFR_ES_PL1_UCA_WIDTH 1 +#define K1C_SFR_ES_PL1_UCA_WFXM_MASK _ULL(0x80000000000) +#define K1C_SFR_ES_PL1_UCA_WFXM_CLEAR _ULL(0x800) +#define K1C_SFR_ES_PL1_UCA_WFXM_SET _ULL(0x80000000000) + +#define K1C_SFR_ES_PL1_AS_MASK _ULL(0x3f00000000000) /* Access Size */ +#define K1C_SFR_ES_PL1_AS_SHIFT 44 +#define K1C_SFR_ES_PL1_AS_WIDTH 6 +#define K1C_SFR_ES_PL1_AS_WFXM_MASK _ULL(0x3f00000000000) +#define K1C_SFR_ES_PL1_AS_WFXM_CLEAR _ULL(0x3f000) +#define K1C_SFR_ES_PL1_AS_WFXM_SET _ULL(0x3f00000000000) + +#define K1C_SFR_ES_PL1_BS_MASK _ULL(0x3c000000000000) /* Bundle Size */ +#define K1C_SFR_ES_PL1_BS_SHIFT 50 +#define K1C_SFR_ES_PL1_BS_WIDTH 4 +#define K1C_SFR_ES_PL1_BS_WFXM_MASK _ULL(0x3c000000000000) +#define K1C_SFR_ES_PL1_BS_WFXM_CLEAR _ULL(0x3c0000) +#define K1C_SFR_ES_PL1_BS_WFXM_SET _ULL(0x3c000000000000) + +#define K1C_SFR_ES_PL1_DRI_MASK _ULL(0xfc0000000000000) /* Data Register Index */ +#define K1C_SFR_ES_PL1_DRI_SHIFT 54 +#define K1C_SFR_ES_PL1_DRI_WIDTH 6 +#define K1C_SFR_ES_PL1_DRI_WFXM_MASK _ULL(0xfc0000000000000) +#define K1C_SFR_ES_PL1_DRI_WFXM_CLEAR _ULL(0xfc00000) +#define K1C_SFR_ES_PL1_DRI_WFXM_SET _ULL(0xfc0000000000000) + +#define K1C_SFR_ES_PL1_PIC_MASK _ULL(0xf000000000000000) /* Privileged Instruction Code */ +#define K1C_SFR_ES_PL1_PIC_SHIFT 60 +#define K1C_SFR_ES_PL1_PIC_WIDTH 4 +#define K1C_SFR_ES_PL1_PIC_WFXM_MASK _ULL(0xf000000000000000) +#define K1C_SFR_ES_PL1_PIC_WFXM_CLEAR _ULL(0xf0000000) +#define K1C_SFR_ES_PL1_PIC_WFXM_SET _ULL(0xf000000000000000) + +#define K1C_SFR_ES_PL1_DC_MASK _ULL(0x3000) /* Debug Cause */ +#define K1C_SFR_ES_PL1_DC_SHIFT 12 +#define K1C_SFR_ES_PL1_DC_WIDTH 2 +#define K1C_SFR_ES_PL1_DC_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_ES_PL1_DC_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_ES_PL1_DC_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_ES_PL1_BN_MASK _ULL(0x4000) /* Breakpoint Number */ +#define K1C_SFR_ES_PL1_BN_SHIFT 14 +#define K1C_SFR_ES_PL1_BN_WIDTH 1 +#define K1C_SFR_ES_PL1_BN_WFXL_MASK _ULL(0x4000) +#define K1C_SFR_ES_PL1_BN_WFXL_CLEAR _ULL(0x4000) +#define K1C_SFR_ES_PL1_BN_WFXL_SET _ULL(0x400000000000) + +#define K1C_SFR_ES_PL1_WN_MASK _ULL(0x8000) /* Watchpoint Number */ +#define K1C_SFR_ES_PL1_WN_SHIFT 15 +#define K1C_SFR_ES_PL1_WN_WIDTH 1 +#define K1C_SFR_ES_PL1_WN_WFXL_MASK _ULL(0x8000) +#define K1C_SFR_ES_PL1_WN_WFXL_CLEAR _ULL(0x8000) +#define K1C_SFR_ES_PL1_WN_WFXL_SET _ULL(0x800000000000) + +#define K1C_SFR_ES_PL2_EC_MASK _ULL(0xf) /* Exception Class */ +#define K1C_SFR_ES_PL2_EC_SHIFT 0 +#define K1C_SFR_ES_PL2_EC_WIDTH 4 +#define K1C_SFR_ES_PL2_EC_WFXL_MASK _ULL(0xf) +#define K1C_SFR_ES_PL2_EC_WFXL_CLEAR _ULL(0xf) +#define K1C_SFR_ES_PL2_EC_WFXL_SET _ULL(0xf00000000) + +#define K1C_SFR_ES_PL2_ED_MASK _ULL(0xfffffffffffffff0) /* Exception Details */ +#define K1C_SFR_ES_PL2_ED_SHIFT 4 +#define K1C_SFR_ES_PL2_ED_WIDTH 60 +#define K1C_SFR_ES_PL2_ED_WFXL_MASK _ULL(0xfffffff0) +#define K1C_SFR_ES_PL2_ED_WFXL_CLEAR _ULL(0xfffffff0) +#define K1C_SFR_ES_PL2_ED_WFXL_SET _ULL(0xfffffff000000000) +#define K1C_SFR_ES_PL2_ED_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_ES_PL2_ED_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_ES_PL2_ED_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_ES_PL2_OAPL_MASK _ULL(0x30) /* Origin Absolute PL */ +#define K1C_SFR_ES_PL2_OAPL_SHIFT 4 +#define K1C_SFR_ES_PL2_OAPL_WIDTH 2 +#define K1C_SFR_ES_PL2_OAPL_WFXL_MASK _ULL(0x30) +#define K1C_SFR_ES_PL2_OAPL_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_ES_PL2_OAPL_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_ES_PL2_ORPL_MASK _ULL(0xc0) /* Origin Relative PL */ +#define K1C_SFR_ES_PL2_ORPL_SHIFT 6 +#define K1C_SFR_ES_PL2_ORPL_WIDTH 2 +#define K1C_SFR_ES_PL2_ORPL_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_ES_PL2_ORPL_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_ES_PL2_ORPL_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_ES_PL2_PTAPL_MASK _ULL(0x300) /* Target Absolute PL */ +#define K1C_SFR_ES_PL2_PTAPL_SHIFT 8 +#define K1C_SFR_ES_PL2_PTAPL_WIDTH 2 +#define K1C_SFR_ES_PL2_PTAPL_WFXL_MASK _ULL(0x300) +#define K1C_SFR_ES_PL2_PTAPL_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_ES_PL2_PTAPL_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_ES_PL2_PTRPL_MASK _ULL(0xc00) /* Target Relative PL */ +#define K1C_SFR_ES_PL2_PTRPL_SHIFT 10 +#define K1C_SFR_ES_PL2_PTRPL_WIDTH 2 +#define K1C_SFR_ES_PL2_PTRPL_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_ES_PL2_PTRPL_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_ES_PL2_PTRPL_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_ES_PL2_ITN_MASK _ULL(0x1f000) /* InTerrupt Number */ +#define K1C_SFR_ES_PL2_ITN_SHIFT 12 +#define K1C_SFR_ES_PL2_ITN_WIDTH 5 +#define K1C_SFR_ES_PL2_ITN_WFXL_MASK _ULL(0x1f000) +#define K1C_SFR_ES_PL2_ITN_WFXL_CLEAR _ULL(0x1f000) +#define K1C_SFR_ES_PL2_ITN_WFXL_SET _ULL(0x1f00000000000) + +#define K1C_SFR_ES_PL2_ITL_MASK _ULL(0x60000) /* InTerrupt Level */ +#define K1C_SFR_ES_PL2_ITL_SHIFT 17 +#define K1C_SFR_ES_PL2_ITL_WIDTH 2 +#define K1C_SFR_ES_PL2_ITL_WFXL_MASK _ULL(0x60000) +#define K1C_SFR_ES_PL2_ITL_WFXL_CLEAR _ULL(0x60000) +#define K1C_SFR_ES_PL2_ITL_WFXL_SET _ULL(0x6000000000000) + +#define K1C_SFR_ES_PL2_ITI_MASK _ULL(0x1ff80000) /* InTerrupt Info */ +#define K1C_SFR_ES_PL2_ITI_SHIFT 19 +#define K1C_SFR_ES_PL2_ITI_WIDTH 10 +#define K1C_SFR_ES_PL2_ITI_WFXL_MASK _ULL(0x1ff80000) +#define K1C_SFR_ES_PL2_ITI_WFXL_CLEAR _ULL(0x1ff80000) +#define K1C_SFR_ES_PL2_ITI_WFXL_SET _ULL(0x1ff8000000000000) + +#define K1C_SFR_ES_PL2_SN_MASK _ULL(0xfff000) /* Syscall Number */ +#define K1C_SFR_ES_PL2_SN_SHIFT 12 +#define K1C_SFR_ES_PL2_SN_WIDTH 12 +#define K1C_SFR_ES_PL2_SN_WFXL_MASK _ULL(0xfff000) +#define K1C_SFR_ES_PL2_SN_WFXL_CLEAR _ULL(0xfff000) +#define K1C_SFR_ES_PL2_SN_WFXL_SET _ULL(0xfff00000000000) + +#define K1C_SFR_ES_PL2_HTC_MASK _ULL(0x1f000) /* Hardware Trap Cause */ +#define K1C_SFR_ES_PL2_HTC_SHIFT 12 +#define K1C_SFR_ES_PL2_HTC_WIDTH 5 +#define K1C_SFR_ES_PL2_HTC_WFXL_MASK _ULL(0x1f000) +#define K1C_SFR_ES_PL2_HTC_WFXL_CLEAR _ULL(0x1f000) +#define K1C_SFR_ES_PL2_HTC_WFXL_SET _ULL(0x1f00000000000) + +#define K1C_SFR_ES_PL2_SFRT_MASK _ULL(0x20000) /* SFR Trap */ +#define K1C_SFR_ES_PL2_SFRT_SHIFT 17 +#define K1C_SFR_ES_PL2_SFRT_WIDTH 1 +#define K1C_SFR_ES_PL2_SFRT_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_ES_PL2_SFRT_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_ES_PL2_SFRT_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_ES_PL2_SFRI_MASK _ULL(0x1c0000) /* SFR Instruction */ +#define K1C_SFR_ES_PL2_SFRI_SHIFT 18 +#define K1C_SFR_ES_PL2_SFRI_WIDTH 3 +#define K1C_SFR_ES_PL2_SFRI_WFXL_MASK _ULL(0x1c0000) +#define K1C_SFR_ES_PL2_SFRI_WFXL_CLEAR _ULL(0x1c0000) +#define K1C_SFR_ES_PL2_SFRI_WFXL_SET _ULL(0x1c000000000000) + +#define K1C_SFR_ES_PL2_GPRP_MASK _ULL(0x7e00000) /* GPR Pointer */ +#define K1C_SFR_ES_PL2_GPRP_SHIFT 21 +#define K1C_SFR_ES_PL2_GPRP_WIDTH 6 +#define K1C_SFR_ES_PL2_GPRP_WFXL_MASK _ULL(0x7e00000) +#define K1C_SFR_ES_PL2_GPRP_WFXL_CLEAR _ULL(0x7e00000) +#define K1C_SFR_ES_PL2_GPRP_WFXL_SET _ULL(0x7e0000000000000) + +#define K1C_SFR_ES_PL2_SFRP_MASK _ULL(0xff8000000) /* SFR Pointer */ +#define K1C_SFR_ES_PL2_SFRP_SHIFT 27 +#define K1C_SFR_ES_PL2_SFRP_WIDTH 9 +#define K1C_SFR_ES_PL2_SFRP_WFXL_MASK _ULL(0xf8000000) +#define K1C_SFR_ES_PL2_SFRP_WFXL_CLEAR _ULL(0xf8000000) +#define K1C_SFR_ES_PL2_SFRP_WFXL_SET _ULL(0xf800000000000000) +#define K1C_SFR_ES_PL2_SFRP_WFXM_MASK _ULL(0xf00000000) +#define K1C_SFR_ES_PL2_SFRP_WFXM_CLEAR _ULL(0xf) +#define K1C_SFR_ES_PL2_SFRP_WFXM_SET _ULL(0xf00000000) + +#define K1C_SFR_ES_PL2_DHT_MASK _ULL(0x1000000000) /* Disabled Hardware Trap */ +#define K1C_SFR_ES_PL2_DHT_SHIFT 36 +#define K1C_SFR_ES_PL2_DHT_WIDTH 1 +#define K1C_SFR_ES_PL2_DHT_WFXM_MASK _ULL(0x1000000000) +#define K1C_SFR_ES_PL2_DHT_WFXM_CLEAR _ULL(0x10) +#define K1C_SFR_ES_PL2_DHT_WFXM_SET _ULL(0x1000000000) + +#define K1C_SFR_ES_PL2_RWX_MASK _ULL(0x38000000000) /* Read Write Execute */ +#define K1C_SFR_ES_PL2_RWX_SHIFT 39 +#define K1C_SFR_ES_PL2_RWX_WIDTH 3 +#define K1C_SFR_ES_PL2_RWX_WFXM_MASK _ULL(0x38000000000) +#define K1C_SFR_ES_PL2_RWX_WFXM_CLEAR _ULL(0x380) +#define K1C_SFR_ES_PL2_RWX_WFXM_SET _ULL(0x38000000000) + +#define K1C_SFR_ES_PL2_NTA_MASK _ULL(0x40000000000) /* Non-Trapping Access */ +#define K1C_SFR_ES_PL2_NTA_SHIFT 42 +#define K1C_SFR_ES_PL2_NTA_WIDTH 1 +#define K1C_SFR_ES_PL2_NTA_WFXM_MASK _ULL(0x40000000000) +#define K1C_SFR_ES_PL2_NTA_WFXM_CLEAR _ULL(0x400) +#define K1C_SFR_ES_PL2_NTA_WFXM_SET _ULL(0x40000000000) + +#define K1C_SFR_ES_PL2_UCA_MASK _ULL(0x80000000000) /* Un-Cached Access */ +#define K1C_SFR_ES_PL2_UCA_SHIFT 43 +#define K1C_SFR_ES_PL2_UCA_WIDTH 1 +#define K1C_SFR_ES_PL2_UCA_WFXM_MASK _ULL(0x80000000000) +#define K1C_SFR_ES_PL2_UCA_WFXM_CLEAR _ULL(0x800) +#define K1C_SFR_ES_PL2_UCA_WFXM_SET _ULL(0x80000000000) + +#define K1C_SFR_ES_PL2_AS_MASK _ULL(0x3f00000000000) /* Access Size */ +#define K1C_SFR_ES_PL2_AS_SHIFT 44 +#define K1C_SFR_ES_PL2_AS_WIDTH 6 +#define K1C_SFR_ES_PL2_AS_WFXM_MASK _ULL(0x3f00000000000) +#define K1C_SFR_ES_PL2_AS_WFXM_CLEAR _ULL(0x3f000) +#define K1C_SFR_ES_PL2_AS_WFXM_SET _ULL(0x3f00000000000) + +#define K1C_SFR_ES_PL2_BS_MASK _ULL(0x3c000000000000) /* Bundle Size */ +#define K1C_SFR_ES_PL2_BS_SHIFT 50 +#define K1C_SFR_ES_PL2_BS_WIDTH 4 +#define K1C_SFR_ES_PL2_BS_WFXM_MASK _ULL(0x3c000000000000) +#define K1C_SFR_ES_PL2_BS_WFXM_CLEAR _ULL(0x3c0000) +#define K1C_SFR_ES_PL2_BS_WFXM_SET _ULL(0x3c000000000000) + +#define K1C_SFR_ES_PL2_DRI_MASK _ULL(0xfc0000000000000) /* Data Register Index */ +#define K1C_SFR_ES_PL2_DRI_SHIFT 54 +#define K1C_SFR_ES_PL2_DRI_WIDTH 6 +#define K1C_SFR_ES_PL2_DRI_WFXM_MASK _ULL(0xfc0000000000000) +#define K1C_SFR_ES_PL2_DRI_WFXM_CLEAR _ULL(0xfc00000) +#define K1C_SFR_ES_PL2_DRI_WFXM_SET _ULL(0xfc0000000000000) + +#define K1C_SFR_ES_PL2_PIC_MASK _ULL(0xf000000000000000) /* Privileged Instruction Code */ +#define K1C_SFR_ES_PL2_PIC_SHIFT 60 +#define K1C_SFR_ES_PL2_PIC_WIDTH 4 +#define K1C_SFR_ES_PL2_PIC_WFXM_MASK _ULL(0xf000000000000000) +#define K1C_SFR_ES_PL2_PIC_WFXM_CLEAR _ULL(0xf0000000) +#define K1C_SFR_ES_PL2_PIC_WFXM_SET _ULL(0xf000000000000000) + +#define K1C_SFR_ES_PL2_DC_MASK _ULL(0x3000) /* Debug Cause */ +#define K1C_SFR_ES_PL2_DC_SHIFT 12 +#define K1C_SFR_ES_PL2_DC_WIDTH 2 +#define K1C_SFR_ES_PL2_DC_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_ES_PL2_DC_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_ES_PL2_DC_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_ES_PL2_BN_MASK _ULL(0x4000) /* Breakpoint Number */ +#define K1C_SFR_ES_PL2_BN_SHIFT 14 +#define K1C_SFR_ES_PL2_BN_WIDTH 1 +#define K1C_SFR_ES_PL2_BN_WFXL_MASK _ULL(0x4000) +#define K1C_SFR_ES_PL2_BN_WFXL_CLEAR _ULL(0x4000) +#define K1C_SFR_ES_PL2_BN_WFXL_SET _ULL(0x400000000000) + +#define K1C_SFR_ES_PL2_WN_MASK _ULL(0x8000) /* Watchpoint Number */ +#define K1C_SFR_ES_PL2_WN_SHIFT 15 +#define K1C_SFR_ES_PL2_WN_WIDTH 1 +#define K1C_SFR_ES_PL2_WN_WFXL_MASK _ULL(0x8000) +#define K1C_SFR_ES_PL2_WN_WFXL_CLEAR _ULL(0x8000) +#define K1C_SFR_ES_PL2_WN_WFXL_SET _ULL(0x800000000000) + +#define K1C_SFR_ES_PL3_EC_MASK _ULL(0xf) /* Exception Class */ +#define K1C_SFR_ES_PL3_EC_SHIFT 0 +#define K1C_SFR_ES_PL3_EC_WIDTH 4 +#define K1C_SFR_ES_PL3_EC_WFXL_MASK _ULL(0xf) +#define K1C_SFR_ES_PL3_EC_WFXL_CLEAR _ULL(0xf) +#define K1C_SFR_ES_PL3_EC_WFXL_SET _ULL(0xf00000000) + +#define K1C_SFR_ES_PL3_ED_MASK _ULL(0xfffffffffffffff0) /* Exception Details */ +#define K1C_SFR_ES_PL3_ED_SHIFT 4 +#define K1C_SFR_ES_PL3_ED_WIDTH 60 +#define K1C_SFR_ES_PL3_ED_WFXL_MASK _ULL(0xfffffff0) +#define K1C_SFR_ES_PL3_ED_WFXL_CLEAR _ULL(0xfffffff0) +#define K1C_SFR_ES_PL3_ED_WFXL_SET _ULL(0xfffffff000000000) +#define K1C_SFR_ES_PL3_ED_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_ES_PL3_ED_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_ES_PL3_ED_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_ES_PL3_OAPL_MASK _ULL(0x30) /* Origin Absolute PL */ +#define K1C_SFR_ES_PL3_OAPL_SHIFT 4 +#define K1C_SFR_ES_PL3_OAPL_WIDTH 2 +#define K1C_SFR_ES_PL3_OAPL_WFXL_MASK _ULL(0x30) +#define K1C_SFR_ES_PL3_OAPL_WFXL_CLEAR _ULL(0x30) +#define K1C_SFR_ES_PL3_OAPL_WFXL_SET _ULL(0x3000000000) + +#define K1C_SFR_ES_PL3_ORPL_MASK _ULL(0xc0) /* Origin Relative PL */ +#define K1C_SFR_ES_PL3_ORPL_SHIFT 6 +#define K1C_SFR_ES_PL3_ORPL_WIDTH 2 +#define K1C_SFR_ES_PL3_ORPL_WFXL_MASK _ULL(0xc0) +#define K1C_SFR_ES_PL3_ORPL_WFXL_CLEAR _ULL(0xc0) +#define K1C_SFR_ES_PL3_ORPL_WFXL_SET _ULL(0xc000000000) + +#define K1C_SFR_ES_PL3_PTAPL_MASK _ULL(0x300) /* Target Absolute PL */ +#define K1C_SFR_ES_PL3_PTAPL_SHIFT 8 +#define K1C_SFR_ES_PL3_PTAPL_WIDTH 2 +#define K1C_SFR_ES_PL3_PTAPL_WFXL_MASK _ULL(0x300) +#define K1C_SFR_ES_PL3_PTAPL_WFXL_CLEAR _ULL(0x300) +#define K1C_SFR_ES_PL3_PTAPL_WFXL_SET _ULL(0x30000000000) + +#define K1C_SFR_ES_PL3_PTRPL_MASK _ULL(0xc00) /* Target Relative PL */ +#define K1C_SFR_ES_PL3_PTRPL_SHIFT 10 +#define K1C_SFR_ES_PL3_PTRPL_WIDTH 2 +#define K1C_SFR_ES_PL3_PTRPL_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_ES_PL3_PTRPL_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_ES_PL3_PTRPL_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_ES_PL3_ITN_MASK _ULL(0x1f000) /* InTerrupt Number */ +#define K1C_SFR_ES_PL3_ITN_SHIFT 12 +#define K1C_SFR_ES_PL3_ITN_WIDTH 5 +#define K1C_SFR_ES_PL3_ITN_WFXL_MASK _ULL(0x1f000) +#define K1C_SFR_ES_PL3_ITN_WFXL_CLEAR _ULL(0x1f000) +#define K1C_SFR_ES_PL3_ITN_WFXL_SET _ULL(0x1f00000000000) + +#define K1C_SFR_ES_PL3_ITL_MASK _ULL(0x60000) /* InTerrupt Level */ +#define K1C_SFR_ES_PL3_ITL_SHIFT 17 +#define K1C_SFR_ES_PL3_ITL_WIDTH 2 +#define K1C_SFR_ES_PL3_ITL_WFXL_MASK _ULL(0x60000) +#define K1C_SFR_ES_PL3_ITL_WFXL_CLEAR _ULL(0x60000) +#define K1C_SFR_ES_PL3_ITL_WFXL_SET _ULL(0x6000000000000) + +#define K1C_SFR_ES_PL3_ITI_MASK _ULL(0x1ff80000) /* InTerrupt Info */ +#define K1C_SFR_ES_PL3_ITI_SHIFT 19 +#define K1C_SFR_ES_PL3_ITI_WIDTH 10 +#define K1C_SFR_ES_PL3_ITI_WFXL_MASK _ULL(0x1ff80000) +#define K1C_SFR_ES_PL3_ITI_WFXL_CLEAR _ULL(0x1ff80000) +#define K1C_SFR_ES_PL3_ITI_WFXL_SET _ULL(0x1ff8000000000000) + +#define K1C_SFR_ES_PL3_SN_MASK _ULL(0xfff000) /* Syscall Number */ +#define K1C_SFR_ES_PL3_SN_SHIFT 12 +#define K1C_SFR_ES_PL3_SN_WIDTH 12 +#define K1C_SFR_ES_PL3_SN_WFXL_MASK _ULL(0xfff000) +#define K1C_SFR_ES_PL3_SN_WFXL_CLEAR _ULL(0xfff000) +#define K1C_SFR_ES_PL3_SN_WFXL_SET _ULL(0xfff00000000000) + +#define K1C_SFR_ES_PL3_HTC_MASK _ULL(0x1f000) /* Hardware Trap Cause */ +#define K1C_SFR_ES_PL3_HTC_SHIFT 12 +#define K1C_SFR_ES_PL3_HTC_WIDTH 5 +#define K1C_SFR_ES_PL3_HTC_WFXL_MASK _ULL(0x1f000) +#define K1C_SFR_ES_PL3_HTC_WFXL_CLEAR _ULL(0x1f000) +#define K1C_SFR_ES_PL3_HTC_WFXL_SET _ULL(0x1f00000000000) + +#define K1C_SFR_ES_PL3_SFRT_MASK _ULL(0x20000) /* SFR Trap */ +#define K1C_SFR_ES_PL3_SFRT_SHIFT 17 +#define K1C_SFR_ES_PL3_SFRT_WIDTH 1 +#define K1C_SFR_ES_PL3_SFRT_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_ES_PL3_SFRT_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_ES_PL3_SFRT_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_ES_PL3_SFRI_MASK _ULL(0x1c0000) /* SFR Instruction */ +#define K1C_SFR_ES_PL3_SFRI_SHIFT 18 +#define K1C_SFR_ES_PL3_SFRI_WIDTH 3 +#define K1C_SFR_ES_PL3_SFRI_WFXL_MASK _ULL(0x1c0000) +#define K1C_SFR_ES_PL3_SFRI_WFXL_CLEAR _ULL(0x1c0000) +#define K1C_SFR_ES_PL3_SFRI_WFXL_SET _ULL(0x1c000000000000) + +#define K1C_SFR_ES_PL3_GPRP_MASK _ULL(0x7e00000) /* GPR Pointer */ +#define K1C_SFR_ES_PL3_GPRP_SHIFT 21 +#define K1C_SFR_ES_PL3_GPRP_WIDTH 6 +#define K1C_SFR_ES_PL3_GPRP_WFXL_MASK _ULL(0x7e00000) +#define K1C_SFR_ES_PL3_GPRP_WFXL_CLEAR _ULL(0x7e00000) +#define K1C_SFR_ES_PL3_GPRP_WFXL_SET _ULL(0x7e0000000000000) + +#define K1C_SFR_ES_PL3_SFRP_MASK _ULL(0xff8000000) /* SFR Pointer */ +#define K1C_SFR_ES_PL3_SFRP_SHIFT 27 +#define K1C_SFR_ES_PL3_SFRP_WIDTH 9 +#define K1C_SFR_ES_PL3_SFRP_WFXL_MASK _ULL(0xf8000000) +#define K1C_SFR_ES_PL3_SFRP_WFXL_CLEAR _ULL(0xf8000000) +#define K1C_SFR_ES_PL3_SFRP_WFXL_SET _ULL(0xf800000000000000) +#define K1C_SFR_ES_PL3_SFRP_WFXM_MASK _ULL(0xf00000000) +#define K1C_SFR_ES_PL3_SFRP_WFXM_CLEAR _ULL(0xf) +#define K1C_SFR_ES_PL3_SFRP_WFXM_SET _ULL(0xf00000000) + +#define K1C_SFR_ES_PL3_DHT_MASK _ULL(0x1000000000) /* Disabled Hardware Trap */ +#define K1C_SFR_ES_PL3_DHT_SHIFT 36 +#define K1C_SFR_ES_PL3_DHT_WIDTH 1 +#define K1C_SFR_ES_PL3_DHT_WFXM_MASK _ULL(0x1000000000) +#define K1C_SFR_ES_PL3_DHT_WFXM_CLEAR _ULL(0x10) +#define K1C_SFR_ES_PL3_DHT_WFXM_SET _ULL(0x1000000000) + +#define K1C_SFR_ES_PL3_RWX_MASK _ULL(0x38000000000) /* Read Write Execute */ +#define K1C_SFR_ES_PL3_RWX_SHIFT 39 +#define K1C_SFR_ES_PL3_RWX_WIDTH 3 +#define K1C_SFR_ES_PL3_RWX_WFXM_MASK _ULL(0x38000000000) +#define K1C_SFR_ES_PL3_RWX_WFXM_CLEAR _ULL(0x380) +#define K1C_SFR_ES_PL3_RWX_WFXM_SET _ULL(0x38000000000) + +#define K1C_SFR_ES_PL3_NTA_MASK _ULL(0x40000000000) /* Non-Trapping Access */ +#define K1C_SFR_ES_PL3_NTA_SHIFT 42 +#define K1C_SFR_ES_PL3_NTA_WIDTH 1 +#define K1C_SFR_ES_PL3_NTA_WFXM_MASK _ULL(0x40000000000) +#define K1C_SFR_ES_PL3_NTA_WFXM_CLEAR _ULL(0x400) +#define K1C_SFR_ES_PL3_NTA_WFXM_SET _ULL(0x40000000000) + +#define K1C_SFR_ES_PL3_UCA_MASK _ULL(0x80000000000) /* Un-Cached Access */ +#define K1C_SFR_ES_PL3_UCA_SHIFT 43 +#define K1C_SFR_ES_PL3_UCA_WIDTH 1 +#define K1C_SFR_ES_PL3_UCA_WFXM_MASK _ULL(0x80000000000) +#define K1C_SFR_ES_PL3_UCA_WFXM_CLEAR _ULL(0x800) +#define K1C_SFR_ES_PL3_UCA_WFXM_SET _ULL(0x80000000000) + +#define K1C_SFR_ES_PL3_AS_MASK _ULL(0x3f00000000000) /* Access Size */ +#define K1C_SFR_ES_PL3_AS_SHIFT 44 +#define K1C_SFR_ES_PL3_AS_WIDTH 6 +#define K1C_SFR_ES_PL3_AS_WFXM_MASK _ULL(0x3f00000000000) +#define K1C_SFR_ES_PL3_AS_WFXM_CLEAR _ULL(0x3f000) +#define K1C_SFR_ES_PL3_AS_WFXM_SET _ULL(0x3f00000000000) + +#define K1C_SFR_ES_PL3_BS_MASK _ULL(0x3c000000000000) /* Bundle Size */ +#define K1C_SFR_ES_PL3_BS_SHIFT 50 +#define K1C_SFR_ES_PL3_BS_WIDTH 4 +#define K1C_SFR_ES_PL3_BS_WFXM_MASK _ULL(0x3c000000000000) +#define K1C_SFR_ES_PL3_BS_WFXM_CLEAR _ULL(0x3c0000) +#define K1C_SFR_ES_PL3_BS_WFXM_SET _ULL(0x3c000000000000) + +#define K1C_SFR_ES_PL3_DRI_MASK _ULL(0xfc0000000000000) /* Data Register Index */ +#define K1C_SFR_ES_PL3_DRI_SHIFT 54 +#define K1C_SFR_ES_PL3_DRI_WIDTH 6 +#define K1C_SFR_ES_PL3_DRI_WFXM_MASK _ULL(0xfc0000000000000) +#define K1C_SFR_ES_PL3_DRI_WFXM_CLEAR _ULL(0xfc00000) +#define K1C_SFR_ES_PL3_DRI_WFXM_SET _ULL(0xfc0000000000000) + +#define K1C_SFR_ES_PL3_PIC_MASK _ULL(0xf000000000000000) /* Privileged Instruction Code */ +#define K1C_SFR_ES_PL3_PIC_SHIFT 60 +#define K1C_SFR_ES_PL3_PIC_WIDTH 4 +#define K1C_SFR_ES_PL3_PIC_WFXM_MASK _ULL(0xf000000000000000) +#define K1C_SFR_ES_PL3_PIC_WFXM_CLEAR _ULL(0xf0000000) +#define K1C_SFR_ES_PL3_PIC_WFXM_SET _ULL(0xf000000000000000) + +#define K1C_SFR_ES_PL3_DC_MASK _ULL(0x3000) /* Debug Cause */ +#define K1C_SFR_ES_PL3_DC_SHIFT 12 +#define K1C_SFR_ES_PL3_DC_WIDTH 2 +#define K1C_SFR_ES_PL3_DC_WFXL_MASK _ULL(0x3000) +#define K1C_SFR_ES_PL3_DC_WFXL_CLEAR _ULL(0x3000) +#define K1C_SFR_ES_PL3_DC_WFXL_SET _ULL(0x300000000000) + +#define K1C_SFR_ES_PL3_BN_MASK _ULL(0x4000) /* Breakpoint Number */ +#define K1C_SFR_ES_PL3_BN_SHIFT 14 +#define K1C_SFR_ES_PL3_BN_WIDTH 1 +#define K1C_SFR_ES_PL3_BN_WFXL_MASK _ULL(0x4000) +#define K1C_SFR_ES_PL3_BN_WFXL_CLEAR _ULL(0x4000) +#define K1C_SFR_ES_PL3_BN_WFXL_SET _ULL(0x400000000000) + +#define K1C_SFR_ES_PL3_WN_MASK _ULL(0x8000) /* Watchpoint Number */ +#define K1C_SFR_ES_PL3_WN_SHIFT 15 +#define K1C_SFR_ES_PL3_WN_WIDTH 1 +#define K1C_SFR_ES_PL3_WN_WFXL_MASK _ULL(0x8000) +#define K1C_SFR_ES_PL3_WN_WFXL_CLEAR _ULL(0x8000) +#define K1C_SFR_ES_PL3_WN_WFXL_SET _ULL(0x800000000000) + +#define K1C_SFR_TCR_T0CE_MASK _ULL(0x10000) /* Timer 0 Count Enable */ +#define K1C_SFR_TCR_T0CE_SHIFT 16 +#define K1C_SFR_TCR_T0CE_WIDTH 1 +#define K1C_SFR_TCR_T0CE_WFXL_MASK _ULL(0x10000) +#define K1C_SFR_TCR_T0CE_WFXL_CLEAR _ULL(0x10000) +#define K1C_SFR_TCR_T0CE_WFXL_SET _ULL(0x1000000000000) + +#define K1C_SFR_TCR_T1CE_MASK _ULL(0x20000) /* Timer 1 Count Enable */ +#define K1C_SFR_TCR_T1CE_SHIFT 17 +#define K1C_SFR_TCR_T1CE_WIDTH 1 +#define K1C_SFR_TCR_T1CE_WFXL_MASK _ULL(0x20000) +#define K1C_SFR_TCR_T1CE_WFXL_CLEAR _ULL(0x20000) +#define K1C_SFR_TCR_T1CE_WFXL_SET _ULL(0x2000000000000) + +#define K1C_SFR_TCR_T0IE_MASK _ULL(0x40000) /* Timer 0 Interrupt Enable */ +#define K1C_SFR_TCR_T0IE_SHIFT 18 +#define K1C_SFR_TCR_T0IE_WIDTH 1 +#define K1C_SFR_TCR_T0IE_WFXL_MASK _ULL(0x40000) +#define K1C_SFR_TCR_T0IE_WFXL_CLEAR _ULL(0x40000) +#define K1C_SFR_TCR_T0IE_WFXL_SET _ULL(0x4000000000000) + +#define K1C_SFR_TCR_T1IE_MASK _ULL(0x80000) /* Timer 1 Interrupt Enable */ +#define K1C_SFR_TCR_T1IE_SHIFT 19 +#define K1C_SFR_TCR_T1IE_WIDTH 1 +#define K1C_SFR_TCR_T1IE_WFXL_MASK _ULL(0x80000) +#define K1C_SFR_TCR_T1IE_WFXL_CLEAR _ULL(0x80000) +#define K1C_SFR_TCR_T1IE_WFXL_SET _ULL(0x8000000000000) + +#define K1C_SFR_TCR_T0ST_MASK _ULL(0x100000) /* Timer 0 Status */ +#define K1C_SFR_TCR_T0ST_SHIFT 20 +#define K1C_SFR_TCR_T0ST_WIDTH 1 +#define K1C_SFR_TCR_T0ST_WFXL_MASK _ULL(0x100000) +#define K1C_SFR_TCR_T0ST_WFXL_CLEAR _ULL(0x100000) +#define K1C_SFR_TCR_T0ST_WFXL_SET _ULL(0x10000000000000) + +#define K1C_SFR_TCR_T1ST_MASK _ULL(0x200000) /* Timer 1 Status */ +#define K1C_SFR_TCR_T1ST_SHIFT 21 +#define K1C_SFR_TCR_T1ST_WIDTH 1 +#define K1C_SFR_TCR_T1ST_WFXL_MASK _ULL(0x200000) +#define K1C_SFR_TCR_T1ST_WFXL_CLEAR _ULL(0x200000) +#define K1C_SFR_TCR_T1ST_WFXL_SET _ULL(0x20000000000000) + +#define K1C_SFR_TCR_T0SI_MASK _ULL(0x400000) /* Stop Timer 0 in Idle */ +#define K1C_SFR_TCR_T0SI_SHIFT 22 +#define K1C_SFR_TCR_T0SI_WIDTH 1 +#define K1C_SFR_TCR_T0SI_WFXL_MASK _ULL(0x400000) +#define K1C_SFR_TCR_T0SI_WFXL_CLEAR _ULL(0x400000) +#define K1C_SFR_TCR_T0SI_WFXL_SET _ULL(0x40000000000000) + +#define K1C_SFR_TCR_T1SI_MASK _ULL(0x800000) /* Stop Timer 1 in Idle */ +#define K1C_SFR_TCR_T1SI_SHIFT 23 +#define K1C_SFR_TCR_T1SI_WIDTH 1 +#define K1C_SFR_TCR_T1SI_WFXL_MASK _ULL(0x800000) +#define K1C_SFR_TCR_T1SI_WFXL_CLEAR _ULL(0x800000) +#define K1C_SFR_TCR_T1SI_WFXL_SET _ULL(0x80000000000000) + +#define K1C_SFR_TCR_WCE_MASK _ULL(0x1000000) /* Watchdog Counting Enable */ +#define K1C_SFR_TCR_WCE_SHIFT 24 +#define K1C_SFR_TCR_WCE_WIDTH 1 +#define K1C_SFR_TCR_WCE_WFXL_MASK _ULL(0x1000000) +#define K1C_SFR_TCR_WCE_WFXL_CLEAR _ULL(0x1000000) +#define K1C_SFR_TCR_WCE_WFXL_SET _ULL(0x100000000000000) + +#define K1C_SFR_TCR_WIE_MASK _ULL(0x2000000) /* Watchdog Interrupt Enable */ +#define K1C_SFR_TCR_WIE_SHIFT 25 +#define K1C_SFR_TCR_WIE_WIDTH 1 +#define K1C_SFR_TCR_WIE_WFXL_MASK _ULL(0x2000000) +#define K1C_SFR_TCR_WIE_WFXL_CLEAR _ULL(0x2000000) +#define K1C_SFR_TCR_WIE_WFXL_SET _ULL(0x200000000000000) + +#define K1C_SFR_TCR_WUI_MASK _ULL(0x4000000) /* Watchdog Underflow Inform */ +#define K1C_SFR_TCR_WUI_SHIFT 26 +#define K1C_SFR_TCR_WUI_WIDTH 1 +#define K1C_SFR_TCR_WUI_WFXL_MASK _ULL(0x4000000) +#define K1C_SFR_TCR_WUI_WFXL_CLEAR _ULL(0x4000000) +#define K1C_SFR_TCR_WUI_WFXL_SET _ULL(0x400000000000000) + +#define K1C_SFR_TCR_WUS_MASK _ULL(0x8000000) /* Watchdog Underflow Status */ +#define K1C_SFR_TCR_WUS_SHIFT 27 +#define K1C_SFR_TCR_WUS_WIDTH 1 +#define K1C_SFR_TCR_WUS_WFXL_MASK _ULL(0x8000000) +#define K1C_SFR_TCR_WUS_WFXL_CLEAR _ULL(0x8000000) +#define K1C_SFR_TCR_WUS_WFXL_SET _ULL(0x800000000000000) + +#define K1C_SFR_TCR_WSI_MASK _ULL(0x10000000) /* Watchdog Stop in Idle */ +#define K1C_SFR_TCR_WSI_SHIFT 28 +#define K1C_SFR_TCR_WSI_WIDTH 1 +#define K1C_SFR_TCR_WSI_WFXL_MASK _ULL(0x10000000) +#define K1C_SFR_TCR_WSI_WFXL_CLEAR _ULL(0x10000000) +#define K1C_SFR_TCR_WSI_WFXL_SET _ULL(0x1000000000000000) + +#define K1C_SFR_PM0_PM0_MASK _ULL(0xffffffffffffffff) /* Performance Monitor 0 */ +#define K1C_SFR_PM0_PM0_SHIFT 0 +#define K1C_SFR_PM0_PM0_WIDTH 64 +#define K1C_SFR_PM0_PM0_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_PM0_PM0_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_PM0_PM0_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_PM0_PM0_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_PM0_PM0_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_PM0_PM0_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_PM1_PM1_MASK _ULL(0xffffffffffffffff) /* Performance Monitor 1 */ +#define K1C_SFR_PM1_PM1_SHIFT 0 +#define K1C_SFR_PM1_PM1_WIDTH 64 +#define K1C_SFR_PM1_PM1_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_PM1_PM1_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_PM1_PM1_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_PM1_PM1_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_PM1_PM1_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_PM1_PM1_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_PM2_PM2_MASK _ULL(0xffffffffffffffff) /* Performance Monitor 2 */ +#define K1C_SFR_PM2_PM2_SHIFT 0 +#define K1C_SFR_PM2_PM2_WIDTH 64 +#define K1C_SFR_PM2_PM2_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_PM2_PM2_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_PM2_PM2_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_PM2_PM2_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_PM2_PM2_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_PM2_PM2_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_PM3_PM3_MASK _ULL(0xffffffffffffffff) /* Performance Monitor 3 */ +#define K1C_SFR_PM3_PM3_SHIFT 0 +#define K1C_SFR_PM3_PM3_WIDTH 64 +#define K1C_SFR_PM3_PM3_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_PM3_PM3_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_PM3_PM3_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_PM3_PM3_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_PM3_PM3_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_PM3_PM3_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_PMSA_PMSA_MASK _ULL(0xffffffffffffffff) /* Performance Monitor Saved Address */ +#define K1C_SFR_PMSA_PMSA_SHIFT 0 +#define K1C_SFR_PMSA_PMSA_WIDTH 64 +#define K1C_SFR_PMSA_PMSA_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_PMSA_PMSA_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_PMSA_PMSA_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_PMSA_PMSA_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_PMSA_PMSA_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_PMSA_PMSA_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_T0V_T0V_MASK _ULL(0xffffffffffffffff) /* Timer 0 value */ +#define K1C_SFR_T0V_T0V_SHIFT 0 +#define K1C_SFR_T0V_T0V_WIDTH 64 +#define K1C_SFR_T0V_T0V_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_T0V_T0V_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_T0V_T0V_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_T0V_T0V_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_T0V_T0V_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_T0V_T0V_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_T1V_T1V_MASK _ULL(0xffffffffffffffff) /* Timer 1 value */ +#define K1C_SFR_T1V_T1V_SHIFT 0 +#define K1C_SFR_T1V_T1V_WIDTH 64 +#define K1C_SFR_T1V_T1V_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_T1V_T1V_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_T1V_T1V_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_T1V_T1V_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_T1V_T1V_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_T1V_T1V_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_T0R_T0R_MASK _ULL(0xffffffffffffffff) /* Timer 0 reload value */ +#define K1C_SFR_T0R_T0R_SHIFT 0 +#define K1C_SFR_T0R_T0R_WIDTH 64 +#define K1C_SFR_T0R_T0R_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_T0R_T0R_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_T0R_T0R_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_T0R_T0R_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_T0R_T0R_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_T0R_T0R_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_T1R_T1R_MASK _ULL(0xffffffffffffffff) /* Timer 1 reload value */ +#define K1C_SFR_T1R_T1R_SHIFT 0 +#define K1C_SFR_T1R_T1R_WIDTH 64 +#define K1C_SFR_T1R_T1R_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_T1R_T1R_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_T1R_T1R_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_T1R_T1R_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_T1R_T1R_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_T1R_T1R_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_WDV_WDV_MASK _ULL(0xffffffffffffffff) /* Watchdog Value */ +#define K1C_SFR_WDV_WDV_SHIFT 0 +#define K1C_SFR_WDV_WDV_WIDTH 64 +#define K1C_SFR_WDV_WDV_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_WDV_WDV_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_WDV_WDV_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_WDV_WDV_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_WDV_WDV_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_WDV_WDV_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_WDR_WDR_MASK _ULL(0xffffffffffffffff) /* Watchdog Reload Value */ +#define K1C_SFR_WDR_WDR_SHIFT 0 +#define K1C_SFR_WDR_WDR_WIDTH 64 +#define K1C_SFR_WDR_WDR_WFXL_MASK _ULL(0xffffffff) +#define K1C_SFR_WDR_WDR_WFXL_CLEAR _ULL(0xffffffff) +#define K1C_SFR_WDR_WDR_WFXL_SET _ULL(0xffffffff00000000) +#define K1C_SFR_WDR_WDR_WFXM_MASK _ULL(0xffffffff00000000) +#define K1C_SFR_WDR_WDR_WFXM_CLEAR _ULL(0xffffffff) +#define K1C_SFR_WDR_WDR_WFXM_SET _ULL(0xffffffff00000000) + +#define K1C_SFR_PMC_PM0C_MASK _ULL(0x3f) /* PM0 Configuration */ +#define K1C_SFR_PMC_PM0C_SHIFT 0 +#define K1C_SFR_PMC_PM0C_WIDTH 6 +#define K1C_SFR_PMC_PM0C_WFXL_MASK _ULL(0x3f) +#define K1C_SFR_PMC_PM0C_WFXL_CLEAR _ULL(0x3f) +#define K1C_SFR_PMC_PM0C_WFXL_SET _ULL(0x3f00000000) + +#define K1C_SFR_PMC_PM1C_MASK _ULL(0x1f80) /* PM1 Configuration */ +#define K1C_SFR_PMC_PM1C_SHIFT 7 +#define K1C_SFR_PMC_PM1C_WIDTH 6 +#define K1C_SFR_PMC_PM1C_WFXL_MASK _ULL(0x1f80) +#define K1C_SFR_PMC_PM1C_WFXL_CLEAR _ULL(0x1f80) +#define K1C_SFR_PMC_PM1C_WFXL_SET _ULL(0x1f8000000000) + +#define K1C_SFR_PMC_PM2C_MASK _ULL(0xfc000) /* PM2 Configuration */ +#define K1C_SFR_PMC_PM2C_SHIFT 14 +#define K1C_SFR_PMC_PM2C_WIDTH 6 +#define K1C_SFR_PMC_PM2C_WFXL_MASK _ULL(0xfc000) +#define K1C_SFR_PMC_PM2C_WFXL_CLEAR _ULL(0xfc000) +#define K1C_SFR_PMC_PM2C_WFXL_SET _ULL(0xfc00000000000) + +#define K1C_SFR_PMC_PM3C_MASK _ULL(0x7e00000) /* PM3 Configuration */ +#define K1C_SFR_PMC_PM3C_SHIFT 21 +#define K1C_SFR_PMC_PM3C_WIDTH 6 +#define K1C_SFR_PMC_PM3C_WFXL_MASK _ULL(0x7e00000) +#define K1C_SFR_PMC_PM3C_WFXL_CLEAR _ULL(0x7e00000) +#define K1C_SFR_PMC_PM3C_WFXL_SET _ULL(0x7e0000000000000) + +#define K1C_SFR_PMC_SAV_MASK _ULL(0x40000000) /* Saved Address Valid */ +#define K1C_SFR_PMC_SAV_SHIFT 30 +#define K1C_SFR_PMC_SAV_WIDTH 1 +#define K1C_SFR_PMC_SAV_WFXL_MASK _ULL(0x40000000) +#define K1C_SFR_PMC_SAV_WFXL_CLEAR _ULL(0x40000000) +#define K1C_SFR_PMC_SAV_WFXL_SET _ULL(0x4000000000000000) + +#define K1C_SFR_PMC_PM0IE_MASK _ULL(0x100000000) /* PM0 Interrupt Enable */ +#define K1C_SFR_PMC_PM0IE_SHIFT 32 +#define K1C_SFR_PMC_PM0IE_WIDTH 1 +#define K1C_SFR_PMC_PM0IE_WFXM_MASK _ULL(0x100000000) +#define K1C_SFR_PMC_PM0IE_WFXM_CLEAR _ULL(0x1) +#define K1C_SFR_PMC_PM0IE_WFXM_SET _ULL(0x100000000) + +#define K1C_SFR_PMC_PM1IE_MASK _ULL(0x200000000) /* PM1 Interrupt Enable */ +#define K1C_SFR_PMC_PM1IE_SHIFT 33 +#define K1C_SFR_PMC_PM1IE_WIDTH 1 +#define K1C_SFR_PMC_PM1IE_WFXM_MASK _ULL(0x200000000) +#define K1C_SFR_PMC_PM1IE_WFXM_CLEAR _ULL(0x2) +#define K1C_SFR_PMC_PM1IE_WFXM_SET _ULL(0x200000000) + +#define K1C_SFR_PMC_PM2IE_MASK _ULL(0x400000000) /* PM2 Interrupt Enable */ +#define K1C_SFR_PMC_PM2IE_SHIFT 34 +#define K1C_SFR_PMC_PM2IE_WIDTH 1 +#define K1C_SFR_PMC_PM2IE_WFXM_MASK _ULL(0x400000000) +#define K1C_SFR_PMC_PM2IE_WFXM_CLEAR _ULL(0x4) +#define K1C_SFR_PMC_PM2IE_WFXM_SET _ULL(0x400000000) + +#define K1C_SFR_PMC_PM3IE_MASK _ULL(0x800000000) /* PM3 Interrupt Enable */ +#define K1C_SFR_PMC_PM3IE_SHIFT 35 +#define K1C_SFR_PMC_PM3IE_WIDTH 1 +#define K1C_SFR_PMC_PM3IE_WFXM_MASK _ULL(0x800000000) +#define K1C_SFR_PMC_PM3IE_WFXM_CLEAR _ULL(0x8) +#define K1C_SFR_PMC_PM3IE_WFXM_SET _ULL(0x800000000) + +#define K1C_SFR_PMC_SAT_MASK _ULL(0x3000000000) /* Saved Address Type */ +#define K1C_SFR_PMC_SAT_SHIFT 36 +#define K1C_SFR_PMC_SAT_WIDTH 2 +#define K1C_SFR_PMC_SAT_WFXM_MASK _ULL(0x3000000000) +#define K1C_SFR_PMC_SAT_WFXM_CLEAR _ULL(0x30) +#define K1C_SFR_PMC_SAT_WFXM_SET _ULL(0x3000000000) + +#define K1C_SFR_PCR_PID_MASK _ULL(0xff) /* Processing Identifier in cluster */ +#define K1C_SFR_PCR_PID_SHIFT 0 +#define K1C_SFR_PCR_PID_WIDTH 8 +#define K1C_SFR_PCR_PID_WFXL_MASK _ULL(0xff) +#define K1C_SFR_PCR_PID_WFXL_CLEAR _ULL(0xff) +#define K1C_SFR_PCR_PID_WFXL_SET _ULL(0xff00000000) + +#define K1C_SFR_PCR_CID_MASK _ULL(0xff00) /* Cluster Identifier in system */ +#define K1C_SFR_PCR_CID_SHIFT 8 +#define K1C_SFR_PCR_CID_WIDTH 8 +#define K1C_SFR_PCR_CID_WFXL_MASK _ULL(0xff00) +#define K1C_SFR_PCR_CID_WFXL_CLEAR _ULL(0xff00) +#define K1C_SFR_PCR_CID_WFXL_SET _ULL(0xff0000000000) + +#define K1C_SFR_PCR_MID_MASK _ULL(0xff0000) /* MPPA Identifier */ +#define K1C_SFR_PCR_MID_SHIFT 16 +#define K1C_SFR_PCR_MID_WIDTH 8 +#define K1C_SFR_PCR_MID_WFXL_MASK _ULL(0xff0000) +#define K1C_SFR_PCR_MID_WFXL_CLEAR _ULL(0xff0000) +#define K1C_SFR_PCR_MID_WFXL_SET _ULL(0xff000000000000) + +#define K1C_SFR_PCR_CAR_MASK _ULL(0xf000000) /* Core Architecture Revision ID */ +#define K1C_SFR_PCR_CAR_SHIFT 24 +#define K1C_SFR_PCR_CAR_WIDTH 4 +#define K1C_SFR_PCR_CAR_WFXL_MASK _ULL(0xf000000) +#define K1C_SFR_PCR_CAR_WFXL_CLEAR _ULL(0xf000000) +#define K1C_SFR_PCR_CAR_WFXL_SET _ULL(0xf00000000000000) + +#define K1C_SFR_PCR_CMA_MASK _ULL(0xf0000000) /* Core Micro-Architecture Revision ID */ +#define K1C_SFR_PCR_CMA_SHIFT 28 +#define K1C_SFR_PCR_CMA_WIDTH 4 +#define K1C_SFR_PCR_CMA_WFXL_MASK _ULL(0xf0000000) +#define K1C_SFR_PCR_CMA_WFXL_CLEAR _ULL(0xf0000000) +#define K1C_SFR_PCR_CMA_WFXL_SET _ULL(0xf000000000000000) + +#define K1C_SFR_PCR_SV_MASK _ULL(0xff00000000) /* System-On-Chip Version */ +#define K1C_SFR_PCR_SV_SHIFT 32 +#define K1C_SFR_PCR_SV_WIDTH 8 +#define K1C_SFR_PCR_SV_WFXM_MASK _ULL(0xff00000000) +#define K1C_SFR_PCR_SV_WFXM_CLEAR _ULL(0xff) +#define K1C_SFR_PCR_SV_WFXM_SET _ULL(0xff00000000) + +#define K1C_SFR_PCR_ST_MASK _ULL(0xf0000000000) /* System-On-Chip Type */ +#define K1C_SFR_PCR_ST_SHIFT 40 +#define K1C_SFR_PCR_ST_WIDTH 4 +#define K1C_SFR_PCR_ST_WFXM_MASK _ULL(0xf0000000000) +#define K1C_SFR_PCR_ST_WFXM_CLEAR _ULL(0xf00) +#define K1C_SFR_PCR_ST_WFXM_SET _ULL(0xf0000000000) + +#define K1C_SFR_PCR_BM_MASK _ULL(0xff00000000000) /* Boot Mode */ +#define K1C_SFR_PCR_BM_SHIFT 44 +#define K1C_SFR_PCR_BM_WIDTH 8 +#define K1C_SFR_PCR_BM_WFXM_MASK _ULL(0xff00000000000) +#define K1C_SFR_PCR_BM_WFXM_CLEAR _ULL(0xff000) +#define K1C_SFR_PCR_BM_WFXM_SET _ULL(0xff00000000000) + +#define K1C_SFR_PCR_COE_MASK _ULL(0x10000000000000) /* COprocessor Enable */ +#define K1C_SFR_PCR_COE_SHIFT 52 +#define K1C_SFR_PCR_COE_WIDTH 1 +#define K1C_SFR_PCR_COE_WFXM_MASK _ULL(0x10000000000000) +#define K1C_SFR_PCR_COE_WFXM_CLEAR _ULL(0x100000) +#define K1C_SFR_PCR_COE_WFXM_SET _ULL(0x10000000000000) + +#define K1C_SFR_PCR_L1CE_MASK _ULL(0x20000000000000) /* L1 cache Coherency Enable */ +#define K1C_SFR_PCR_L1CE_SHIFT 53 +#define K1C_SFR_PCR_L1CE_WIDTH 1 +#define K1C_SFR_PCR_L1CE_WFXM_MASK _ULL(0x20000000000000) +#define K1C_SFR_PCR_L1CE_WFXM_CLEAR _ULL(0x200000) +#define K1C_SFR_PCR_L1CE_WFXM_SET _ULL(0x20000000000000) + +#define K1C_SFR_PCR_DSEM_MASK _ULL(0x40000000000000) /* Data Simple Ecc exception Mode */ +#define K1C_SFR_PCR_DSEM_SHIFT 54 +#define K1C_SFR_PCR_DSEM_WIDTH 1 +#define K1C_SFR_PCR_DSEM_WFXM_MASK _ULL(0x40000000000000) +#define K1C_SFR_PCR_DSEM_WFXM_CLEAR _ULL(0x400000) +#define K1C_SFR_PCR_DSEM_WFXM_SET _ULL(0x40000000000000) + +#define K1C_SFR_MMC_ASN_MASK _ULL(0x1ff) /* Address Space Number */ +#define K1C_SFR_MMC_ASN_SHIFT 0 +#define K1C_SFR_MMC_ASN_WIDTH 9 +#define K1C_SFR_MMC_ASN_WFXL_MASK _ULL(0x1ff) +#define K1C_SFR_MMC_ASN_WFXL_CLEAR _ULL(0x1ff) +#define K1C_SFR_MMC_ASN_WFXL_SET _ULL(0x1ff00000000) + +#define K1C_SFR_MMC_S_MASK _ULL(0x200) /* Speculative */ +#define K1C_SFR_MMC_S_SHIFT 9 +#define K1C_SFR_MMC_S_WIDTH 1 +#define K1C_SFR_MMC_S_WFXL_MASK _ULL(0x200) +#define K1C_SFR_MMC_S_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_MMC_S_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_MMC_SNE_MASK _ULL(0x4000) /* Speculative NOMAPPING Enable */ +#define K1C_SFR_MMC_SNE_SHIFT 14 +#define K1C_SFR_MMC_SNE_WIDTH 1 +#define K1C_SFR_MMC_SNE_WFXL_MASK _ULL(0x4000) +#define K1C_SFR_MMC_SNE_WFXL_CLEAR _ULL(0x4000) +#define K1C_SFR_MMC_SNE_WFXL_SET _ULL(0x400000000000) + +#define K1C_SFR_MMC_SPE_MASK _ULL(0x8000) /* Speculative PROTECTION Enable */ +#define K1C_SFR_MMC_SPE_SHIFT 15 +#define K1C_SFR_MMC_SPE_WIDTH 1 +#define K1C_SFR_MMC_SPE_WFXL_MASK _ULL(0x8000) +#define K1C_SFR_MMC_SPE_WFXL_CLEAR _ULL(0x8000) +#define K1C_SFR_MMC_SPE_WFXL_SET _ULL(0x800000000000) + +#define K1C_SFR_MMC_PTC_MASK _ULL(0x30000) /* Protection Trap Cause */ +#define K1C_SFR_MMC_PTC_SHIFT 16 +#define K1C_SFR_MMC_PTC_WIDTH 2 +#define K1C_SFR_MMC_PTC_WFXL_MASK _ULL(0x30000) +#define K1C_SFR_MMC_PTC_WFXL_CLEAR _ULL(0x30000) +#define K1C_SFR_MMC_PTC_WFXL_SET _ULL(0x3000000000000) + +#define K1C_SFR_MMC_SW_MASK _ULL(0x3c0000) /* Select Way */ +#define K1C_SFR_MMC_SW_SHIFT 18 +#define K1C_SFR_MMC_SW_WIDTH 4 +#define K1C_SFR_MMC_SW_WFXL_MASK _ULL(0x3c0000) +#define K1C_SFR_MMC_SW_WFXL_CLEAR _ULL(0x3c0000) +#define K1C_SFR_MMC_SW_WFXL_SET _ULL(0x3c000000000000) + +#define K1C_SFR_MMC_SS_MASK _ULL(0xfc00000) /* Select Set */ +#define K1C_SFR_MMC_SS_SHIFT 22 +#define K1C_SFR_MMC_SS_WIDTH 6 +#define K1C_SFR_MMC_SS_WFXL_MASK _ULL(0xfc00000) +#define K1C_SFR_MMC_SS_WFXL_CLEAR _ULL(0xfc00000) +#define K1C_SFR_MMC_SS_WFXL_SET _ULL(0xfc0000000000000) + +#define K1C_SFR_MMC_SB_MASK _ULL(0x10000000) /* Select Buffer */ +#define K1C_SFR_MMC_SB_SHIFT 28 +#define K1C_SFR_MMC_SB_WIDTH 1 +#define K1C_SFR_MMC_SB_WFXL_MASK _ULL(0x10000000) +#define K1C_SFR_MMC_SB_WFXL_CLEAR _ULL(0x10000000) +#define K1C_SFR_MMC_SB_WFXL_SET _ULL(0x1000000000000000) + +#define K1C_SFR_MMC_PAR_MASK _ULL(0x40000000) /* PARity error flag */ +#define K1C_SFR_MMC_PAR_SHIFT 30 +#define K1C_SFR_MMC_PAR_WIDTH 1 +#define K1C_SFR_MMC_PAR_WFXL_MASK _ULL(0x40000000) +#define K1C_SFR_MMC_PAR_WFXL_CLEAR _ULL(0x40000000) +#define K1C_SFR_MMC_PAR_WFXL_SET _ULL(0x4000000000000000) + +#define K1C_SFR_MMC_E_MASK _ULL(0x80000000) /* Error Flag */ +#define K1C_SFR_MMC_E_SHIFT 31 +#define K1C_SFR_MMC_E_WIDTH 1 +#define K1C_SFR_MMC_E_WFXL_MASK _ULL(0x80000000) +#define K1C_SFR_MMC_E_WFXL_CLEAR _ULL(0x80000000) +#define K1C_SFR_MMC_E_WFXL_SET _ULL(0x8000000000000000) + +#define K1C_SFR_TEL_ES_MASK _ULL(0x3) /* Entry Status */ +#define K1C_SFR_TEL_ES_SHIFT 0 +#define K1C_SFR_TEL_ES_WIDTH 2 +#define K1C_SFR_TEL_ES_WFXL_MASK _ULL(0x3) +#define K1C_SFR_TEL_ES_WFXL_CLEAR _ULL(0x3) +#define K1C_SFR_TEL_ES_WFXL_SET _ULL(0x300000000) + +#define K1C_SFR_TEL_CP_MASK _ULL(0xc) /* Cache Policy */ +#define K1C_SFR_TEL_CP_SHIFT 2 +#define K1C_SFR_TEL_CP_WIDTH 2 +#define K1C_SFR_TEL_CP_WFXL_MASK _ULL(0xc) +#define K1C_SFR_TEL_CP_WFXL_CLEAR _ULL(0xc) +#define K1C_SFR_TEL_CP_WFXL_SET _ULL(0xc00000000) + +#define K1C_SFR_TEL_PA_MASK _ULL(0xf0) /* Protection Attributes */ +#define K1C_SFR_TEL_PA_SHIFT 4 +#define K1C_SFR_TEL_PA_WIDTH 4 +#define K1C_SFR_TEL_PA_WFXL_MASK _ULL(0xf0) +#define K1C_SFR_TEL_PA_WFXL_CLEAR _ULL(0xf0) +#define K1C_SFR_TEL_PA_WFXL_SET _ULL(0xf000000000) + +#define K1C_SFR_TEL_PS_MASK _ULL(0xc00) /* Page Size */ +#define K1C_SFR_TEL_PS_SHIFT 10 +#define K1C_SFR_TEL_PS_WIDTH 2 +#define K1C_SFR_TEL_PS_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_TEL_PS_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_TEL_PS_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_TEL_FN_MASK _ULL(0xfffffff000) /* Frame Number */ +#define K1C_SFR_TEL_FN_SHIFT 12 +#define K1C_SFR_TEL_FN_WIDTH 28 +#define K1C_SFR_TEL_FN_WFXL_MASK _ULL(0xfffff000) +#define K1C_SFR_TEL_FN_WFXL_CLEAR _ULL(0xfffff000) +#define K1C_SFR_TEL_FN_WFXL_SET _ULL(0xfffff00000000000) +#define K1C_SFR_TEL_FN_WFXM_MASK _ULL(0xff00000000) +#define K1C_SFR_TEL_FN_WFXM_CLEAR _ULL(0xff) +#define K1C_SFR_TEL_FN_WFXM_SET _ULL(0xff00000000) + +#define K1C_SFR_TEH_ASN_MASK _ULL(0x1ff) /* Adress Space Number */ +#define K1C_SFR_TEH_ASN_SHIFT 0 +#define K1C_SFR_TEH_ASN_WIDTH 9 +#define K1C_SFR_TEH_ASN_WFXL_MASK _ULL(0x1ff) +#define K1C_SFR_TEH_ASN_WFXL_CLEAR _ULL(0x1ff) +#define K1C_SFR_TEH_ASN_WFXL_SET _ULL(0x1ff00000000) + +#define K1C_SFR_TEH_G_MASK _ULL(0x200) /* Global page indicator */ +#define K1C_SFR_TEH_G_SHIFT 9 +#define K1C_SFR_TEH_G_WIDTH 1 +#define K1C_SFR_TEH_G_WFXL_MASK _ULL(0x200) +#define K1C_SFR_TEH_G_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_TEH_G_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_TEH_VS_MASK _ULL(0xc00) /* Virtual Space */ +#define K1C_SFR_TEH_VS_SHIFT 10 +#define K1C_SFR_TEH_VS_WIDTH 2 +#define K1C_SFR_TEH_VS_WFXL_MASK _ULL(0xc00) +#define K1C_SFR_TEH_VS_WFXL_CLEAR _ULL(0xc00) +#define K1C_SFR_TEH_VS_WFXL_SET _ULL(0xc0000000000) + +#define K1C_SFR_TEH_PN_MASK _ULL(0x1fffffff000) /* Page Number */ +#define K1C_SFR_TEH_PN_SHIFT 12 +#define K1C_SFR_TEH_PN_WIDTH 29 +#define K1C_SFR_TEH_PN_WFXL_MASK _ULL(0xfffff000) +#define K1C_SFR_TEH_PN_WFXL_CLEAR _ULL(0xfffff000) +#define K1C_SFR_TEH_PN_WFXL_SET _ULL(0xfffff00000000000) +#define K1C_SFR_TEH_PN_WFXM_MASK _ULL(0x1ff00000000) +#define K1C_SFR_TEH_PN_WFXM_CLEAR _ULL(0x1ff) +#define K1C_SFR_TEH_PN_WFXM_SET _ULL(0x1ff00000000) + +#define K1C_SFR_DC_BE0_MASK _ULL(0x1) /* Breakpoint 0 Enable */ +#define K1C_SFR_DC_BE0_SHIFT 0 +#define K1C_SFR_DC_BE0_WIDTH 1 +#define K1C_SFR_DC_BE0_WFXL_MASK _ULL(0x1) +#define K1C_SFR_DC_BE0_WFXL_CLEAR _ULL(0x1) +#define K1C_SFR_DC_BE0_WFXL_SET _ULL(0x100000000) + +#define K1C_SFR_DC_BR0_MASK _ULL(0x7e) /* Breakpoint 0 Range */ +#define K1C_SFR_DC_BR0_SHIFT 1 +#define K1C_SFR_DC_BR0_WIDTH 6 +#define K1C_SFR_DC_BR0_WFXL_MASK _ULL(0x7e) +#define K1C_SFR_DC_BR0_WFXL_CLEAR _ULL(0x7e) +#define K1C_SFR_DC_BR0_WFXL_SET _ULL(0x7e00000000) + +#define K1C_SFR_DC_BE1_MASK _ULL(0x80) /* Breakpoint 1 Enable */ +#define K1C_SFR_DC_BE1_SHIFT 7 +#define K1C_SFR_DC_BE1_WIDTH 1 +#define K1C_SFR_DC_BE1_WFXL_MASK _ULL(0x80) +#define K1C_SFR_DC_BE1_WFXL_CLEAR _ULL(0x80) +#define K1C_SFR_DC_BE1_WFXL_SET _ULL(0x8000000000) + +#define K1C_SFR_DC_BR1_MASK _ULL(0x3f00) /* Breakpoint 1 Range */ +#define K1C_SFR_DC_BR1_SHIFT 8 +#define K1C_SFR_DC_BR1_WIDTH 6 +#define K1C_SFR_DC_BR1_WFXL_MASK _ULL(0x3f00) +#define K1C_SFR_DC_BR1_WFXL_CLEAR _ULL(0x3f00) +#define K1C_SFR_DC_BR1_WFXL_SET _ULL(0x3f0000000000) + +#define K1C_SFR_DC_WE0_MASK _ULL(0x4000) /* Watchpoint 0 Enable */ +#define K1C_SFR_DC_WE0_SHIFT 14 +#define K1C_SFR_DC_WE0_WIDTH 1 +#define K1C_SFR_DC_WE0_WFXL_MASK _ULL(0x4000) +#define K1C_SFR_DC_WE0_WFXL_CLEAR _ULL(0x4000) +#define K1C_SFR_DC_WE0_WFXL_SET _ULL(0x400000000000) + +#define K1C_SFR_DC_WR0_MASK _ULL(0x1f8000) /* Watchpoint 0 Range */ +#define K1C_SFR_DC_WR0_SHIFT 15 +#define K1C_SFR_DC_WR0_WIDTH 6 +#define K1C_SFR_DC_WR0_WFXL_MASK _ULL(0x1f8000) +#define K1C_SFR_DC_WR0_WFXL_CLEAR _ULL(0x1f8000) +#define K1C_SFR_DC_WR0_WFXL_SET _ULL(0x1f800000000000) + +#define K1C_SFR_DC_WE1_MASK _ULL(0x200000) /* Watchpoint 1 Enable */ +#define K1C_SFR_DC_WE1_SHIFT 21 +#define K1C_SFR_DC_WE1_WIDTH 1 +#define K1C_SFR_DC_WE1_WFXL_MASK _ULL(0x200000) +#define K1C_SFR_DC_WE1_WFXL_CLEAR _ULL(0x200000) +#define K1C_SFR_DC_WE1_WFXL_SET _ULL(0x20000000000000) + +#define K1C_SFR_DC_WR1_MASK _ULL(0xfc00000) /* Watchpoint 1 Range */ +#define K1C_SFR_DC_WR1_SHIFT 22 +#define K1C_SFR_DC_WR1_WIDTH 6 +#define K1C_SFR_DC_WR1_WFXL_MASK _ULL(0xfc00000) +#define K1C_SFR_DC_WR1_WFXL_CLEAR _ULL(0xfc00000) +#define K1C_SFR_DC_WR1_WFXL_SET _ULL(0xfc0000000000000) + +#define K1C_SFR_MES_PSE_MASK _ULL(0x1) /* Program Simple Ecc */ +#define K1C_SFR_MES_PSE_SHIFT 0 +#define K1C_SFR_MES_PSE_WIDTH 1 +#define K1C_SFR_MES_PSE_WFXL_MASK _ULL(0x1) +#define K1C_SFR_MES_PSE_WFXL_CLEAR _ULL(0x1) +#define K1C_SFR_MES_PSE_WFXL_SET _ULL(0x100000000) + +#define K1C_SFR_MES_PILSY_MASK _ULL(0x2) /* Program cache Invalidated Line following pSYs error. */ +#define K1C_SFR_MES_PILSY_SHIFT 1 +#define K1C_SFR_MES_PILSY_WIDTH 1 +#define K1C_SFR_MES_PILSY_WFXL_MASK _ULL(0x2) +#define K1C_SFR_MES_PILSY_WFXL_CLEAR _ULL(0x2) +#define K1C_SFR_MES_PILSY_WFXL_SET _ULL(0x200000000) + +#define K1C_SFR_MES_PILDE_MASK _ULL(0x4) /* Program cache Invalidated Line following pDEcc error. */ +#define K1C_SFR_MES_PILDE_SHIFT 2 +#define K1C_SFR_MES_PILDE_WIDTH 1 +#define K1C_SFR_MES_PILDE_WFXL_MASK _ULL(0x4) +#define K1C_SFR_MES_PILDE_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_MES_PILDE_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_MES_PILPA_MASK _ULL(0x8) /* Program cache Invalidated Line following pPArity error. */ +#define K1C_SFR_MES_PILPA_SHIFT 3 +#define K1C_SFR_MES_PILPA_WIDTH 1 +#define K1C_SFR_MES_PILPA_WFXL_MASK _ULL(0x8) +#define K1C_SFR_MES_PILPA_WFXL_CLEAR _ULL(0x8) +#define K1C_SFR_MES_PILPA_WFXL_SET _ULL(0x800000000) + +#define K1C_SFR_MES_DSE_MASK _ULL(0x10) /* Data Simple Ecc */ +#define K1C_SFR_MES_DSE_SHIFT 4 +#define K1C_SFR_MES_DSE_WIDTH 1 +#define K1C_SFR_MES_DSE_WFXL_MASK _ULL(0x10) +#define K1C_SFR_MES_DSE_WFXL_CLEAR _ULL(0x10) +#define K1C_SFR_MES_DSE_WFXL_SET _ULL(0x1000000000) + +#define K1C_SFR_MES_DILSY_MASK _ULL(0x20) /* Data cache Invalidated Line following dSYs error. */ +#define K1C_SFR_MES_DILSY_SHIFT 5 +#define K1C_SFR_MES_DILSY_WIDTH 1 +#define K1C_SFR_MES_DILSY_WFXL_MASK _ULL(0x20) +#define K1C_SFR_MES_DILSY_WFXL_CLEAR _ULL(0x20) +#define K1C_SFR_MES_DILSY_WFXL_SET _ULL(0x2000000000) + +#define K1C_SFR_MES_DILDE_MASK _ULL(0x40) /* Data cache Invalidated Line following dDEcc error. */ +#define K1C_SFR_MES_DILDE_SHIFT 6 +#define K1C_SFR_MES_DILDE_WIDTH 1 +#define K1C_SFR_MES_DILDE_WFXL_MASK _ULL(0x40) +#define K1C_SFR_MES_DILDE_WFXL_CLEAR _ULL(0x40) +#define K1C_SFR_MES_DILDE_WFXL_SET _ULL(0x4000000000) + +#define K1C_SFR_MES_DILPA_MASK _ULL(0x80) /* Data cache Invalidated Line following dPArity error. */ +#define K1C_SFR_MES_DILPA_SHIFT 7 +#define K1C_SFR_MES_DILPA_WIDTH 1 +#define K1C_SFR_MES_DILPA_WFXL_MASK _ULL(0x80) +#define K1C_SFR_MES_DILPA_WFXL_CLEAR _ULL(0x80) +#define K1C_SFR_MES_DILPA_WFXL_SET _ULL(0x8000000000) + +#define K1C_SFR_MES_DDEE_MASK _ULL(0x100) /* Data DEcc Error. */ +#define K1C_SFR_MES_DDEE_SHIFT 8 +#define K1C_SFR_MES_DDEE_WIDTH 1 +#define K1C_SFR_MES_DDEE_WFXL_MASK _ULL(0x100) +#define K1C_SFR_MES_DDEE_WFXL_CLEAR _ULL(0x100) +#define K1C_SFR_MES_DDEE_WFXL_SET _ULL(0x10000000000) + +#define K1C_SFR_MES_DSYE_MASK _ULL(0x200) /* Data dSYs Error. */ +#define K1C_SFR_MES_DSYE_SHIFT 9 +#define K1C_SFR_MES_DSYE_WIDTH 1 +#define K1C_SFR_MES_DSYE_WFXL_MASK _ULL(0x200) +#define K1C_SFR_MES_DSYE_WFXL_CLEAR _ULL(0x200) +#define K1C_SFR_MES_DSYE_WFXL_SET _ULL(0x20000000000) + +#define K1C_SFR_WS_WU0_MASK _ULL(0x1) /* Wake-Up 0 */ +#define K1C_SFR_WS_WU0_SHIFT 0 +#define K1C_SFR_WS_WU0_WIDTH 1 +#define K1C_SFR_WS_WU0_WFXL_MASK _ULL(0x1) +#define K1C_SFR_WS_WU0_WFXL_CLEAR _ULL(0x1) +#define K1C_SFR_WS_WU0_WFXL_SET _ULL(0x100000000) + +#define K1C_SFR_WS_WU1_MASK _ULL(0x2) /* Wake-Up 1 */ +#define K1C_SFR_WS_WU1_SHIFT 1 +#define K1C_SFR_WS_WU1_WIDTH 1 +#define K1C_SFR_WS_WU1_WFXL_MASK _ULL(0x2) +#define K1C_SFR_WS_WU1_WFXL_CLEAR _ULL(0x2) +#define K1C_SFR_WS_WU1_WFXL_SET _ULL(0x200000000) + +#define K1C_SFR_WS_WU2_MASK _ULL(0x4) /* Wake-Up 2 */ +#define K1C_SFR_WS_WU2_SHIFT 2 +#define K1C_SFR_WS_WU2_WIDTH 1 +#define K1C_SFR_WS_WU2_WFXL_MASK _ULL(0x4) +#define K1C_SFR_WS_WU2_WFXL_CLEAR _ULL(0x4) +#define K1C_SFR_WS_WU2_WFXL_SET _ULL(0x400000000) + +#define K1C_SFR_IPE_FE_MASK _ULL(0xffff) /* Forward Events */ +#define K1C_SFR_IPE_FE_SHIFT 0 +#define K1C_SFR_IPE_FE_WIDTH 16 +#define K1C_SFR_IPE_FE_WFXL_MASK _ULL(0xffff) +#define K1C_SFR_IPE_FE_WFXL_CLEAR _ULL(0xffff) +#define K1C_SFR_IPE_FE_WFXL_SET _ULL(0xffff00000000) + +#define K1C_SFR_IPE_BE_MASK _ULL(0xffff0000) /* Backward Events */ +#define K1C_SFR_IPE_BE_SHIFT 16 +#define K1C_SFR_IPE_BE_WIDTH 16 +#define K1C_SFR_IPE_BE_WFXL_MASK _ULL(0xffff0000) +#define K1C_SFR_IPE_BE_WFXL_CLEAR _ULL(0xffff0000) +#define K1C_SFR_IPE_BE_WFXL_SET _ULL(0xffff000000000000) + +#define K1C_SFR_IPE_FM_MASK _ULL(0xffff00000000) /* Forward Mode */ +#define K1C_SFR_IPE_FM_SHIFT 32 +#define K1C_SFR_IPE_FM_WIDTH 16 +#define K1C_SFR_IPE_FM_WFXM_MASK _ULL(0xffff00000000) +#define K1C_SFR_IPE_FM_WFXM_CLEAR _ULL(0xffff) +#define K1C_SFR_IPE_FM_WFXM_SET _ULL(0xffff00000000) + +#define K1C_SFR_IPE_BM_MASK _ULL(0xffff000000000000) /* Backward Modes */ +#define K1C_SFR_IPE_BM_SHIFT 48 +#define K1C_SFR_IPE_BM_WIDTH 16 +#define K1C_SFR_IPE_BM_WFXM_MASK _ULL(0xffff000000000000) +#define K1C_SFR_IPE_BM_WFXM_CLEAR _ULL(0xffff0000) +#define K1C_SFR_IPE_BM_WFXM_SET _ULL(0xffff000000000000) + +#endif/*_ASM_K1C_SFR_DEFS_H */ -- 2.15.0.276.g89ea799 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/5] k1c: Add support for device tree 2020-01-15 10:26 [PATCH 0/5] Add support for Kalray k1c core Clement Leger 2020-01-15 10:26 ` [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support Clement Leger 2020-01-15 10:26 ` [PATCH 2/5] k1c: Add processor definitions Clement Leger @ 2020-01-15 10:26 ` Clement Leger 2020-01-15 10:26 ` [PATCH 4/5] clocksource: k1c: Add k1c clocksource support Clement Leger ` (3 subsequent siblings) 6 siblings, 0 replies; 22+ messages in thread From: Clement Leger @ 2020-01-15 10:26 UTC (permalink / raw) To: barebox, Sascha Hauer; +Cc: Clement Leger Add dts folder with minimal device tree for kalray K200 board. Signed-off-by: Clement Leger <cleger@kalray.eu> --- arch/k1c/Kconfig | 20 ++++++++++ arch/k1c/Makefile | 1 + arch/k1c/dts/Makefile | 13 +++++++ arch/k1c/dts/k200.dts | 105 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 139 insertions(+) create mode 100644 arch/k1c/dts/Makefile create mode 100644 arch/k1c/dts/k200.dts diff --git a/arch/k1c/Kconfig b/arch/k1c/Kconfig index f0f9d1728..cf5c7beff 100644 --- a/arch/k1c/Kconfig +++ b/arch/k1c/Kconfig @@ -43,3 +43,23 @@ config MALLOC_SIZE default 0x800000 prompt "malloc area size" endmenu + +menu "Board configuration" + +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + +choice + prompt "Select your board" + +config BOARD_K200 + bool "K200 Network card" + +endchoice + +endmenu diff --git a/arch/k1c/Makefile b/arch/k1c/Makefile index 10852406f..6eb28d1b2 100644 --- a/arch/k1c/Makefile +++ b/arch/k1c/Makefile @@ -26,6 +26,7 @@ PHONY += maketools common-y += arch/k1c/lib/ common-y += arch/k1c/cpu/ +common-$(CONFIG_OFTREE) += arch/k1c/dts/ lds-y += arch/k1c/cpu/barebox.lds diff --git a/arch/k1c/dts/Makefile b/arch/k1c/dts/Makefile new file mode 100644 index 000000000..9d5e94ae1 --- /dev/null +++ b/arch/k1c/dts/Makefile @@ -0,0 +1,13 @@ +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +ifneq ($(BUILTIN_DTB),) +obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o +endif + +obj-dtb-$(CONFIG_BOARD_K200) += k200.dtb.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts diff --git a/arch/k1c/dts/k200.dts b/arch/k1c/dts/k200.dts new file mode 100644 index 000000000..fc9a21ad4 --- /dev/null +++ b/arch/k1c/dts/k200.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray, Inc. + */ + +/dts-v1/; + +/ { + model = "KONIC 200 (K200)"; + compatible = "kalray,board-k200"; + + #address-cells = <2>; + #size-cells = <2>; + + /* Standard nodes (choosen, cpus, memory, etc) */ + chosen { + bootargs = "earlycon norandmaps console=ttyS0"; + stdout-path = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "kalray,k1c-pe"; + reg = <0>; + clocks = <&core_clk>; + clock-names = "cpu"; + }; + + }; + + clocks { + ref_clk: ref_clk@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* 100 MHz clock */ + clock-frequency = <100000000>; + }; + + core_clk: core_clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* 1 GHz clock */ + clock-frequency = <1000000000>; + }; + }; + + ddr: memory@100000000 { + device_type = "memory"; + /* Declare 4G of DDR starting at 4G */ + reg = <0x1 0x00000000 0x1 0x00000000>; + }; + + smem: memory@0 { + device_type = "memory"; + /* 4M of SMEM starting at @0 */ + reg = <0x0 0x0 0x0 0x400000>; + }; + + core_timer { + compatible = "kalray,k1c-core-timer"; + clocks = <&core_clk>; + }; + + core_watchdog { + compatible = "kalray,k1c-core-watchdog"; + clocks = <&core_clk>; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + + pmx_gpio0: pinmux@20230008 { + compatible = "pinctrl-single"; + reg = <0x0 0x20230008 0x0 0x4>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x1>; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,bits = <0x00 0x00000003 0x00000003>; + }; + }; + + serial0: uart0@20210000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20210000 0x0 0x100>; + clocks = <&ref_clk>; + reg-io-width = <4>; + reg-shift = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + }; + }; +}; -- 2.15.0.276.g89ea799 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 4/5] clocksource: k1c: Add k1c clocksource support 2020-01-15 10:26 [PATCH 0/5] Add support for Kalray k1c core Clement Leger ` (2 preceding siblings ...) 2020-01-15 10:26 ` [PATCH 3/5] k1c: Add support for device tree Clement Leger @ 2020-01-15 10:26 ` Clement Leger 2020-01-15 10:26 ` [PATCH 5/5] watchdog: k1c: Add k1c watchdog support Clement Leger ` (2 subsequent siblings) 6 siblings, 0 replies; 22+ messages in thread From: Clement Leger @ 2020-01-15 10:26 UTC (permalink / raw) To: barebox, Sascha Hauer; +Cc: Clement Leger Add a clocksource for k1c architecture based on core performance counter. This performance counter is configured to count cycles and as such can be used to be a clocksource. Signed-off-by: Clement Leger <cleger@kalray.eu> --- arch/k1c/configs/generic_defconfig | 1 + drivers/clocksource/Kconfig | 4 +++ drivers/clocksource/Makefile | 1 + drivers/clocksource/k1c_timer.c | 59 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 65 insertions(+) create mode 100644 drivers/clocksource/k1c_timer.c diff --git a/arch/k1c/configs/generic_defconfig b/arch/k1c/configs/generic_defconfig index 535f1cf8b..0821030f6 100644 --- a/arch/k1c/configs/generic_defconfig +++ b/arch/k1c/configs/generic_defconfig @@ -1,6 +1,7 @@ CONFIG_AUTO_COMPLETE=y CONFIG_BAUDRATE=115200 # CONFIG_BOOTM is not set +CONFIG_CLOCKSOURCE_K1C=y CONFIG_CMD_CMP=y CONFIG_CMD_OF_DUMP=y CONFIG_CMD_POWEROFF=y diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 44a6cef6f..12ff00be9 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -47,6 +47,10 @@ config CLOCKSOURCE_EFI_X86 bool "EFI X86 HW driver" depends on EFI_BOOTUP && X86 +config CLOCKSOURCE_K1C + bool "K1C core timer clocksource" + depends on K1C + config CLOCKSOURCE_MVEBU bool depends on ARCH_MVEBU diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index f8ff83d60..678b587dc 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_CLOCKSOURCE_CLPS711X) += clps711x.o obj-$(CONFIG_CLOCKSOURCE_DIGIC) += digic.o obj-$(CONFIG_CLOCKSOURCE_EFI) += efi.o obj-$(CONFIG_CLOCKSOURCE_EFI_X86) += efi_x86.o +obj-$(CONFIG_CLOCKSOURCE_K1C) += k1c_timer.o obj-$(CONFIG_CLOCKSOURCE_MVEBU) += mvebu.o obj-$(CONFIG_CLOCKSOURCE_NOMADIK) += nomadik.o obj-$(CONFIG_CLOCKSOURCE_ORION) += orion.o diff --git a/drivers/clocksource/k1c_timer.c b/drivers/clocksource/k1c_timer.c new file mode 100644 index 000000000..af5f73a66 --- /dev/null +++ b/drivers/clocksource/k1c_timer.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2018 Kalray Inc. + */ + +#include <common.h> +#include <clock.h> +#include <init.h> + +#include <linux/clk.h> +#include <linux/err.h> + +#include <asm/sfr.h> + +static uint64_t k1c_pm_read(void) +{ + return k1c_sfr_get(K1C_SFR_PM0); +} + +static struct clocksource k1c_clksrc = { + .read = k1c_pm_read, + .mask = CLOCKSOURCE_MASK(64), + .shift = 0, +}; + +static int k1c_timer_probe(struct device_d *dev) +{ + struct clk *clk; + uint32_t clk_freq; + struct device_node *np = dev->device_node; + + /* Get clock frequency */ + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); + return PTR_ERR(clk); + } + + clk_freq = clk_get_rate(clk); + clk_put(clk); + + /* Init clocksource */ + k1c_clksrc.mult = clocksource_hz2mult(clk_freq, k1c_clksrc.shift); + + return init_clock(&k1c_clksrc); +} + +static struct of_device_id k1c_timer_dt_ids[] = { + { .compatible = "kalray,k1c-core-timer", }, + { } +}; + +static struct driver_d k1c_timer_driver = { + .name = "k1c-timer", + .probe = k1c_timer_probe, + .of_compatible = DRV_OF_COMPAT(k1c_timer_dt_ids), +}; + +device_platform_driver(k1c_timer_driver); -- 2.15.0.276.g89ea799 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 5/5] watchdog: k1c: Add k1c watchdog support 2020-01-15 10:26 [PATCH 0/5] Add support for Kalray k1c core Clement Leger ` (3 preceding siblings ...) 2020-01-15 10:26 ` [PATCH 4/5] clocksource: k1c: Add k1c clocksource support Clement Leger @ 2020-01-15 10:26 ` Clement Leger 2020-01-20 15:10 ` Ahmad Fatoum 2020-01-16 8:25 ` [PATCH 0/5] Add support for Kalray k1c core Sascha Hauer 2020-01-16 9:49 ` Roland Hieber 6 siblings, 1 reply; 22+ messages in thread From: Clement Leger @ 2020-01-15 10:26 UTC (permalink / raw) To: barebox, Sascha Hauer; +Cc: Clement Leger Add a watchdog for k1c architecture based on core watchdog. Signed-off-by: Clement Leger <cleger@kalray.eu> --- arch/k1c/configs/generic_defconfig | 3 + drivers/watchdog/Kconfig | 7 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/k1c_wdt.c | 126 +++++++++++++++++++++++++++++++++++++ 4 files changed, 137 insertions(+) create mode 100644 drivers/watchdog/k1c_wdt.c diff --git a/arch/k1c/configs/generic_defconfig b/arch/k1c/configs/generic_defconfig index 0821030f6..6c8d676df 100644 --- a/arch/k1c/configs/generic_defconfig +++ b/arch/k1c/configs/generic_defconfig @@ -5,6 +5,9 @@ CONFIG_CLOCKSOURCE_K1C=y CONFIG_CMD_CMP=y CONFIG_CMD_OF_DUMP=y CONFIG_CMD_POWEROFF=y +CONFIG_CMD_WD=y CONFIG_CONSOLE_RATP=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_PINCTRL_SINGLE=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_K1C=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 45dd41a2a..17a850de6 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -70,6 +70,13 @@ config WATCHDOG_ORION help Add support for watchdog on the Marvall Armada XP +config WATCHDOG_K1C + bool "K1C Core watchdog" + select RESET_CONTROLLER + depends on K1C + help + Add support for the K1C core watchdog. + config WATCHDOG_BCM2835 bool "Watchdog for BCM283x SoCs" depends on ARCH_BCM283X diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 63efc2a87..bbf5e8767 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_WATCHDOG_DW) += dw_wdt.o obj-$(CONFIG_WATCHDOG_JZ4740) += jz4740.o obj-$(CONFIG_WATCHDOG_IMX_RESET_SOURCE) += imxwd.o obj-$(CONFIG_WATCHDOG_IMX) += imxwd.o +obj-$(CONFIG_WATCHDOG_K1C) += k1c_wdt.o obj-$(CONFIG_WATCHDOG_ORION) += orion_wdt.o obj-$(CONFIG_ARCH_BCM283X) += bcm2835_wdt.o obj-$(CONFIG_RAVE_SP_WATCHDOG) += rave-sp-wdt.o diff --git a/drivers/watchdog/k1c_wdt.c b/drivers/watchdog/k1c_wdt.c new file mode 100644 index 000000000..23b6cbf33 --- /dev/null +++ b/drivers/watchdog/k1c_wdt.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2018 Kalray Inc. + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <of.h> +#include <restart.h> +#include <watchdog.h> + +#include <linux/clk.h> +#include <linux/err.h> + +#include <asm/sfr.h> + +#define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) + +struct k1c_wdt { + uint64_t clk_rate; + struct watchdog wdd; + struct restart_handler restart; + struct reset_control *rst; +}; + +static void k1c_watchdog_disable(void) +{ + k1c_sfr_clear_bit(K1C_SFR_TCR, K1C_SFR_TCR_WUI_SHIFT); + k1c_sfr_clear_bit(K1C_SFR_TCR, K1C_SFR_TCR_WCE_SHIFT); +} + +static int k1c_wdt_set_timeout(struct watchdog *wdd, unsigned int timeout) +{ + struct k1c_wdt *wdt = container_of(wdd, struct k1c_wdt, wdd); + uint64_t cycle_timeout = wdt->clk_rate * timeout; + + /* Disable watchdog */ + if (timeout == 0) { + k1c_watchdog_disable(); + return 0; + } + + k1c_sfr_set(K1C_SFR_WDV, cycle_timeout); + k1c_sfr_set(K1C_SFR_WDR, 0); + + /* Start watchdog counting */ + k1c_sfr_set_bit(K1C_SFR_TCR, K1C_SFR_TCR_WUI_SHIFT); + k1c_sfr_set_bit(K1C_SFR_TCR, K1C_SFR_TCR_WCE_SHIFT); + + return 0; +} + +static void __noreturn k1c_wdt_restart_handle(struct restart_handler *rst) +{ + struct k1c_wdt *k1c_wdt; + + k1c_wdt = container_of(rst, struct k1c_wdt, restart); + + k1c_wdt->wdd.set_timeout(&k1c_wdt->wdd, 1); + + mdelay(1000); + + hang(); +} + +static int count; + +static int k1c_wdt_drv_probe(struct device_d *dev) +{ + struct watchdog *wdd; + struct clk *clk; + struct k1c_wdt *k1c_wdt; + int ret; + + if (count != 0) { + dev_warn(dev, "Tried to register core watchdog twice\n"); + return -EINVAL; + } + count++; + + k1c_wdt = xzalloc(sizeof(*k1c_wdt)); + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + k1c_wdt->clk_rate = clk_get_rate(clk); + clk_put(clk); + + wdd = &k1c_wdt->wdd; + wdd->name = "k1c_wdt"; + wdd->hwdev = dev; + wdd->set_timeout = k1c_wdt_set_timeout; + + /* Be sure that interrupt is disabled */ + k1c_sfr_clear_bit(K1C_SFR_TCR, K1C_SFR_TCR_WIE_SHIFT); + + k1c_watchdog_disable(); + + ret = watchdog_register(wdd); + if (ret) + return -EINVAL; + + k1c_wdt->restart.name = "k1c_wdt"; + k1c_wdt->restart.priority = 50; + k1c_wdt->restart.restart = k1c_wdt_restart_handle; + + ret = restart_handler_register(&k1c_wdt->restart); + if (ret) + dev_warn(dev, "cannot register restart handler\n"); + + return 0; + +} + +static struct of_device_id k1c_wdt_of_match[] = { + { .compatible = "kalray,k1c-core-watchdog", }, + { /* sentinel */ } +}; + +static struct driver_d k1c_wdt_driver = { + .name = "k1c-wdt", + .probe = k1c_wdt_drv_probe, + .of_compatible = DRV_OF_COMPAT(k1c_wdt_of_match), +}; +device_platform_driver(k1c_wdt_driver); -- 2.15.0.276.g89ea799 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 5/5] watchdog: k1c: Add k1c watchdog support 2020-01-15 10:26 ` [PATCH 5/5] watchdog: k1c: Add k1c watchdog support Clement Leger @ 2020-01-20 15:10 ` Ahmad Fatoum 2020-01-20 16:08 ` Clément Leger 0 siblings, 1 reply; 22+ messages in thread From: Ahmad Fatoum @ 2020-01-20 15:10 UTC (permalink / raw) To: barebox On 1/15/20 11:26 AM, Clement Leger wrote: > Add a watchdog for k1c architecture based on core watchdog. > > Signed-off-by: Clement Leger <cleger@kalray.eu> > --- > arch/k1c/configs/generic_defconfig | 3 + > drivers/watchdog/Kconfig | 7 +++ > drivers/watchdog/Makefile | 1 + > drivers/watchdog/k1c_wdt.c | 126 +++++++++++++++++++++++++++++++++++++ > 4 files changed, 137 insertions(+) > create mode 100644 drivers/watchdog/k1c_wdt.c > > diff --git a/arch/k1c/configs/generic_defconfig b/arch/k1c/configs/generic_defconfig > index 0821030f6..6c8d676df 100644 > --- a/arch/k1c/configs/generic_defconfig > +++ b/arch/k1c/configs/generic_defconfig > @@ -5,6 +5,9 @@ CONFIG_CLOCKSOURCE_K1C=y > CONFIG_CMD_CMP=y > CONFIG_CMD_OF_DUMP=y > CONFIG_CMD_POWEROFF=y > +CONFIG_CMD_WD=y > CONFIG_CONSOLE_RATP=y > CONFIG_DRIVER_SERIAL_NS16550=y > CONFIG_PINCTRL_SINGLE=y > +CONFIG_WATCHDOG=y > +CONFIG_WATCHDOG_K1C=y > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index 45dd41a2a..17a850de6 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -70,6 +70,13 @@ config WATCHDOG_ORION > help > Add support for watchdog on the Marvall Armada XP > > +config WATCHDOG_K1C > + bool "K1C Core watchdog" > + select RESET_CONTROLLER This seems only used for struct reset_control *rst, which you don't use anywhere. > + depends on K1C > + help > + Add support for the K1C core watchdog. > + > config WATCHDOG_BCM2835 > bool "Watchdog for BCM283x SoCs" > depends on ARCH_BCM283X > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile > index 63efc2a87..bbf5e8767 100644 > --- a/drivers/watchdog/Makefile > +++ b/drivers/watchdog/Makefile > @@ -8,6 +8,7 @@ obj-$(CONFIG_WATCHDOG_DW) += dw_wdt.o > obj-$(CONFIG_WATCHDOG_JZ4740) += jz4740.o > obj-$(CONFIG_WATCHDOG_IMX_RESET_SOURCE) += imxwd.o > obj-$(CONFIG_WATCHDOG_IMX) += imxwd.o > +obj-$(CONFIG_WATCHDOG_K1C) += k1c_wdt.o > obj-$(CONFIG_WATCHDOG_ORION) += orion_wdt.o > obj-$(CONFIG_ARCH_BCM283X) += bcm2835_wdt.o > obj-$(CONFIG_RAVE_SP_WATCHDOG) += rave-sp-wdt.o > diff --git a/drivers/watchdog/k1c_wdt.c b/drivers/watchdog/k1c_wdt.c > new file mode 100644 > index 000000000..23b6cbf33 > --- /dev/null > +++ b/drivers/watchdog/k1c_wdt.c > @@ -0,0 +1,126 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright (C) 2018 Kalray Inc. > + */ > + > +#include <common.h> > +#include <init.h> > +#include <io.h> > +#include <of.h> > +#include <restart.h> > +#include <watchdog.h> > + > +#include <linux/clk.h> > +#include <linux/err.h> > + > +#include <asm/sfr.h> > + > +#define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) used no where > + > +struct k1c_wdt { > + uint64_t clk_rate; > + struct watchdog wdd; > + struct restart_handler restart; > + struct reset_control *rst; > +}; > + > +static void k1c_watchdog_disable(void) > +{ > + k1c_sfr_clear_bit(K1C_SFR_TCR, K1C_SFR_TCR_WUI_SHIFT); > + k1c_sfr_clear_bit(K1C_SFR_TCR, K1C_SFR_TCR_WCE_SHIFT); > +} > + > +static int k1c_wdt_set_timeout(struct watchdog *wdd, unsigned int timeout) > +{ > + struct k1c_wdt *wdt = container_of(wdd, struct k1c_wdt, wdd); > + uint64_t cycle_timeout = wdt->clk_rate * timeout; > + > + /* Disable watchdog */ > + if (timeout == 0) { > + k1c_watchdog_disable(); > + return 0; > + } > + > + k1c_sfr_set(K1C_SFR_WDV, cycle_timeout); > + k1c_sfr_set(K1C_SFR_WDR, 0); > + > + /* Start watchdog counting */ > + k1c_sfr_set_bit(K1C_SFR_TCR, K1C_SFR_TCR_WUI_SHIFT); > + k1c_sfr_set_bit(K1C_SFR_TCR, K1C_SFR_TCR_WCE_SHIFT); > + > + return 0; > +} > + > +static void __noreturn k1c_wdt_restart_handle(struct restart_handler *rst) > +{ > + struct k1c_wdt *k1c_wdt; > + > + k1c_wdt = container_of(rst, struct k1c_wdt, restart); > + > + k1c_wdt->wdd.set_timeout(&k1c_wdt->wdd, 1); Do you do the same under Linux as well? This means you can't differentiate between watchdog and normal resets. > + > + mdelay(1000); > + > + hang(); > +} > + > +static int count; > + > +static int k1c_wdt_drv_probe(struct device_d *dev) > +{ > + struct watchdog *wdd; > + struct clk *clk; > + struct k1c_wdt *k1c_wdt; > + int ret; > + > + if (count != 0) { > + dev_warn(dev, "Tried to register core watchdog twice\n"); > + return -EINVAL; > + } > + count++; > + > + k1c_wdt = xzalloc(sizeof(*k1c_wdt)); > + clk = clk_get(dev, NULL); > + if (IS_ERR(clk)) > + return PTR_ERR(clk); > + > + k1c_wdt->clk_rate = clk_get_rate(clk); > + clk_put(clk); > + > + wdd = &k1c_wdt->wdd; > + wdd->name = "k1c_wdt"; > + wdd->hwdev = dev; > + wdd->set_timeout = k1c_wdt_set_timeout; > + > + /* Be sure that interrupt is disabled */ > + k1c_sfr_clear_bit(K1C_SFR_TCR, K1C_SFR_TCR_WIE_SHIFT); > + > + k1c_watchdog_disable(); > + > + ret = watchdog_register(wdd); > + if (ret) > + return -EINVAL; > + > + k1c_wdt->restart.name = "k1c_wdt"; > + k1c_wdt->restart.priority = 50; Maybe add a comment on why you set a lower than default priority? > + k1c_wdt->restart.restart = k1c_wdt_restart_handle; > + > + ret = restart_handler_register(&k1c_wdt->restart); > + if (ret) > + dev_warn(dev, "cannot register restart handler\n"); > + > + return 0; > + > +} > + > +static struct of_device_id k1c_wdt_of_match[] = { > + { .compatible = "kalray,k1c-core-watchdog", }, > + { /* sentinel */ } > +}; > + > +static struct driver_d k1c_wdt_driver = { > + .name = "k1c-wdt", > + .probe = k1c_wdt_drv_probe, > + .of_compatible = DRV_OF_COMPAT(k1c_wdt_of_match), > +}; > +device_platform_driver(k1c_wdt_driver); > -- Pengutronix e.K. | | Steuerwalder Str. 21 | https://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 5/5] watchdog: k1c: Add k1c watchdog support 2020-01-20 15:10 ` Ahmad Fatoum @ 2020-01-20 16:08 ` Clément Leger 0 siblings, 0 replies; 22+ messages in thread From: Clément Leger @ 2020-01-20 16:08 UTC (permalink / raw) To: Ahmad Fatoum; +Cc: Barebox List Hi Ahmad, ----- On 20 Jan, 2020, at 16:10, Ahmad Fatoum a.fatoum@pengutronix.de wrote: > On 1/15/20 11:26 AM, Clement Leger wrote: >> Add a watchdog for k1c architecture based on core watchdog. >> >> Signed-off-by: Clement Leger <cleger@kalray.eu> >> --- >> arch/k1c/configs/generic_defconfig | 3 + >> drivers/watchdog/Kconfig | 7 +++ >> drivers/watchdog/Makefile | 1 + >> drivers/watchdog/k1c_wdt.c | 126 +++++++++++++++++++++++++++++++++++++ >> 4 files changed, 137 insertions(+) >> create mode 100644 drivers/watchdog/k1c_wdt.c >> >> diff --git a/arch/k1c/configs/generic_defconfig >> b/arch/k1c/configs/generic_defconfig >> index 0821030f6..6c8d676df 100644 >> --- a/arch/k1c/configs/generic_defconfig >> +++ b/arch/k1c/configs/generic_defconfig >> @@ -5,6 +5,9 @@ CONFIG_CLOCKSOURCE_K1C=y >> CONFIG_CMD_CMP=y >> CONFIG_CMD_OF_DUMP=y >> CONFIG_CMD_POWEROFF=y >> +CONFIG_CMD_WD=y >> CONFIG_CONSOLE_RATP=y >> CONFIG_DRIVER_SERIAL_NS16550=y >> CONFIG_PINCTRL_SINGLE=y >> +CONFIG_WATCHDOG=y >> +CONFIG_WATCHDOG_K1C=y >> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig >> index 45dd41a2a..17a850de6 100644 >> --- a/drivers/watchdog/Kconfig >> +++ b/drivers/watchdog/Kconfig >> @@ -70,6 +70,13 @@ config WATCHDOG_ORION >> help >> Add support for watchdog on the Marvall Armada XP >> >> +config WATCHDOG_K1C >> + bool "K1C Core watchdog" >> + select RESET_CONTROLLER > > This seems only used for struct reset_control *rst, which you > don't use anywhere. Indeed. > >> + depends on K1C >> + help >> + Add support for the K1C core watchdog. >> + >> config WATCHDOG_BCM2835 >> bool "Watchdog for BCM283x SoCs" >> depends on ARCH_BCM283X >> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile >> index 63efc2a87..bbf5e8767 100644 >> --- a/drivers/watchdog/Makefile >> +++ b/drivers/watchdog/Makefile >> @@ -8,6 +8,7 @@ obj-$(CONFIG_WATCHDOG_DW) += dw_wdt.o >> obj-$(CONFIG_WATCHDOG_JZ4740) += jz4740.o >> obj-$(CONFIG_WATCHDOG_IMX_RESET_SOURCE) += imxwd.o >> obj-$(CONFIG_WATCHDOG_IMX) += imxwd.o >> +obj-$(CONFIG_WATCHDOG_K1C) += k1c_wdt.o >> obj-$(CONFIG_WATCHDOG_ORION) += orion_wdt.o >> obj-$(CONFIG_ARCH_BCM283X) += bcm2835_wdt.o >> obj-$(CONFIG_RAVE_SP_WATCHDOG) += rave-sp-wdt.o >> diff --git a/drivers/watchdog/k1c_wdt.c b/drivers/watchdog/k1c_wdt.c >> new file mode 100644 >> index 000000000..23b6cbf33 >> --- /dev/null >> +++ b/drivers/watchdog/k1c_wdt.c >> @@ -0,0 +1,126 @@ >> +// SPDX-License-Identifier: GPL-2.0-or-later >> +/* >> + * Copyright (C) 2018 Kalray Inc. >> + */ >> + >> +#include <common.h> >> +#include <init.h> >> +#include <io.h> >> +#include <of.h> >> +#include <restart.h> >> +#include <watchdog.h> >> + >> +#include <linux/clk.h> >> +#include <linux/err.h> >> + >> +#include <asm/sfr.h> >> + >> +#define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) > > used no where Yes > >> + >> +struct k1c_wdt { >> + uint64_t clk_rate; >> + struct watchdog wdd; >> + struct restart_handler restart; >> + struct reset_control *rst; >> +}; >> + >> +static void k1c_watchdog_disable(void) >> +{ >> + k1c_sfr_clear_bit(K1C_SFR_TCR, K1C_SFR_TCR_WUI_SHIFT); >> + k1c_sfr_clear_bit(K1C_SFR_TCR, K1C_SFR_TCR_WCE_SHIFT); >> +} >> + >> +static int k1c_wdt_set_timeout(struct watchdog *wdd, unsigned int timeout) >> +{ >> + struct k1c_wdt *wdt = container_of(wdd, struct k1c_wdt, wdd); >> + uint64_t cycle_timeout = wdt->clk_rate * timeout; >> + >> + /* Disable watchdog */ >> + if (timeout == 0) { >> + k1c_watchdog_disable(); >> + return 0; >> + } >> + >> + k1c_sfr_set(K1C_SFR_WDV, cycle_timeout); >> + k1c_sfr_set(K1C_SFR_WDR, 0); >> + >> + /* Start watchdog counting */ >> + k1c_sfr_set_bit(K1C_SFR_TCR, K1C_SFR_TCR_WUI_SHIFT); >> + k1c_sfr_set_bit(K1C_SFR_TCR, K1C_SFR_TCR_WCE_SHIFT); >> + >> + return 0; >> +} >> + >> +static void __noreturn k1c_wdt_restart_handle(struct restart_handler *rst) >> +{ >> + struct k1c_wdt *k1c_wdt; >> + >> + k1c_wdt = container_of(rst, struct k1c_wdt, restart); >> + >> + k1c_wdt->wdd.set_timeout(&k1c_wdt->wdd, 1); > > Do you do the same under Linux as well? This means you can't differentiate > between watchdog and normal resets. Agreed, on linux we did not implemented it like that and you are right, the reset cause will be the same. I think I should remove this restart handler part (See my comment below). > >> + >> + mdelay(1000); >> + >> + hang(); >> +} >> + >> +static int count; >> + >> +static int k1c_wdt_drv_probe(struct device_d *dev) >> +{ >> + struct watchdog *wdd; >> + struct clk *clk; >> + struct k1c_wdt *k1c_wdt; >> + int ret; >> + >> + if (count != 0) { >> + dev_warn(dev, "Tried to register core watchdog twice\n"); >> + return -EINVAL; >> + } >> + count++; >> + >> + k1c_wdt = xzalloc(sizeof(*k1c_wdt)); >> + clk = clk_get(dev, NULL); >> + if (IS_ERR(clk)) >> + return PTR_ERR(clk); >> + >> + k1c_wdt->clk_rate = clk_get_rate(clk); >> + clk_put(clk); >> + >> + wdd = &k1c_wdt->wdd; >> + wdd->name = "k1c_wdt"; >> + wdd->hwdev = dev; >> + wdd->set_timeout = k1c_wdt_set_timeout; >> + >> + /* Be sure that interrupt is disabled */ >> + k1c_sfr_clear_bit(K1C_SFR_TCR, K1C_SFR_TCR_WIE_SHIFT); >> + >> + k1c_watchdog_disable(); >> + >> + ret = watchdog_register(wdd); >> + if (ret) >> + return -EINVAL; >> + >> + k1c_wdt->restart.name = "k1c_wdt"; >> + k1c_wdt->restart.priority = 50; > > Maybe add a comment on why you set a lower than default priority? Indeed. We actually have another mean of resetting so this is not the preferred way to restart. I'm not even sure if I should keep the restart handler. Maybe I should left it out and use the reset register. Thanks for your review Clément > >> + k1c_wdt->restart.restart = k1c_wdt_restart_handle; >> + >> + ret = restart_handler_register(&k1c_wdt->restart); >> + if (ret) >> + dev_warn(dev, "cannot register restart handler\n"); >> + >> + return 0; >> + >> +} >> + >> +static struct of_device_id k1c_wdt_of_match[] = { >> + { .compatible = "kalray,k1c-core-watchdog", }, >> + { /* sentinel */ } >> +}; >> + >> +static struct driver_d k1c_wdt_driver = { >> + .name = "k1c-wdt", >> + .probe = k1c_wdt_drv_probe, >> + .of_compatible = DRV_OF_COMPAT(k1c_wdt_of_match), >> +}; >> +device_platform_driver(k1c_wdt_driver); >> > > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | https://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > > _______________________________________________ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] Add support for Kalray k1c core 2020-01-15 10:26 [PATCH 0/5] Add support for Kalray k1c core Clement Leger ` (4 preceding siblings ...) 2020-01-15 10:26 ` [PATCH 5/5] watchdog: k1c: Add k1c watchdog support Clement Leger @ 2020-01-16 8:25 ` Sascha Hauer 2020-01-16 8:53 ` Clément Leger 2020-01-16 9:49 ` Roland Hieber 6 siblings, 1 reply; 22+ messages in thread From: Sascha Hauer @ 2020-01-16 8:25 UTC (permalink / raw) To: Clement Leger; +Cc: barebox Hi Clement, On Wed, Jan 15, 2020 at 11:26:45AM +0100, Clement Leger wrote: > Kalray k1c core is embedded in Kalray Coolidge SoC. This core has the > following features: > - 32/64 bits > - 6-issue VLIW architecture > - 64 x 64bits general purpose registers > - SIMD instructions > - little-endian > > This port is a 64 bits one and allows to boot up to a barebox prompt on a k200 > board. k1c support for clocksource and watchdog is also part of this port. > > In order to build a usable toolchain, build scripts are provided at the > following address: https://github.com/kalray/build-scripts. > > Kalray uses FOSS which is available at https://github.com/kalray > > Clement Leger (5): > k1c: Initial Kalray Coolidge (k1c) architecture support > k1c: Add processor definitions > k1c: Add support for device tree > clocksource: k1c: Add k1c clocksource support > watchdog: k1c: Add k1c watchdog support From a first look this is all pretty straight forward, looks good ;) barebox is entered at 0x0. According to the linker script and the device tree you have 4MiB of SRAM there, right? I don't see any SDRAM setup code in this series, nevertheless it is used. How is SDRAM setup done? Is it done in ROM or is it some board specific binary that runs before barebox? Generally it seems that the board code is not very well separated from the SoC code. Ideally barebox startup is like: - The entry point is board specific - in this board specific code everything is done that is needed for a properly running SoC with SDRAM enabled. This may require some helper functions to be shared between boards - the entry code jumps to the generic code, passing a pointer to the device tree and if necessary SDRAM base/size With this setup we can build barebox images for multiple boards (or multiple configurations of boards) in one go. As a developer you can test on multiple boards without having to recompile. For a compile tester it reduces the number of configurations to build (faster results). For an integrator it reduces the number of barebox receipts to keep track of. Overall it's worth implementing such a scheme. It would be great to get there with the Kalray SoC as well, that's why I asked about the SDRAM setup above. If there is board specific code running before barebox, it should be possible to pass information to barebox on which board we are actually running. With this information we could reduce the need for board specifics in barebox. I hope my questions go into the right direction, maybe just tell me a little bit more about the SoC startup. Regards, Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] Add support for Kalray k1c core 2020-01-16 8:25 ` [PATCH 0/5] Add support for Kalray k1c core Sascha Hauer @ 2020-01-16 8:53 ` Clément Leger 2020-01-16 9:22 ` Sascha Hauer 0 siblings, 1 reply; 22+ messages in thread From: Clément Leger @ 2020-01-16 8:53 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List Hi Sasha ----- On 16 Jan, 2020, at 09:25, Sascha Hauer s.hauer@pengutronix.de wrote: > Hi Clement, > > On Wed, Jan 15, 2020 at 11:26:45AM +0100, Clement Leger wrote: >> Kalray k1c core is embedded in Kalray Coolidge SoC. This core has the >> following features: >> - 32/64 bits >> - 6-issue VLIW architecture >> - 64 x 64bits general purpose registers >> - SIMD instructions >> - little-endian >> >> This port is a 64 bits one and allows to boot up to a barebox prompt on a k200 >> board. k1c support for clocksource and watchdog is also part of this port. >> >> In order to build a usable toolchain, build scripts are provided at the >> following address: https://github.com/kalray/build-scripts. >> >> Kalray uses FOSS which is available at https://github.com/kalray >> >> Clement Leger (5): >> k1c: Initial Kalray Coolidge (k1c) architecture support >> k1c: Add processor definitions >> k1c: Add support for device tree >> clocksource: k1c: Add k1c clocksource support >> watchdog: k1c: Add k1c watchdog support > > From a first look this is all pretty straight forward, looks good ;) > > barebox is entered at 0x0. According to the linker script and the device > tree you have 4MiB of SRAM there, right? Indeed, you are right, currently, with this setup the processor boots at address 0x0. Currently, this is used since the JTAG loader can only start an elf at address 0 (temporary limitation). The FSBL (First Stage boot loader) can however load the elf file at any address. I have a patch to locate all the barebox code in SDRAM which is used by the FSBL (see below) to load barebox in SDRAM. I can probably contribute this version if you prefer. Moreover, this will be the final usage so better get it ok right now. For your information about SoC memory map, the SDRAM is located at 0x100000000 and span on 64G, Additionally, 4G are mirrored at 0x80000000 for 32 bits compatibility. > > I don't see any SDRAM setup code in this series, nevertheless it is > used. How is SDRAM setup done? Is it done in ROM or is it some board > specific binary that runs before barebox? This is done using ROM code which runs before barebox. Boot flow is the following: - Processor boots in NOR SPI (XIP) - Execute ROM FSBL (First Stage Bootloader) which initialize needed peripherals (DDR, PCIe, etc) - Load SSBL (second stage bootloader) which is barebox ELF file in our case. - .dtb ELF section is patched by this bootloader using the device tree flashed into the board SPI NOR. - Then jumps to barebox. So the version I sent you is a bit different since it allow to have a builtin DTB. I wanted to be more standard with existing architecture. In our version, we have an empty .dtb section (which is of fixed size 24K). And the tools to load elf files (either the FSBL or JTAG tools) are flashing the right dtb (either from flash for FSBL or by board detection with JTAG) into the .dtb section. Tell me if you want me to stay the "standard" way with builtin DTB or if I can go with our way (fixed size .dtb section patched dynamically). > > Generally it seems that the board code is not very well separated from > the SoC code. Ideally barebox startup is like: > > - The entry point is board specific > - in this board specific code everything is done that is needed for a > properly running SoC with SDRAM enabled. This may require some helper > functions to be shared between boards > - the entry code jumps to the generic code, passing a pointer to > the device tree and if necessary SDRAM base/size > > With this setup we can build barebox images for multiple boards (or > multiple configurations of boards) in one go. As a developer you can > test on multiple boards without having to recompile. For a compile > tester it reduces the number of configurations to build (faster > results). For an integrator it reduces the number of barebox receipts to > keep track of. Overall it's worth implementing such a scheme. Actually, due to the fact we use device tree from the scratch, we don't have any board specific code. Almost everything is probed from the device tree. So we always have only one barebox binary which runs on multiple boards and the .dtb section is patched dynamically. > > It would be great to get there with the Kalray SoC as well, that's why I > asked about the SDRAM setup above. If there is board specific code > running before barebox, it should be possible to pass information to > barebox on which board we are actually running. With this information we > could reduce the need for board specifics in barebox. > > I hope my questions go into the right direction, maybe just tell me a > little bit more about the SoC startup. Hope this shed some light on the boot process and why we don't have any boards/ directory :) Thanks for your review, Regards, Clément > > Regards, > Sascha > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] Add support for Kalray k1c core 2020-01-16 8:53 ` Clément Leger @ 2020-01-16 9:22 ` Sascha Hauer 2020-01-16 9:37 ` Clément Leger 0 siblings, 1 reply; 22+ messages in thread From: Sascha Hauer @ 2020-01-16 9:22 UTC (permalink / raw) To: Clément Leger; +Cc: Barebox List On Thu, Jan 16, 2020 at 09:53:41AM +0100, Clément Leger wrote: > Hi Sasha > > ----- On 16 Jan, 2020, at 09:25, Sascha Hauer s.hauer@pengutronix.de wrote: > > > Hi Clement, > > > > On Wed, Jan 15, 2020 at 11:26:45AM +0100, Clement Leger wrote: > >> Kalray k1c core is embedded in Kalray Coolidge SoC. This core has the > >> following features: > >> - 32/64 bits > >> - 6-issue VLIW architecture > >> - 64 x 64bits general purpose registers > >> - SIMD instructions > >> - little-endian > >> > >> This port is a 64 bits one and allows to boot up to a barebox prompt on a k200 > >> board. k1c support for clocksource and watchdog is also part of this port. > >> > >> In order to build a usable toolchain, build scripts are provided at the > >> following address: https://github.com/kalray/build-scripts. > >> > >> Kalray uses FOSS which is available at https://github.com/kalray > >> > >> Clement Leger (5): > >> k1c: Initial Kalray Coolidge (k1c) architecture support > >> k1c: Add processor definitions > >> k1c: Add support for device tree > >> clocksource: k1c: Add k1c clocksource support > >> watchdog: k1c: Add k1c watchdog support > > > > From a first look this is all pretty straight forward, looks good ;) > > > > barebox is entered at 0x0. According to the linker script and the device > > tree you have 4MiB of SRAM there, right? > > Indeed, you are right, currently, with this setup the processor boots > at address 0x0. > Currently, this is used since the JTAG loader can only start an elf > at address 0 (temporary limitation). The FSBL (First Stage boot loader) > can however load the elf file at any address. > > I have a patch to locate all the barebox code in SDRAM which is used > by the FSBL (see below) to load barebox in SDRAM. > > I can probably contribute this version if you prefer. Moreover, this will > be the final usage so better get it ok right now. > > For your information about SoC memory map, the SDRAM is located at > 0x100000000 and span on 64G, Additionally, 4G are mirrored at > 0x80000000 for 32 bits compatibility. > > > > > I don't see any SDRAM setup code in this series, nevertheless it is > > used. How is SDRAM setup done? Is it done in ROM or is it some board > > specific binary that runs before barebox? > > This is done using ROM code which runs before barebox. Boot flow is the > following: > - Processor boots in NOR SPI (XIP) > - Execute ROM FSBL (First Stage Bootloader) which initialize needed > peripherals (DDR, PCIe, etc) > - Load SSBL (second stage bootloader) which is barebox ELF file in our case. > - .dtb ELF section is patched by this bootloader using the device tree > flashed into the board SPI NOR. > - Then jumps to barebox. > > So the version I sent you is a bit different since it allow to have a > builtin DTB. I wanted to be more standard with existing architecture. > > In our version, we have an empty .dtb section (which is of fixed size 24K). > And the tools to load elf files (either the FSBL or JTAG tools) are > flashing the right dtb (either from flash for FSBL or by board detection > with JTAG) into the .dtb section. > > Tell me if you want me to stay the "standard" way with builtin DTB or if > I can go with our way (fixed size .dtb section patched dynamically). Well, patching the barebox binary with a device tree is not very standard at all ;) How about just passing the dtb as a pointer to barebox? You are probably passing the device tree to linux as well, right? Maybe you can reuse your Kernel calling convention for barebox? That way it wouldn't matter if a started image is barebox or linux, it's both the same. > > > > > Generally it seems that the board code is not very well separated from > > the SoC code. Ideally barebox startup is like: > > > > - The entry point is board specific > > - in this board specific code everything is done that is needed for a > > properly running SoC with SDRAM enabled. This may require some helper > > functions to be shared between boards > > - the entry code jumps to the generic code, passing a pointer to > > the device tree and if necessary SDRAM base/size > > > > With this setup we can build barebox images for multiple boards (or > > multiple configurations of boards) in one go. As a developer you can > > test on multiple boards without having to recompile. For a compile > > tester it reduces the number of configurations to build (faster > > results). For an integrator it reduces the number of barebox receipts to > > keep track of. Overall it's worth implementing such a scheme. > > Actually, due to the fact we use device tree from the scratch, we don't > have any board specific code. Almost everything is probed from the device > tree. So we always have only one barebox binary which runs on multiple > boards and the .dtb section is patched dynamically. Ok, that's good news. With that your barebox startup is just fine and you don't need any multi image builds, at least as long as you do not integrate the first stage loader into barebox ;) Regards, Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] Add support for Kalray k1c core 2020-01-16 9:22 ` Sascha Hauer @ 2020-01-16 9:37 ` Clément Leger 2020-01-16 9:46 ` Sascha Hauer 0 siblings, 1 reply; 22+ messages in thread From: Clément Leger @ 2020-01-16 9:37 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List ----- On 16 Jan, 2020, at 10:22, Sascha Hauer s.hauer@pengutronix.de wrote: > On Thu, Jan 16, 2020 at 09:53:41AM +0100, Clément Leger wrote: >> Hi Sasha >> >> ----- On 16 Jan, 2020, at 09:25, Sascha Hauer s.hauer@pengutronix.de wrote: >> >> > Hi Clement, >> > >> > On Wed, Jan 15, 2020 at 11:26:45AM +0100, Clement Leger wrote: >> >> Kalray k1c core is embedded in Kalray Coolidge SoC. This core has the >> >> following features: >> >> - 32/64 bits >> >> - 6-issue VLIW architecture >> >> - 64 x 64bits general purpose registers >> >> - SIMD instructions >> >> - little-endian >> >> >> >> This port is a 64 bits one and allows to boot up to a barebox prompt on a k200 >> >> board. k1c support for clocksource and watchdog is also part of this port. >> >> >> >> In order to build a usable toolchain, build scripts are provided at the >> >> following address: https://github.com/kalray/build-scripts. >> >> >> >> Kalray uses FOSS which is available at https://github.com/kalray >> >> >> >> Clement Leger (5): >> >> k1c: Initial Kalray Coolidge (k1c) architecture support >> >> k1c: Add processor definitions >> >> k1c: Add support for device tree >> >> clocksource: k1c: Add k1c clocksource support >> >> watchdog: k1c: Add k1c watchdog support >> > >> > From a first look this is all pretty straight forward, looks good ;) >> > >> > barebox is entered at 0x0. According to the linker script and the device >> > tree you have 4MiB of SRAM there, right? >> >> Indeed, you are right, currently, with this setup the processor boots >> at address 0x0. >> Currently, this is used since the JTAG loader can only start an elf >> at address 0 (temporary limitation). The FSBL (First Stage boot loader) >> can however load the elf file at any address. >> >> I have a patch to locate all the barebox code in SDRAM which is used >> by the FSBL (see below) to load barebox in SDRAM. >> >> I can probably contribute this version if you prefer. Moreover, this will >> be the final usage so better get it ok right now. >> >> For your information about SoC memory map, the SDRAM is located at >> 0x100000000 and span on 64G, Additionally, 4G are mirrored at >> 0x80000000 for 32 bits compatibility. >> >> > >> > I don't see any SDRAM setup code in this series, nevertheless it is >> > used. How is SDRAM setup done? Is it done in ROM or is it some board >> > specific binary that runs before barebox? >> >> This is done using ROM code which runs before barebox. Boot flow is the >> following: >> - Processor boots in NOR SPI (XIP) >> - Execute ROM FSBL (First Stage Bootloader) which initialize needed >> peripherals (DDR, PCIe, etc) >> - Load SSBL (second stage bootloader) which is barebox ELF file in our case. >> - .dtb ELF section is patched by this bootloader using the device tree >> flashed into the board SPI NOR. >> - Then jumps to barebox. >> >> So the version I sent you is a bit different since it allow to have a >> builtin DTB. I wanted to be more standard with existing architecture. >> >> In our version, we have an empty .dtb section (which is of fixed size 24K). >> And the tools to load elf files (either the FSBL or JTAG tools) are >> flashing the right dtb (either from flash for FSBL or by board detection >> with JTAG) into the .dtb section. >> >> Tell me if you want me to stay the "standard" way with builtin DTB or if >> I can go with our way (fixed size .dtb section patched dynamically). > > Well, patching the barebox binary with a device tree is not very > standard at all ;) > > How about just passing the dtb as a pointer to barebox? You are probably > passing the device tree to linux as well, right? Maybe you can reuse > your Kernel calling convention for barebox? That way it wouldn't matter > if a started image is barebox or linux, it's both the same. Agreed, moreover, this is already done in our Linux port :) So to sumarize, I should keep the buitlin DTB mecanism + dtb passing via registers. Is it ok ? > >> >> > >> > Generally it seems that the board code is not very well separated from >> > the SoC code. Ideally barebox startup is like: >> > >> > - The entry point is board specific >> > - in this board specific code everything is done that is needed for a >> > properly running SoC with SDRAM enabled. This may require some helper >> > functions to be shared between boards >> > - the entry code jumps to the generic code, passing a pointer to >> > the device tree and if necessary SDRAM base/size >> > >> > With this setup we can build barebox images for multiple boards (or >> > multiple configurations of boards) in one go. As a developer you can >> > test on multiple boards without having to recompile. For a compile >> > tester it reduces the number of configurations to build (faster >> > results). For an integrator it reduces the number of barebox receipts to >> > keep track of. Overall it's worth implementing such a scheme. >> >> Actually, due to the fact we use device tree from the scratch, we don't >> have any board specific code. Almost everything is probed from the device >> tree. So we always have only one barebox binary which runs on multiple >> boards and the .dtb section is patched dynamically. > > Ok, that's good news. With that your barebox startup is just fine and > you don't need any multi image builds, at least as long as you do not > integrate the first stage loader into barebox ;) Yes ! > > Regards, > Sascha > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] Add support for Kalray k1c core 2020-01-16 9:37 ` Clément Leger @ 2020-01-16 9:46 ` Sascha Hauer 0 siblings, 0 replies; 22+ messages in thread From: Sascha Hauer @ 2020-01-16 9:46 UTC (permalink / raw) To: Clément Leger; +Cc: Barebox List On Thu, Jan 16, 2020 at 10:37:26AM +0100, Clément Leger wrote: > > > ----- On 16 Jan, 2020, at 10:22, Sascha Hauer s.hauer@pengutronix.de wrote: > > > On Thu, Jan 16, 2020 at 09:53:41AM +0100, Clément Leger wrote: > >> Hi Sasha > >> > >> ----- On 16 Jan, 2020, at 09:25, Sascha Hauer s.hauer@pengutronix.de wrote: > >> > >> > Hi Clement, > >> > > >> > On Wed, Jan 15, 2020 at 11:26:45AM +0100, Clement Leger wrote: > >> >> Kalray k1c core is embedded in Kalray Coolidge SoC. This core has the > >> >> following features: > >> >> - 32/64 bits > >> >> - 6-issue VLIW architecture > >> >> - 64 x 64bits general purpose registers > >> >> - SIMD instructions > >> >> - little-endian > >> >> > >> >> This port is a 64 bits one and allows to boot up to a barebox prompt on a k200 > >> >> board. k1c support for clocksource and watchdog is also part of this port. > >> >> > >> >> In order to build a usable toolchain, build scripts are provided at the > >> >> following address: https://github.com/kalray/build-scripts. > >> >> > >> >> Kalray uses FOSS which is available at https://github.com/kalray > >> >> > >> >> Clement Leger (5): > >> >> k1c: Initial Kalray Coolidge (k1c) architecture support > >> >> k1c: Add processor definitions > >> >> k1c: Add support for device tree > >> >> clocksource: k1c: Add k1c clocksource support > >> >> watchdog: k1c: Add k1c watchdog support > >> > > >> > From a first look this is all pretty straight forward, looks good ;) > >> > > >> > barebox is entered at 0x0. According to the linker script and the device > >> > tree you have 4MiB of SRAM there, right? > >> > >> Indeed, you are right, currently, with this setup the processor boots > >> at address 0x0. > >> Currently, this is used since the JTAG loader can only start an elf > >> at address 0 (temporary limitation). The FSBL (First Stage boot loader) > >> can however load the elf file at any address. > >> > >> I have a patch to locate all the barebox code in SDRAM which is used > >> by the FSBL (see below) to load barebox in SDRAM. > >> > >> I can probably contribute this version if you prefer. Moreover, this will > >> be the final usage so better get it ok right now. > >> > >> For your information about SoC memory map, the SDRAM is located at > >> 0x100000000 and span on 64G, Additionally, 4G are mirrored at > >> 0x80000000 for 32 bits compatibility. > >> > >> > > >> > I don't see any SDRAM setup code in this series, nevertheless it is > >> > used. How is SDRAM setup done? Is it done in ROM or is it some board > >> > specific binary that runs before barebox? > >> > >> This is done using ROM code which runs before barebox. Boot flow is the > >> following: > >> - Processor boots in NOR SPI (XIP) > >> - Execute ROM FSBL (First Stage Bootloader) which initialize needed > >> peripherals (DDR, PCIe, etc) > >> - Load SSBL (second stage bootloader) which is barebox ELF file in our case. > >> - .dtb ELF section is patched by this bootloader using the device tree > >> flashed into the board SPI NOR. > >> - Then jumps to barebox. > >> > >> So the version I sent you is a bit different since it allow to have a > >> builtin DTB. I wanted to be more standard with existing architecture. > >> > >> In our version, we have an empty .dtb section (which is of fixed size 24K). > >> And the tools to load elf files (either the FSBL or JTAG tools) are > >> flashing the right dtb (either from flash for FSBL or by board detection > >> with JTAG) into the .dtb section. > >> > >> Tell me if you want me to stay the "standard" way with builtin DTB or if > >> I can go with our way (fixed size .dtb section patched dynamically). > > > > Well, patching the barebox binary with a device tree is not very > > standard at all ;) > > > > How about just passing the dtb as a pointer to barebox? You are probably > > passing the device tree to linux as well, right? Maybe you can reuse > > your Kernel calling convention for barebox? That way it wouldn't matter > > if a started image is barebox or linux, it's both the same. > > Agreed, moreover, this is already done in our Linux port :) > > So to sumarize, I should keep the buitlin DTB mecanism + dtb passing > via registers. Is it ok ? I don't think we need builtin DTB at all. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] Add support for Kalray k1c core 2020-01-15 10:26 [PATCH 0/5] Add support for Kalray k1c core Clement Leger ` (5 preceding siblings ...) 2020-01-16 8:25 ` [PATCH 0/5] Add support for Kalray k1c core Sascha Hauer @ 2020-01-16 9:49 ` Roland Hieber 2020-01-16 9:53 ` Clément Leger 6 siblings, 1 reply; 22+ messages in thread From: Roland Hieber @ 2020-01-16 9:49 UTC (permalink / raw) To: Clement Leger; +Cc: barebox On Wed, Jan 15, 2020 at 11:26:45AM +0100, Clement Leger wrote: > Kalray k1c core is embedded in Kalray Coolidge SoC. This core has the > following features: > - 32/64 bits > - 6-issue VLIW architecture > - 64 x 64bits general purpose registers > - SIMD instructions > - little-endian > > This port is a 64 bits one and allows to boot up to a barebox prompt on a k200 > board. k1c support for clocksource and watchdog is also part of this port. > > In order to build a usable toolchain, build scripts are provided at the > following address: https://github.com/kalray/build-scripts. > > Kalray uses FOSS which is available at https://github.com/kalray > > Clement Leger (5): > k1c: Initial Kalray Coolidge (k1c) architecture support > k1c: Add processor definitions > k1c: Add support for device tree > clocksource: k1c: Add k1c clocksource support > watchdog: k1c: Add k1c watchdog support Uuuh, a shiny new architecture! You might also want to add some (minimal) documentation in Documentation/boards/ to advertise it. This way it will also appear on https://www.barebox.org/doc/latest/boards.html :) - Roland -- Roland Hieber, Pengutronix e.K. | r.hieber@pengutronix.de | Steuerwalder Str. 21 | https://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] Add support for Kalray k1c core 2020-01-16 9:49 ` Roland Hieber @ 2020-01-16 9:53 ` Clément Leger 0 siblings, 0 replies; 22+ messages in thread From: Clément Leger @ 2020-01-16 9:53 UTC (permalink / raw) To: Roland Hieber; +Cc: Barebox List Hi Roland, ----- On 16 Jan, 2020, at 10:49, Roland Hieber rhi@pengutronix.de wrote: > On Wed, Jan 15, 2020 at 11:26:45AM +0100, Clement Leger wrote: >> Kalray k1c core is embedded in Kalray Coolidge SoC. This core has the >> following features: >> - 32/64 bits >> - 6-issue VLIW architecture >> - 64 x 64bits general purpose registers >> - SIMD instructions >> - little-endian >> >> This port is a 64 bits one and allows to boot up to a barebox prompt on a k200 >> board. k1c support for clocksource and watchdog is also part of this port. >> >> In order to build a usable toolchain, build scripts are provided at the >> following address: https://github.com/kalray/build-scripts. >> >> Kalray uses FOSS which is available at https://github.com/kalray >> >> Clement Leger (5): >> k1c: Initial Kalray Coolidge (k1c) architecture support >> k1c: Add processor definitions >> k1c: Add support for device tree >> clocksource: k1c: Add k1c clocksource support >> watchdog: k1c: Add k1c watchdog support > > Uuuh, a shiny new architecture! You might also want to add some > (minimal) documentation in Documentation/boards/ to advertise it. This > way it will also appear on > https://www.barebox.org/doc/latest/boards.html :) Nice, thanks for the info ! Clément > > - Roland > > -- > Roland Hieber, Pengutronix e.K. | r.hieber@pengutronix.de | > Steuerwalder Str. 21 | https://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2020-01-20 16:09 UTC | newest] Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-01-15 10:26 [PATCH 0/5] Add support for Kalray k1c core Clement Leger 2020-01-15 10:26 ` [PATCH 1/5] k1c: Initial Kalray Coolidge (k1c) architecture support Clement Leger 2020-01-16 9:26 ` Sascha Hauer 2020-01-16 10:49 ` Clément Leger 2020-01-16 10:55 ` Sascha Hauer 2020-01-16 12:24 ` Clément Leger 2020-01-16 13:11 ` Sascha Hauer 2020-01-16 13:26 ` Clément Leger 2020-01-16 13:34 ` Sascha Hauer 2020-01-15 10:26 ` [PATCH 2/5] k1c: Add processor definitions Clement Leger 2020-01-15 10:26 ` [PATCH 3/5] k1c: Add support for device tree Clement Leger 2020-01-15 10:26 ` [PATCH 4/5] clocksource: k1c: Add k1c clocksource support Clement Leger 2020-01-15 10:26 ` [PATCH 5/5] watchdog: k1c: Add k1c watchdog support Clement Leger 2020-01-20 15:10 ` Ahmad Fatoum 2020-01-20 16:08 ` Clément Leger 2020-01-16 8:25 ` [PATCH 0/5] Add support for Kalray k1c core Sascha Hauer 2020-01-16 8:53 ` Clément Leger 2020-01-16 9:22 ` Sascha Hauer 2020-01-16 9:37 ` Clément Leger 2020-01-16 9:46 ` Sascha Hauer 2020-01-16 9:49 ` Roland Hieber 2020-01-16 9:53 ` Clément Leger
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