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dkim=none (message not signed) header.d=none;lists.infradead.org; dmarc=none action=none header.from=wolfvision.net; Received: from DBBPR08MB4523.eurprd08.prod.outlook.com (2603:10a6:10:c8::19) by DBBPR08MB5222.eurprd08.prod.outlook.com (2603:10a6:10:dc::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Mon, 21 Jun 2021 11:27:13 +0000 Received: from DBBPR08MB4523.eurprd08.prod.outlook.com ([fe80::7067:f3cb:b0c4:25dd]) by DBBPR08MB4523.eurprd08.prod.outlook.com ([fe80::7067:f3cb:b0c4:25dd%7]) with mapi id 15.20.4242.023; Mon, 21 Jun 2021 11:27:13 +0000 To: Sascha Hauer Cc: barebox@lists.infradead.org References: <20210617143654.32616-1-michael.riesch@wolfvision.net> <20210621043036.GE9782@pengutronix.de> From: Michael Riesch Organization: WolfVision GmbH Message-ID: Date: Mon, 21 Jun 2021 13:27:09 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.9.0 In-Reply-To: <20210621043036.GE9782@pengutronix.de> Content-Language: en-US X-Originating-IP: [91.118.163.37] X-ClientProxiedBy: VI1PR07CA0227.eurprd07.prod.outlook.com (2603:10a6:802:58::30) To DBBPR08MB4523.eurprd08.prod.outlook.com (2603:10a6:10:c8::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [192.168.100.125] (91.118.163.37) by VI1PR07CA0227.eurprd07.prod.outlook.com (2603:10a6:802:58::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.7 via Frontend Transport; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:e::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-3.5 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,NICE_REPLY_A, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH] aiodev: add driver for Rockchip SARADC X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) Hello Sascha, thanks for the review, I'll prepare a v2. On 6/21/21 6:30 AM, Sascha Hauer wrote: > Hi Michael, > > On Thu, Jun 17, 2021 at 04:36:54PM +0200, Michael Riesch wrote: >> +static int rockchip_saradc_read(struct aiochannel *chan, int *val) >> +{ >> + struct rockchip_saradc_data *data; >> + int timeout = SARADC_TIMEOUT; >> + u32 value = 0; >> + u32 control = 0; >> + u32 mask; >> + >> + if (!chan || !val) >> + return -EINVAL; >> + >> + data = container_of(chan->aiodev, struct rockchip_saradc_data, aiodev); >> + if (!data) >> + return -EINVAL; >> + >> + rockchip_saradc_reg_wr(data, 8, SARADC_DLY_PU_SOC); >> + rockchip_saradc_reg_wr(data, >> + (chan->index & SARADC_CTRL_CHN_MASK) | >> + SARADC_CTRL_IRQ_ENABLE | >> + SARADC_CTRL_POWER_CTRL, >> + SARADC_CTRL); >> + >> + do { >> + control = rockchip_saradc_reg_rd(data, SARADC_CTRL); >> + >> + if (--timeout == 0) >> + return -ETIMEDOUT; >> + mdelay(1); >> + } while (!(control & SARADC_CTRL_IRQ_STATUS)); > > You should do a timeout loop with > > u64 start = get_time_ns(); > > do { > if (is_timeout(start, 100 * MSECOND) > return -ETIMEDOUT; > } while(bar); > > We don't have any way nor need to put the CPU into idle, so we can poll > as fast as we can. OK, will replace that. >> + >> + mask = (1 << data->config->num_bits) - 1; >> + value = rockchip_saradc_reg_rd(data, SARADC_DATA) & mask; >> + rockchip_saradc_reg_wr(data, 0, SARADC_CTRL); >> + >> + printf("Raw value: %d\n", value); > > Debugging leftover. D'oh! >> +fail_channels: >> + kfree(data->channels); >> + kfree(data->aiodev.channels); >> + >> +fail_data: >> + kfree(data); >> + return ret; >> +} >> + >> +static const struct rockchip_saradc_cfg rk3568_saradc_cfg = { >> + .ref_voltage_mv = 1800, > > From looking at the downstream dts files this doesn't seem to be SoC > specific: > > &saradc { > status = "okay"; > vref-supply = <&vcca_1v8>; > }; > > I suggest doing the same here. > >> + .num_bits = 10, >> + .num_channels = 8, >> +}; >> + >> +static const struct of_device_id of_rockchip_saradc_match[] = { >> + { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_cfg }, > > The device nodes in the downstream Kernel also contain some clocks. > These should be handled in the driver. I'll see what I can do :-) Just had a look over the mainstream Kernel device tree. Resets, interrupts and number of io-channels are also provided there. Now I think that the interrupts are quite irrelevant for barebox, but should the resets be addressed as well? As to the number of iochannels, I think the maximum number should be provided in the SoC specific struct. Not sure what the value of specifying the actual number of channels in the device tree is, though. Regards, Michael _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox