Enclustra SA2: enable dual fast Ethernet

[David Picard <david.picard@clermont.in2p3.fr>]

Hello,

I am still using the same Mercury_SA2_ST1_Reference_Design [1][2] 
released by the manufacturer:
https://github.com/enclustra/Mercury_SA2_ST1_Reference_Design.git

But I compiled a variant of the project to enable dual fast Ethernet, 
because I need a 2nd Ethernet interface.

SA2 module Ethernet layout:
- 1 Ethernet MAC ("gmac1" in the DTS) of the HPS [3] is used for gigabit 
Ethernet, and connects with RGMII to PHY at address 3 >> working!
- 2 Ethernet MACs are implemented as FPGA IP cores and connect with RMII 
to PHYs at addresses 1 and 2 >> to be configured...

All 3 PHYs share the same MDIO bus.

I generated a DTS file with Intel's tool:
$ sopc2dts --force-altr -t dts -i 
./Quartus/ME-SA2-D6-7I-D11-DFE/sdmmc/Mercury_SA2_pd.sopcinfo -o 
Mercury_SA2_pd.dts

The file is here [4]:
https://filesender.renater.fr/?s=download&token=b2eeab16-063c-41ef-8abe-ea5b44f8f25a&lang=en

Now, I am trying to merge the fast Ethernet section with the 
socfpga_cyclone5_mercury_sa2.dtsi, but I really need a hint, here...
https://git.pengutronix.de/cgit/barebox/tree/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
https://git.pengutronix.de/cgit/barebox/tree/dts/src/arm/intel/socfpga/socfpga.dtsi

However, I do know for a fact that the 2 PHYs at addresses 1 and 2 share 
the same reset pin and can be released from reset by:
reset-gpios = <&portb 6 GPIO_ACTIVE_LOW>;

Currently, I program the FPGA from Linux with the .rbf file.

David (alias dpcrd)

=====
[1] An Intel Quartus project that generates the FPGA .rbf file, HPS (ARM 
core) configuration, etc.
[2] SA2 is the plug-in module with the SoC FPGA; ST1 is the development 
baseboard with connectors.
[3] HPS (Hardware Processor System) = ARM core inside the SoC FPGA chip.
[4] Generated DTS file + a screenshot of Platform Designer, the tool to 
configure the SoC FPGA system. "hps_0" is the ARM core, 
"fast_ethernet_0" (collapsed for clarity) and "fast_ethernet_1" are 2 
instances of the IP core. The left panel shows logical connections 
between blocks. Filled dots: horizontal and vertical lines are 
connected. Hollow dots: no connection.