* [PATCH 0/6] arm: imx8mp: add karo electronics qsxp imx8mp som support
@ 2024-03-11 9:10 Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 1/6] of: introduce of_property_read_s32 Stefan Kerkmann
` (5 more replies)
0 siblings, 6 replies; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 9:10 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX
The Ka-Ro QSXP[1] is a i.MX8M Plus solder down system on module. This
series adds support for the SOM itself on the QSBASE4 RDK. For ethernet
support on the QSBASE4 RDK, the Micrel phy driver gains support for the
KSZ9131 gigabit ethernet phy.
[1]: https://www.karo-electronics.de/qsxp
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
---
Marc Kleine-Budde (4):
net: phy: micrel: update id table from Linux kernel
net: phy: micrel: add support for ksz9131 phy
arm: dts: karo: import dts for karo-qsxp-ml81
arm: imx8mp: add karo electronics qsxp imx8mp som support
Sebastian Reichel (1):
of: introduce of_property_read_s32
Stefan Kerkmann (1):
arm: dts: karo: add karo imx8mp-karo-qsxp-qsbase4
arch/arm/boards/Makefile | 1 +
arch/arm/boards/karo-qsxp-ml81/Makefile | 4 +
arch/arm/boards/karo-qsxp-ml81/board.c | 35 +
.../flash-header-karo-qsxp-ml81.imxcfg | 9 +
arch/arm/boards/karo-qsxp-ml81/lowlevel.c | 102 ++
arch/arm/boards/karo-qsxp-ml81/lowlevel.h | 8 +
arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c | 1597 ++++++++++++++++++++
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts | 86 ++
arch/arm/dts/imx8mp-karo-qsxp-ml81.dts | 160 ++
arch/arm/dts/imx8mp-karo.dtsi | 407 +++++
arch/arm/mach-imx/Kconfig | 10 +
drivers/net/phy/micrel.c | 188 +++
images/Makefile.imx | 2 +
include/linux/micrel_phy.h | 49 +-
include/of.h | 7 +
16 files changed, 2659 insertions(+), 7 deletions(-)
---
base-commit: 6883d32102d8a253f4fc2bcfafbf3767a725e3a8
change-id: 20240311-karo-imx8mp-som-board-upstreaming-9eef98b7735e
Best regards,
--
Stefan Kerkmann <s.kerkmann@pengutronix.de>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/6] of: introduce of_property_read_s32
2024-03-11 9:10 [PATCH 0/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
@ 2024-03-11 9:10 ` Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 2/6] net: phy: micrel: update id table from Linux kernel Stefan Kerkmann
` (4 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 9:10 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX
From: Sebastian Reichel <sre@kernel.org>
Introduce signed 32bit integer of_property_read method.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
---
include/of.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/of.h b/include/of.h
index 9cd2c9aee2..9eef6d7f13 100644
--- a/include/of.h
+++ b/include/of.h
@@ -1138,6 +1138,13 @@ static inline int of_property_read_u32(const struct device_node *np,
return of_property_read_u32_array(np, propname, out_value, 1);
}
+static inline int of_property_read_s32(const struct device_node *np,
+ const char *propname,
+ s32 *out_value)
+{
+ return of_property_read_u32(np, propname, (u32*) out_value);
+}
+
/**
* of_property_read_u64_array - Find and read an array of 64 bit integers
* from a property.
--
2.39.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/6] net: phy: micrel: update id table from Linux kernel
2024-03-11 9:10 [PATCH 0/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 1/6] of: introduce of_property_read_s32 Stefan Kerkmann
@ 2024-03-11 9:10 ` Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 3/6] net: phy: micrel: add support for ksz9131 phy Stefan Kerkmann
` (3 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 9:10 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX
From: Marc Kleine-Budde <mkl@pengutronix.de>
This syncs the known Micrel PHY IDs and register definitions with the
Linux kernel, commit f600bb612b06adf70ccdefbd3294c71275b650c2.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
---
include/linux/micrel_phy.h | 49 +++++++++++++++++++++++++++++++++++++++-------
1 file changed, 42 insertions(+), 7 deletions(-)
diff --git a/include/linux/micrel_phy.h b/include/linux/micrel_phy.h
index 8752dbbc61..591bf5b5e8 100644
--- a/include/linux/micrel_phy.h
+++ b/include/linux/micrel_phy.h
@@ -1,26 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/linux/micrel_phy.h
*
* Micrel PHY IDs
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
*/
#ifndef _MICREL_PHY_H
#define _MICREL_PHY_H
+#define MICREL_OUI 0x0885
+
#define MICREL_PHY_ID_MASK 0x00fffff0
#define PHY_ID_KSZ8873MLL 0x000e7237
#define PHY_ID_KSZ9021 0x00221610
+#define PHY_ID_KSZ9021RLRN 0x00221611
#define PHY_ID_KS8737 0x00221720
#define PHY_ID_KSZ8021 0x00221555
#define PHY_ID_KSZ8031 0x00221556
#define PHY_ID_KSZ8041 0x00221510
+/* undocumented */
+#define PHY_ID_KSZ8041RNLI 0x00221537
#define PHY_ID_KSZ8051 0x00221550
/* same id: ks8001 Rev. A/B, and ks8721 Rev 3. */
#define PHY_ID_KSZ8001 0x0022161A
@@ -28,11 +28,46 @@
#define PHY_ID_KSZ8081 0x00221560
#define PHY_ID_KSZ8061 0x00221570
#define PHY_ID_KSZ9031 0x00221620
+#define PHY_ID_KSZ9131 0x00221640
+#define PHY_ID_LAN8814 0x00221660
+#define PHY_ID_LAN8804 0x00221670
+#define PHY_ID_LAN8841 0x00221650
#define PHY_ID_KSZ886X 0x00221430
#define PHY_ID_KSZ8863 0x00221435
+#define PHY_ID_KSZ87XX 0x00221550
+
+#define PHY_ID_KSZ9477 0x00221631
+
/* struct phy_device dev_flags definitions */
-#define MICREL_PHY_50MHZ_CLK 0x00000001
+#define MICREL_PHY_50MHZ_CLK BIT(0)
+#define MICREL_PHY_FXEN BIT(1)
+#define MICREL_KSZ8_P1_ERRATA BIT(2)
+#define MICREL_NO_EEE BIT(3)
+
+#define MICREL_KSZ9021_EXTREG_CTRL 0xB
+#define MICREL_KSZ9021_EXTREG_DATA_WRITE 0xC
+#define MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW 0x104
+#define MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW 0x105
+
+/* Device specific MII_BMCR (Reg 0) bits */
+/* 1 = HP Auto MDI/MDI-X mode, 0 = Microchip Auto MDI/MDI-X mode */
+#define KSZ886X_BMCR_HP_MDIX BIT(5)
+/* 1 = Force MDI (transmit on RXP/RXM pins), 0 = Normal operation
+ * (transmit on TXP/TXM pins)
+ */
+#define KSZ886X_BMCR_FORCE_MDI BIT(4)
+/* 1 = Disable auto MDI-X */
+#define KSZ886X_BMCR_DISABLE_AUTO_MDIX BIT(3)
+#define KSZ886X_BMCR_DISABLE_FAR_END_FAULT BIT(2)
+#define KSZ886X_BMCR_DISABLE_TRANSMIT BIT(1)
+#define KSZ886X_BMCR_DISABLE_LED BIT(0)
+
+/* PHY Special Control/Status Register (Reg 31) */
+#define KSZ886X_CTRL_MDIX_STAT BIT(4)
+#define KSZ886X_CTRL_FORCE_LINK BIT(3)
+#define KSZ886X_CTRL_PWRSAVE BIT(2)
+#define KSZ886X_CTRL_REMOTE_LOOPBACK BIT(1)
#endif /* _MICREL_PHY_H */
--
2.39.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/6] net: phy: micrel: add support for ksz9131 phy
2024-03-11 9:10 [PATCH 0/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 1/6] of: introduce of_property_read_s32 Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 2/6] net: phy: micrel: update id table from Linux kernel Stefan Kerkmann
@ 2024-03-11 9:10 ` Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 4/6] arm: dts: karo: import dts for karo-qsxp-ml81 Stefan Kerkmann
` (2 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 9:10 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX
From: Marc Kleine-Budde <mkl@pengutronix.de>
This imports the micrel KSZ9131 gigabit phy driver from Linux, commit
0316c7e66bbd16cf2d01a4e2f5afa6afb01278f2.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
---
drivers/net/phy/micrel.c | 188 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 188 insertions(+)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 36cc857a2c..a203669353 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -546,6 +546,186 @@ static int ksz9031_config_init(struct phy_device *phydev)
return ret;
}
+#define KSZ9131_SKEW_5BIT_MAX 2400
+#define KSZ9131_SKEW_4BIT_MAX 800
+#define KSZ9131_OFFSET 700
+#define KSZ9131_STEP 100
+
+static int ksz9131_of_load_skew_values(struct phy_device *phydev,
+ const struct device_node *of_node,
+ u16 reg, size_t field_sz,
+ const char *field[], u8 numfields)
+{
+ int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
+ -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
+ int skewval, skewmax = 0;
+ int matches = 0;
+ u16 maxval;
+ u16 newval;
+ u16 mask;
+ int i;
+
+ /* psec properties in dts should mean x pico seconds */
+ if (field_sz == 5)
+ skewmax = KSZ9131_SKEW_5BIT_MAX;
+ else
+ skewmax = KSZ9131_SKEW_4BIT_MAX;
+
+ for (i = 0; i < numfields; i++)
+ if (!of_property_read_s32(of_node, field[i], &skewval)) {
+ if (skewval < -KSZ9131_OFFSET)
+ skewval = -KSZ9131_OFFSET;
+ else if (skewval > skewmax)
+ skewval = skewmax;
+
+ val[i] = skewval + KSZ9131_OFFSET;
+ matches++;
+ }
+
+ if (!matches)
+ return 0;
+
+ if (matches < numfields)
+ newval = phy_read_mmd(phydev, 2, reg);
+ else
+ newval = 0;
+
+ maxval = (field_sz == 4) ? 0xf : 0x1f;
+ for (i = 0; i < numfields; i++)
+ if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
+ mask = 0xffff;
+ mask ^= maxval << (field_sz * i);
+ newval = (newval & mask) |
+ (((val[i] / KSZ9131_STEP) & maxval)
+ << (field_sz * i));
+ }
+
+ return phy_write_mmd(phydev, 2, reg, newval);
+}
+
+#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
+#define KSZ9131RN_RXC_DLL_CTRL 76
+#define KSZ9131RN_TXC_DLL_CTRL 77
+#define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
+#define KSZ9131RN_DLL_ENABLE_DELAY 0
+#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
+
+static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
+{
+ u16 rxcdll_val, txcdll_val;
+ int ret;
+
+ switch (phydev->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+ txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+ txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+ txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+ txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+ break;
+ default:
+ return 0;
+ }
+
+ ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+ rxcdll_val);
+ if (ret < 0)
+ return ret;
+
+ return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+ txcdll_val);
+}
+
+/* Silicon Errata DS80000693B
+ *
+ * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
+ * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
+ * according to the datasheet (off if there is no link).
+ */
+static int ksz9131_led_errata(struct phy_device *phydev)
+{
+ int reg;
+
+ reg = phy_read_mmd(phydev, 2, 0);
+ if (reg < 0)
+ return reg;
+
+ if (!(reg & BIT(4)))
+ return 0;
+
+ return phy_set_bits(phydev, 0x1e, BIT(9));
+}
+
+static int ksz9131_config_init(struct phy_device *phydev)
+{
+ const struct device *dev = &phydev->dev;
+ const struct device_node *of_node = dev->of_node;
+ static const char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
+ static const char *rx_data_skews[4] = {
+ "rxd0-skew-psec", "rxd1-skew-psec",
+ "rxd2-skew-psec", "rxd3-skew-psec"
+ };
+ static const char *tx_data_skews[4] = {
+ "txd0-skew-psec", "txd1-skew-psec",
+ "txd2-skew-psec", "txd3-skew-psec"
+ };
+ static const char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
+ int ret;
+
+ if (!of_node && dev->parent->of_node)
+ of_node = dev->parent->of_node;
+
+ if (!of_node)
+ return 0;
+
+ if (phy_interface_is_rgmii(phydev)) {
+ ret = ksz9131_config_rgmii_delay(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = ksz9131_of_load_skew_values(phydev, of_node,
+ MII_KSZ9031RN_CLK_PAD_SKEW, 5,
+ clk_skews, 2);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz9131_of_load_skew_values(phydev, of_node,
+ MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
+ control_skews, 2);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz9131_of_load_skew_values(phydev, of_node,
+ MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
+ rx_data_skews, 4);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz9131_of_load_skew_values(phydev, of_node,
+ MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
+ tx_data_skews, 4);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz9131_led_errata(phydev);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
@@ -757,6 +937,14 @@ static struct phy_driver ksphy_driver[] = {
.config_init = ksz9031_config_init,
.config_aneg = genphy_config_aneg,
.read_status = ksz9031_read_status,
+}, {
+ .phy_id = PHY_ID_KSZ9131,
+ .phy_id_mask = 0x00fffff0,
+ .drv.name = "Microchip KSZ9131 Gigabit PHY",
+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
+ .config_init = ksz9131_config_init,
+ .config_aneg = genphy_config_aneg,
+ .read_status = genphy_read_status,
}, {
.phy_id = PHY_ID_KSZ8873MLL,
.phy_id_mask = 0x00fffff0,
--
2.39.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/6] arm: dts: karo: import dts for karo-qsxp-ml81
2024-03-11 9:10 [PATCH 0/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
` (2 preceding siblings ...)
2024-03-11 9:10 ` [PATCH 3/6] net: phy: micrel: add support for ksz9131 phy Stefan Kerkmann
@ 2024-03-11 9:10 ` Stefan Kerkmann
2024-03-11 10:02 ` Ahmad Fatoum
2024-03-11 9:10 ` [PATCH 5/6] arm: dts: karo: add karo imx8mp-karo-qsxp-qsbase4 Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 6/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
5 siblings, 1 reply; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 9:10 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX
From: Marc Kleine-Budde <mkl@pengutronix.de>
This imports the device tree for the Ka-Ro QSXP, which is a i.MX8M Plus
solder down system on module. The sources have been adapted from the
offical Ka-Ro github[1], commit a49b38ec97854c0cd9cd83a9f4ae3b56e99a58b6.
[1]: https://github.com/karo-electronics/meta-karo-nxp.git
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
---
arch/arm/dts/imx8mp-karo-qsxp-ml81.dts | 160 +++++++++++++
arch/arm/dts/imx8mp-karo.dtsi | 407 +++++++++++++++++++++++++++++++++
2 files changed, 567 insertions(+)
diff --git a/arch/arm/dts/imx8mp-karo-qsxp-ml81.dts b/arch/arm/dts/imx8mp-karo-qsxp-ml81.dts
new file mode 100644
index 0000000000..f64a279e66
--- /dev/null
+++ b/arch/arm/dts/imx8mp-karo-qsxp-ml81.dts
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "imx8mp-karo.dtsi"
+
+/ {
+ model = "Ka-Ro electronics QSXP-ML81 (NXP i.MX8MP) module";
+ compatible = "karo,imx8mp-qsxp-ml81", "fsl,imx8mp";
+
+ reg_3v3_etn: regulator-3v3-etn {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3-etn";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ldo5_reg>;
+ };
+
+ chosen {
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &env_emmc;
+ status = "disabled";
+ };
+ };
+
+ aliases {
+ state = &state_emmc;
+ };
+
+ state_emmc: state {
+ compatible = "barebox,state";
+ magic = <0xabff4b1f>;
+ backend-type = "raw";
+ backend = <&usdhc3>;
+ backend-storage-type="direct";
+ /*
+ * barebox-state partition size: 1 MiB
+ * nr. of redundant copies: 4
+ * ==> max. stride size: 1 MiB / 4 = 256 KiB = 262144 Byte
+ *
+ * stride size: 262144 Byte
+ * raw-header: - 16 Byte
+ * direct-storage: - 8 Byte
+ * ------------
+ * max state size: 262120 Byte
+ * ===========
+ */
+ backend-stridesize = <0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ system0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ remaining_attempts@0 {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ default = <2>;
+ };
+
+ priority@4 {
+ reg = <0x4 0x4>;
+ type= "uint32";
+ default = <21>;
+ };
+ };
+
+ system1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ remaining_attempts@8 {
+ reg = <0x8 0x4>;
+ type = "uint32";
+ default = <2>;
+ };
+
+ priority@c {
+ reg = <0xc 0x4>;
+ type= "uint32";
+ default = <20>;
+ };
+ };
+
+ last_chosen@10 {
+ reg = <0x10 0x4>;
+ type = "uint32";
+ };
+ };
+ };
+};
+
+&usdhc3 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0x0 0x0 0x100000>;
+ };
+
+ env_emmc: partition@100000 {
+ label = "dt-barebox-environment";
+ reg = <0x0 0x100000 0x0 0x100000>;
+ };
+ };
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&ldo5_reg {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+};
+
+&iomuxc {
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x140
+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x140
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x140
+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-karo.dtsi b/arch/arm/dts/imx8mp-karo.dtsi
new file mode 100644
index 0000000000..7e679362ac
--- /dev/null
+++ b/arch/arm/dts/imx8mp-karo.dtsi
@@ -0,0 +1,407 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ */
+
+#include <arm64/freescale/imx8mp.dtsi>
+#include "imx8mp.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pmic@25 {
+ reg = <0x25>;
+ compatible = "nxp,pca9450c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ status = "okay";
+
+ regulators {
+ reg_vdd_soc: BUCK1 {
+ regulator-name = "vdd-soc";
+ regulator-min-microvolt = <805000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ reg_vdd_arm: BUCK2 {
+ regulator-name = "vdd-core";
+ regulator-min-microvolt = <805000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ reg_vdd_3v3: BUCK4 {
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_nand: BUCK5 {
+ regulator-name = "nvcc-nand";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_dram: BUCK6 {
+ regulator-name = "nvcc-dram";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_snvs_1v8: LDO1 {
+ regulator-name = "snvs-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ };
+
+ reg_vdda_1v8: LDO3 {
+ regulator-name = "vdda-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_rtscts>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
+ dma-names = "rx", "tx";
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "peripheral";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_usdhc2_cd>;
+ bus-width = <4>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_vdd_3v3>;
+ voltage-ranges = <3300 3300>;
+ no-1-8-v;
+ fsl,wp-controller;
+};
+
+&usdhc3 { /* eMMC */
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_nvcc_nand>;
+ voltage-ranges = <3300 3300>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2
+ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2
+ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4-gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c2
+ MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c2
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart1_rtscts: uart1-rtsctsgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
+ MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_cd: usdhc2-cdgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--
2.39.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/6] arm: dts: karo: add karo imx8mp-karo-qsxp-qsbase4
2024-03-11 9:10 [PATCH 0/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
` (3 preceding siblings ...)
2024-03-11 9:10 ` [PATCH 4/6] arm: dts: karo: import dts for karo-qsxp-ml81 Stefan Kerkmann
@ 2024-03-11 9:10 ` Stefan Kerkmann
2024-03-11 10:05 ` Ahmad Fatoum
2024-03-11 9:10 ` [PATCH 6/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
5 siblings, 1 reply; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 9:10 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX
The Ka-Ro QSXP-QSBASE4[1] is the offical DK from Ka-Ro for their QSXP
i.MX8M Plus solder down system on module. It comes with an additional
Micrel KSZ9131 gigabit ethernet phy. The devicetree was adapted from the
offical Ka-Ro github[2], commit a49b38ec97854c0cd9cd83a9f4ae3b56e99a58b6.
[1]: https://karo-electronics.github.io/docs/getting-started/qsbase4/quickstart-qsbase4.html
[2]: https://github.com/karo-electronics/meta-karo-nxp.git
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
---
arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts | 86 ++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts b/arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts
new file mode 100644
index 0000000000..aa70d0aee0
--- /dev/null
+++ b/arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "imx8mp-karo-qsxp-ml81.dts"
+
+&{/} {
+ model = "Ka-Ro electronics QSXP-ML81-QSBASE4 (NXP i.MX8MP) Board";
+ compatible = "karo,imx8mp-qsxp-ml81-qsbase4", "karo,imx8mp-qsxp-ml81", "fsl,imx8mp";
+};
+
+&eqos {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_eqos>;
+ pinctrl-1 = <&pinctrl_eqos_sleep>;
+ phy-connection-type = "rgmii-id";
+ phy-handle = <ðphy1>;
+ phy-supply = <&ldo5_reg>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <100>;
+ reset-deassert-us = <250000>;
+ };
+ };
+};
+
+&usdhc2 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x140 /* PHY reset */
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x142
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x142
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x40000016
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x016
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x016
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x016
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x016
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x016
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x110 /* MODE0 */
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x150 /* MODE1 */
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x150 /* MODE2 */
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x150 /* MODE3 */
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x156 /* PHYAD2 */
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x000 /* CLK125_EN */
+ MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x110 /* LED_MODE */
+ >;
+ };
+
+ pinctrl_eqos_sleep: eqos-sleep-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x120
+ MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x120
+ MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x120
+ MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x120
+ MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x120
+ MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x120
+ MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x120
+ MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x120
+ MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x120
+ MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x120
+ MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x120
+ MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x120
+ MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x120
+ MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x120
+ MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x120
+ MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x120
+ >;
+ };
+};
--
2.39.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/6] arm: imx8mp: add karo electronics qsxp imx8mp som support
2024-03-11 9:10 [PATCH 0/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
` (4 preceding siblings ...)
2024-03-11 9:10 ` [PATCH 5/6] arm: dts: karo: add karo imx8mp-karo-qsxp-qsbase4 Stefan Kerkmann
@ 2024-03-11 9:10 ` Stefan Kerkmann
2024-03-11 10:13 ` Ahmad Fatoum
5 siblings, 1 reply; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 9:10 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX
From: Marc Kleine-Budde <mkl@pengutronix.de>
The Ka-Ro QSXP is a i.MX8M Plus solder down system on module. This
commit adds support for the SOM on the QSBASE4 RDK.
[1]: https://www.karo-electronics.de/qsxp
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/karo-qsxp-ml81/Makefile | 4 +
arch/arm/boards/karo-qsxp-ml81/board.c | 35 +
| 9 +
arch/arm/boards/karo-qsxp-ml81/lowlevel.c | 102 ++
arch/arm/boards/karo-qsxp-ml81/lowlevel.h | 8 +
arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c | 1597 ++++++++++++++++++++
arch/arm/dts/Makefile | 1 +
arch/arm/mach-imx/Kconfig | 10 +
images/Makefile.imx | 2 +
10 files changed, 1769 insertions(+)
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index e597b02be6..dbec2bcc26 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_MACH_HABA_KNX_LITE) += haba-knx/
obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/
obj-$(CONFIG_MACH_INNOCOMM_WB15) += innocomm-imx8mm-wb15/
obj-$(CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR) += kamstrup-mx7-concentrator/
+obj-$(CONFIG_MACH_KARO_QSXP_ML81) += karo-qsxp-ml81/
obj-$(CONFIG_MACH_KONTRON_SAMX6I) += kontron-samx6i/
obj-$(CONFIG_MACH_LENOVO_IX4_300D) += lenovo-ix4-300d/
obj-$(CONFIG_MACH_LUBBOCK) += lubbock/
diff --git a/arch/arm/boards/karo-qsxp-ml81/Makefile b/arch/arm/boards/karo-qsxp-ml81/Makefile
new file mode 100644
index 0000000000..10abebc539
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o lpddr4-timing.o
+obj-y += board.o
diff --git a/arch/arm/boards/karo-qsxp-ml81/board.c b/arch/arm/boards/karo-qsxp-ml81/board.c
new file mode 100644
index 0000000000..e9e3d46bf1
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/board.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
+
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <mach/imx/bbu.h>
+
+static int karo_qsxp_ml81_probe(struct device *dev)
+{
+ int emmc_bbu_flag = 0;
+
+ if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 2) {
+ of_device_enable_path("/chosen/environment-emmc");
+ emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ }
+
+ imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
+
+ return 0;
+}
+
+static const struct of_device_id karo_qsxp_ml81_of_match[] = {
+ { .compatible = "karo,imx8mp-qsxp-ml81-qsbase4" },
+ { /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(karo_qsxp_ml81_of_match);
+
+static struct driver karo_qsxp_ml81_board_driver = {
+ .name = "board-karo-qsxp-ml81",
+ .probe = karo_qsxp_ml81_probe,
+ .of_compatible = DRV_OF_COMPAT(karo_qsxp_ml81_of_match),
+};
+coredevice_platform_driver(karo_qsxp_ml81_board_driver);
--git a/arch/arm/boards/karo-qsxp-ml81/flash-header-karo-qsxp-ml81.imxcfg b/arch/arm/boards/karo-qsxp-ml81/flash-header-karo-qsxp-ml81.imxcfg
new file mode 100644
index 0000000000..da0892e52d
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/flash-header-karo-qsxp-ml81.imxcfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mp
+
+loadaddr 0x00920000
+max_load_size 0x3f000
+ivtofs 0x0
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/karo-qsxp-ml81/lowlevel.c b/arch/arm/boards/karo-qsxp-ml81/lowlevel.c
new file mode 100644
index 0000000000..47638718ad
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/lowlevel.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <asm/barebox-arm.h>
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <mach/imx/xload.h>
+#include <mfd/pca9450.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <soc/imx8m/ddr.h>
+
+#include "lowlevel.h"
+
+extern char __dtb_z_imx8mp_karo_qsxp_ml81_qsbase4_start[];
+
+#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+ MX8MP_PAD_CTL_FSEL)
+
+#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_PE | \
+ MX8MP_PAD_CTL_HYS | \
+ MX8MP_PAD_CTL_PUE | \
+ MX8MP_PAD_CTL_DSE6)
+
+static void setup_uart(void)
+{
+ void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR);
+
+ imx8m_early_setup_uart_clock();
+
+ imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL);
+ imx8m_uart_setup(uart);
+
+ pbl_set_putc(imx_uart_putc, uart);
+
+ putc_ll('>');
+}
+
+#define pca9450_mV_to_reg(mV) (((mV) - 600) * 10 / 125)
+#define pca9450_reg_to_mV(val) (((val) * 125 / 10) + 600)
+
+#define VDD_SOC_VAL pca9450_mV_to_reg(950)
+#define VDD_SOC_SLP_VAL pca9450_mV_to_reg(850)
+#define VDD_ARM_VAL pca9450_mV_to_reg(950)
+#define VDD_DRAM_VAL pca9450_mV_to_reg(950)
+
+static struct pmic_config pca9450_cfg[] = {
+ { PCA9450_BUCK123_DVS, 0x29 },
+ { PCA9450_BUCK1OUT_DVS0, VDD_SOC_VAL },
+ { PCA9450_BUCK1OUT_DVS1, VDD_SOC_SLP_VAL },
+ { PCA9450_BUCK2OUT_DVS0, VDD_ARM_VAL },
+ { PCA9450_BUCK3OUT_DVS0, VDD_DRAM_VAL },
+ { PCA9450_BUCK1CTRL, 0x59 },
+ { PCA9450_RESET_CTRL, 0xA1 },
+};
+
+static void power_init_board(void)
+{
+ struct pbl_i2c *i2c;
+
+ imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
+ imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
+
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+ i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
+
+ pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+}
+
+ENTRY_FUNCTION(start_karo_qsxp_ml81, r0, r1, r2)
+{
+ imx8mp_cpu_lowlevel_init();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ setup_uart();
+
+ /*
+ * If we are in EL3 we are running for the first time out of OCRAM,
+ * we'll need to initialize the DRAM and run TF-A (BL31). The TF-A
+ * will then jump to DRAM in EL2
+ */
+ if (current_el() == 3) {
+ imx8mp_early_clock_init();
+
+ power_init_board();
+
+ imx8mp_ddr_init(&karo_qsxp_ml81_dram_timing, DRAM_TYPE_LPDDR4);
+
+ imx8mp_load_and_start_image_via_tfa();
+ }
+
+ /* Standard entry we hit once we initialized both DDR and ATF */
+ imx8mm_barebox_entry(__dtb_z_imx8mp_karo_qsxp_ml81_qsbase4_start);
+}
diff --git a/arch/arm/boards/karo-qsxp-ml81/lowlevel.h b/arch/arm/boards/karo-qsxp-ml81/lowlevel.h
new file mode 100644
index 0000000000..37e5269653
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/lowlevel.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef KARO_QSXP_ML81_LOWLEVEL_H_
+#define KARO_QSXP_ML81_LOWLEVEL_H_
+
+extern struct dram_timing_info karo_qsxp_ml81_dram_timing;
+
+#endif
diff --git a/arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c b/arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c
new file mode 100644
index 0000000000..e5a927d1bb
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c
@@ -0,0 +1,1597 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+
+#include <soc/imx8m/lpddr4_define.h>
+
+#include "lowlevel.h"
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x1203 },
+ { 0x3d400024, 0x186a000 },
+ { 0x3d400064, 0x6100e0 },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc003061c },
+ { 0x3d4000d4, 0x9e0000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x210000 },
+ { 0x3d4000e8, 0x630048 },
+ { 0x3d4000ec, 0x140025 },
+ { 0x3d400100, 0x1a201b22 },
+ { 0x3d400104, 0x60633 },
+ { 0x3d40010c, 0xc0c000 },
+ { 0x3d400110, 0xf04080f },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0xe6 },
+ { 0x3d400144, 0xa00050 },
+ { 0x3d400180, 0x3200018 },
+ { 0x3d400184, 0x28061a8 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x1 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x5 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x2 },
+ { 0x100a5, 0x4 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x7 },
+ { 0x110a1, 0x6 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x5 },
+ { 0x110a4, 0x4 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x1 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x4 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x2 },
+ { 0x120a6, 0x6 },
+ { 0x120a7, 0x7 },
+ { 0x130a0, 0x1 },
+ { 0x130a1, 0x6 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x7 },
+ { 0x130a7, 0x0 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x2002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x20024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x1004d, 0x600 },
+ { 0x1014d, 0x600 },
+ { 0x1104d, 0x600 },
+ { 0x1114d, 0x600 },
+ { 0x1204d, 0x600 },
+ { 0x1214d, 0x600 },
+ { 0x1304d, 0x600 },
+ { 0x1314d, 0x600 },
+ { 0x10049, 0x69a },
+ { 0x10149, 0x69a },
+ { 0x11049, 0x69a },
+ { 0x11149, 0x69a },
+ { 0x12049, 0x69a },
+ { 0x12149, 0x69a },
+ { 0x13049, 0x69a },
+ { 0x13149, 0x69a },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x320 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x200f0, 0x0 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
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+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x303c },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x21 },
+ { 0x5401b, 0x4863 },
+ { 0x5401c, 0x2500 },
+ { 0x5401e, 0x14 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x21 },
+ { 0x54021, 0x4863 },
+ { 0x54022, 0x2500 },
+ { 0x54024, 0x14 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x212d },
+ { 0x54034, 0x6300 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x25 },
+ { 0x54037, 0x1400 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x212d },
+ { 0x5403a, 0x6300 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x25 },
+ { 0x5403d, 0x1400 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x303c },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x21 },
+ { 0x5401b, 0x4863 },
+ { 0x5401c, 0x2500 },
+ { 0x5401e, 0x14 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x21 },
+ { 0x54021, 0x4863 },
+ { 0x54022, 0x2500 },
+ { 0x54024, 0x14 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x212d },
+ { 0x54034, 0x6300 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x25 },
+ { 0x54037, 0x1400 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x212d },
+ { 0x5403a, 0x6300 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x25 },
+ { 0x5403d, 0x1400 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x1 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x478 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x68 },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x384 },
+ { 0x2000c, 0xc8 },
+ { 0x2000d, 0x7d0 },
+ { 0x2000e, 0x2c },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info karo_qsxp_ml81_dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3200, },
+};
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 67bc1e0b16..60562baff9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -36,6 +36,7 @@ lwl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
lwl-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o
lwl-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o
lwl-$(CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR) += imx7d-flex-concentrator-mfg.dtb.o
+lwl-$(CONFIG_MACH_KARO_QSXP_ML81) += imx8mp-karo-qsxp-ml81-qsbase4.dtb.o
lwl-$(CONFIG_MACH_KONTRON_SAMX6I) += imx6q-samx6i.dtb.o \
imx6dl-samx6i.dtb.o
lwl-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c455179dee..325b602114 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -606,6 +606,16 @@ config MACH_INNOCOMM_WB15
select USB_GADGET_DRIVER_ARC_PBL
imply AT803X_PHY
+config MACH_KARO_QSXP_ML81
+ bool "Karo QSXP ML81 (i.MX8MP) SOM on QSBASE4 Board"
+ select ARCH_IMX8MP
+ select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+ select FIRMWARE_IMX8MP_ATF
+ select ARM_SMCCC
+ select MCI_IMX_ESDHC_PBL
+ select IMX8M_DRAM
+ select I2C_IMX_EARLY
+
config MACH_MNT_REFORM
bool "MNT Reform"
select ARCH_IMX8MQ
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 1b85112ff2..ee7edd02d3 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -472,6 +472,8 @@ $(call build_imx8m_habv4img, CONFIG_MACH_NXP_IMX8MN_EVK, start_nxp_imx8mn_evk, n
# ----------------------- i.MX8mp based boards --------------------------
$(call build_imx8m_habv4img, CONFIG_MACH_NXP_IMX8MP_EVK, start_nxp_imx8mp_evk, nxp-imx8mp-evk/flash-header-imx8mp-evk, nxp-imx8mp-evk)
+$(call build_imx8m_habv4img, CONFIG_MACH_KARO_QSXP_ML81, start_karo_qsxp_ml81, karo-qsxp-ml81/flash-header-karo-qsxp-ml81, karo-qsxp-ml81)
+
$(call build_imx8m_habv4img, CONFIG_MACH_SKOV_IMX8MP, start_skov_imx8mp, skov-imx8mp/flash-header-skov-imx8mp, skov-imx8mp)
$(call build_imx8m_habv4img, CONFIG_MACH_TQ_MBA8MPXL, start_tqma8mpxl, tqma8mpxl/flash-header-tqma8mpxl, tqma8mpxl)
--
2.39.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/6] arm: dts: karo: import dts for karo-qsxp-ml81
2024-03-11 9:10 ` [PATCH 4/6] arm: dts: karo: import dts for karo-qsxp-ml81 Stefan Kerkmann
@ 2024-03-11 10:02 ` Ahmad Fatoum
2024-03-11 14:23 ` Stefan Kerkmann
0 siblings, 1 reply; 17+ messages in thread
From: Ahmad Fatoum @ 2024-03-11 10:02 UTC (permalink / raw)
To: Stefan Kerkmann, Sascha Hauer, BAREBOX
Hello Stefan,
On 11.03.24 10:10, Stefan Kerkmann wrote:
> From: Marc Kleine-Budde <mkl@pengutronix.de>
>
> This imports the device tree for the Ka-Ro QSXP, which is a i.MX8M Plus
> solder down system on module. The sources have been adapted from the
> offical Ka-Ro github[1], commit a49b38ec97854c0cd9cd83a9f4ae3b56e99a58b6.
>
> [1]: https://github.com/karo-electronics/meta-karo-nxp.git
To make it easier to sync with Linux, once the device tree goes upstream,
could you separate the barebox-specific changes into a separate file?
> + model = "Ka-Ro electronics QSXP-ML81 (NXP i.MX8MP) module";
> + compatible = "karo,imx8mp-qsxp-ml81", "fsl,imx8mp";
Add a compatible for the SoM here: "karo,imx8mp-qsxp".
> +&usb_dwc3_0 {
> + dr_mode = "peripheral";
I think this should rather be moved into the DTS, because it's a property
of the baseboard, how he OTG is usd.
> +&usdhc3 { /* eMMC */
> + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
> + assigned-clock-rates = <400000000>;
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> + bus-width = <8>;
> + no-sd;
> + no-sdio;
> + vmmc-supply = <®_vdd_3v3>;
> + vqmmc-supply = <®_nvcc_nand>;
> + voltage-ranges = <3300 3300>;
I never used voltage-ranges, but this might be wrong. You can't do
200MHz with 3.3v and vqmmc-supply is fixed already at 1.8v, so here
seem to be no voltage shifters involved at all?
Either way, it doesn't matter to barebox.
> + non-removable;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
> + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
> + >;
> + };
> +
> + pinctrl_i2c1_gpio: i2c1-gpiogrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
> + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
> + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
> + >;
> + };
> +
> + pinctrl_i2c2_gpio: i2c2-gpiogrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2
> + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
> + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
> + >;
> + };
> +
> + pinctrl_i2c3_gpio: i2c3-gpiogrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2
> + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
> + >;
> + };
> +
> + pinctrl_i2c4: i2c4grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
> + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
> + >;
> + };
> +
> + pinctrl_i2c4_gpio: i2c4-gpiogrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c2
> + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c2
> + >;
> + };
> +
> + pinctrl_pmic: pmicgrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
> + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
> + >;
> + };
> +
> + pinctrl_uart1_rtscts: uart1-rtsctsgrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
> + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
> + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
> + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
> + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
> + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
> + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
> + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
> + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc2_cd: usdhc2-cdgrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
> + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
> + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
> + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
> + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
> + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
> + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
> + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
> + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
> + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
> + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
> + >;
> + };
> +
> + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
> + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
> + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
> + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
> + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
> + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
> + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
> + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
> + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
> + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
> + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
> + >;
> + };
> +
> + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
> + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
> + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
> + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
> + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
> + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
> + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
> + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
> + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
> + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
> + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
> + >;
> + };
> +};
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/6] arm: dts: karo: add karo imx8mp-karo-qsxp-qsbase4
2024-03-11 9:10 ` [PATCH 5/6] arm: dts: karo: add karo imx8mp-karo-qsxp-qsbase4 Stefan Kerkmann
@ 2024-03-11 10:05 ` Ahmad Fatoum
2024-03-11 13:25 ` Stefan Kerkmann
0 siblings, 1 reply; 17+ messages in thread
From: Ahmad Fatoum @ 2024-03-11 10:05 UTC (permalink / raw)
To: Stefan Kerkmann, Sascha Hauer, BAREBOX
On 11.03.24 10:10, Stefan Kerkmann wrote:
> +/dts-v1/;
> +
> +#include "imx8mp-karo-qsxp-ml81.dts"
> +
> +&{/} {
While not wrong, this is unnecessary. We know that there is a / already.
> + model = "Ka-Ro electronics QSXP-ML81-QSBASE4 (NXP i.MX8MP) Board";
> + compatible = "karo,imx8mp-qsxp-ml81-qsbase4", "karo,imx8mp-qsxp-ml81", "fsl,imx8mp";
Ok, this confuses me. I thought QSXP is the SoM. What's ML81?
> +&usdhc2 {
> + status = "disabled";
> +};
Nitpick: Should be disabled in SoM, as it requires outside hardware to be functional.
> +
> +&iomuxc {
> + pinctrl_eqos: eqosgrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x140 /* PHY reset */
> + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x142
> + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x142
> + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x40000016
> + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x016
> + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x016
> + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x016
> + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x016
> + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x016
> + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x110 /* MODE0 */
> + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x150 /* MODE1 */
> + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x150 /* MODE2 */
> + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x150 /* MODE3 */
> + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x156 /* PHYAD2 */
> + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x000 /* CLK125_EN */
> + MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x110 /* LED_MODE */
> + >;
> + };
> +
> + pinctrl_eqos_sleep: eqos-sleep-grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x120
> + MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x120
> + MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x120
> + MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x120
> + MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x120
> + MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x120
> + MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x120
> + MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x120
> + MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x120
> + MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x120
> + MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x120
> + MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x120
> + MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x120
> + MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x120
> + MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x120
> + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x120
> + >;
> + };
> +};
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/6] arm: imx8mp: add karo electronics qsxp imx8mp som support
2024-03-11 9:10 ` [PATCH 6/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
@ 2024-03-11 10:13 ` Ahmad Fatoum
2024-03-11 13:32 ` Stefan Kerkmann
0 siblings, 1 reply; 17+ messages in thread
From: Ahmad Fatoum @ 2024-03-11 10:13 UTC (permalink / raw)
To: Stefan Kerkmann, Sascha Hauer, BAREBOX
Hello Stefan,
On 11.03.24 10:10, Stefan Kerkmann wrote:
> From: Marc Kleine-Budde <mkl@pengutronix.de>
>
> The Ka-Ro QSXP is a i.MX8M Plus solder down system on module. This
> commit adds support for the SOM on the QSBASE4 RDK.
>
> [1]: https://www.karo-electronics.de/qsxp
>
> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
> Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
> ---
> arch/arm/boards/Makefile | 1 +
> arch/arm/boards/karo-qsxp-ml81/Makefile | 4 +
> arch/arm/boards/karo-qsxp-ml81/board.c | 35 +
> .../flash-header-karo-qsxp-ml81.imxcfg | 9 +
> arch/arm/boards/karo-qsxp-ml81/lowlevel.c | 102 ++
> arch/arm/boards/karo-qsxp-ml81/lowlevel.h | 8 +
> arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c | 1597 ++++++++++++++++++++
If QSXP is the SoM name, rename the folder name to drop ml81.
> +
> + /*
> + * If we are in EL3 we are running for the first time out of OCRAM,
> + * we'll need to initialize the DRAM and run TF-A (BL31). The TF-A
> + * will then jump to DRAM in EL2
> + */
> + if (current_el() == 3) {
> + imx8mp_early_clock_init();
> +
> + power_init_board();
> +
> + imx8mp_ddr_init(&karo_qsxp_ml81_dram_timing, DRAM_TYPE_LPDDR4);
> +
> + imx8mp_load_and_start_image_via_tfa();
> + }
> +
> + /* Standard entry we hit once we initialized both DDR and ATF */
> + imx8mm_barebox_entry(__dtb_z_imx8mp_karo_qsxp_ml81_qsbase4_start);
s/imx8mm/imx8mp/
> +/* ddr phy trained csr */
> +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
This is unused. See commit
975acf1bafba ("ARM: i.MX8M: delete unused per-board ddr_ddrphy_trained_csr array")
Unless your value differ from the default, just drop this from here.
> +static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> + {
> + /* P0 3200mts 1D */
> + .drate = 3200,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp0_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> + },
> + {
> + /* P0 3200mts 2D */
> + .drate = 3200,
> + .fw_type = FW_2D_IMAGE,
> + .fsp_cfg = ddr_fsp0_2d_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> + },
JFYI, if you want to dynamic frequency scaling for DDR, you'll need some
more entries here.
> +config MACH_KARO_QSXP_ML81
Please enable this in imx_v8_defconfig and multi_v8_defconfig for CI coverage.
Cheers,
Ahmad
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/6] arm: dts: karo: add karo imx8mp-karo-qsxp-qsbase4
2024-03-11 10:05 ` Ahmad Fatoum
@ 2024-03-11 13:25 ` Stefan Kerkmann
0 siblings, 0 replies; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 13:25 UTC (permalink / raw)
To: Ahmad Fatoum, Sascha Hauer, BAREBOX
Hello Ahmad,
On 11.03.24 11:05, Ahmad Fatoum wrote:
> On 11.03.24 10:10, Stefan Kerkmann wrote:
>> +/dts-v1/;
>> +
>> +#include "imx8mp-karo-qsxp-ml81.dts"
>> +
>> +&{/} {
>
> While not wrong, this is unnecessary. We know that there is a / already.
>
Ack.
>> + model = "Ka-Ro electronics QSXP-ML81-QSBASE4 (NXP i.MX8MP) Board";
>> + compatible = "karo,imx8mp-qsxp-ml81-qsbase4", "karo,imx8mp-qsxp-ml81", "fsl,imx8mp";
>
> Ok, this confuses me. I thought QSXP is the SoM. What's ML81?
The official part number from karo is `QSXP-ML81`, it is just not
mentioned upfront on their product page - but you'll see it under
`Varianten` at https://www.karo-electronics.de/qsxp#c12158. Therefore I
vote to keep the `ml81` part.
>
>
>> +&usdhc2 {
>> + status = "disabled";
>> +};
>
> Nitpick: Should be disabled in SoM, as it requires outside hardware to be functional.
>
Ack.
>> +
>> +&iomuxc {
>> + pinctrl_eqos: eqosgrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x140 /* PHY reset */
>> + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x142
>> + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x142
>> + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x40000016
>> + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x016
>> + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x016
>> + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x016
>> + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x016
>> + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x016
>> + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x110 /* MODE0 */
>> + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x150 /* MODE1 */
>> + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x150 /* MODE2 */
>> + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x150 /* MODE3 */
>> + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x156 /* PHYAD2 */
>> + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x000 /* CLK125_EN */
>> + MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x110 /* LED_MODE */
>> + >;
>> + };
>> +
>> + pinctrl_eqos_sleep: eqos-sleep-grp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x120
>> + MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x120
>> + MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x120
>> + MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x120
>> + MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x120
>> + MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x120
>> + MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x120
>> + MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x120
>> + MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x120
>> + MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x120
>> + MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x120
>> + MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x120
>> + MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x120
>> + MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x120
>> + MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x120
>> + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x120
>> + >;
>> + };
>> +};
>>
>
--
Pengutronix e.K. | Stefan Kerkmann |
Steuerwalder Str. 21 | https://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-128 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/6] arm: imx8mp: add karo electronics qsxp imx8mp som support
2024-03-11 10:13 ` Ahmad Fatoum
@ 2024-03-11 13:32 ` Stefan Kerkmann
2024-03-11 13:58 ` Ahmad Fatoum
0 siblings, 1 reply; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 13:32 UTC (permalink / raw)
To: Ahmad Fatoum, Sascha Hauer, BAREBOX
Hello Ahmad,
On 11.03.24 11:13, Ahmad Fatoum wrote:
> Hello Stefan,
>
> On 11.03.24 10:10, Stefan Kerkmann wrote:
>> From: Marc Kleine-Budde <mkl@pengutronix.de>
>>
>> The Ka-Ro QSXP is a i.MX8M Plus solder down system on module. This
>> commit adds support for the SOM on the QSBASE4 RDK.
>>
>> [1]: https://www.karo-electronics.de/qsxp
>>
>> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
>> Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
>> ---
>> arch/arm/boards/Makefile | 1 +
>> arch/arm/boards/karo-qsxp-ml81/Makefile | 4 +
>> arch/arm/boards/karo-qsxp-ml81/board.c | 35 +
>> .../flash-header-karo-qsxp-ml81.imxcfg | 9 +
>> arch/arm/boards/karo-qsxp-ml81/lowlevel.c | 102 ++
>> arch/arm/boards/karo-qsxp-ml81/lowlevel.h | 8 +
>> arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c | 1597 ++++++++++++++++++++
>
> If QSXP is the SoM name, rename the folder name to drop ml81.
>
See reply to patch 5/6, the full manufacturer part number is `QSXP-ML81`
therefore I vote to keep the `ml81` part.
>> +
>> + /*
>> + * If we are in EL3 we are running for the first time out of OCRAM,
>> + * we'll need to initialize the DRAM and run TF-A (BL31). The TF-A
>> + * will then jump to DRAM in EL2
>> + */
>> + if (current_el() == 3) {
>> + imx8mp_early_clock_init();
>> +
>> + power_init_board();
>> +
>> + imx8mp_ddr_init(&karo_qsxp_ml81_dram_timing, DRAM_TYPE_LPDDR4);
>> +
>> + imx8mp_load_and_start_image_via_tfa();
>> + }
>> +
>> + /* Standard entry we hit once we initialized both DDR and ATF */
>> + imx8mm_barebox_entry(__dtb_z_imx8mp_karo_qsxp_ml81_qsbase4_start);
>
> s/imx8mm/imx8mp/
>
Ack.
>> +/* ddr phy trained csr */
>> +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
>
> This is unused. See commit
> 975acf1bafba ("ARM: i.MX8M: delete unused per-board ddr_ddrphy_trained_csr array")
>
> Unless your value differ from the default, just drop this from here.
>
Ack.
>> +static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
>> + {
>> + /* P0 3200mts 1D */
>> + .drate = 3200,
>> + .fw_type = FW_1D_IMAGE,
>> + .fsp_cfg = ddr_fsp0_cfg,
>> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
>> + },
>> + {
>> + /* P0 3200mts 2D */
>> + .drate = 3200,
>> + .fw_type = FW_2D_IMAGE,
>> + .fsp_cfg = ddr_fsp0_2d_cfg,
>> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
>> + },
>
> JFYI, if you want to dynamic frequency scaling for DDR, you'll need some
> more entries here.
>
I'm unfamiliar with dynamic frequency scaling, so I'm not sure if we
need/want more for a first support of this SOM?
>> +config MACH_KARO_QSXP_ML81
>
> Please enable this in imx_v8_defconfig and multi_v8_defconfig for CI coverage.
>
Ack.
>
> Cheers,
> Ahmad
>
Cheers,
Stefan
--
Pengutronix e.K. | Stefan Kerkmann |
Steuerwalder Str. 21 | https://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-128 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/6] arm: imx8mp: add karo electronics qsxp imx8mp som support
2024-03-11 13:32 ` Stefan Kerkmann
@ 2024-03-11 13:58 ` Ahmad Fatoum
2024-03-11 14:01 ` Stefan Kerkmann
0 siblings, 1 reply; 17+ messages in thread
From: Ahmad Fatoum @ 2024-03-11 13:58 UTC (permalink / raw)
To: Stefan Kerkmann, Sascha Hauer, BAREBOX
Hello Stefan,
On 11.03.24 14:32, Stefan Kerkmann wrote:
> Hello Ahmad,
>
> On 11.03.24 11:13, Ahmad Fatoum wrote:
>> Hello Stefan,
>>
>> On 11.03.24 10:10, Stefan Kerkmann wrote:
>>> From: Marc Kleine-Budde <mkl@pengutronix.de>
>>>
>>> The Ka-Ro QSXP is a i.MX8M Plus solder down system on module. This
>>> commit adds support for the SOM on the QSBASE4 RDK.
>>>
>>> [1]: https://www.karo-electronics.de/qsxp
>>>
>>> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
>>> Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
>>> ---
>>> arch/arm/boards/Makefile | 1 +
>>> arch/arm/boards/karo-qsxp-ml81/Makefile | 4 +
>>> arch/arm/boards/karo-qsxp-ml81/board.c | 35 +
>>> .../flash-header-karo-qsxp-ml81.imxcfg | 9 +
>>> arch/arm/boards/karo-qsxp-ml81/lowlevel.c | 102 ++
>>> arch/arm/boards/karo-qsxp-ml81/lowlevel.h | 8 +
>>> arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c | 1597 ++++++++++++++++++++
>>
>> If QSXP is the SoM name, rename the folder name to drop ml81.
>>
>
> See reply to patch 5/6, the full manufacturer part number is `QSXP-ML81`
> therefore I vote to keep the `ml81` part.
Ok, can you call it QSXP-ML81 in the commit message?
>> JFYI, if you want to dynamic frequency scaling for DDR, you'll need some
>> more entries here.
>>
>
> I'm unfamiliar with dynamic frequency scaling, so I'm not sure if we
> need/want more for a first support of this SOM?
No, you don't need more. This is Just For Your Information. Dynamic Frequency
Scaling can be useful to reduce power usage.
Cheers,
Ahmad
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/6] arm: imx8mp: add karo electronics qsxp imx8mp som support
2024-03-11 13:58 ` Ahmad Fatoum
@ 2024-03-11 14:01 ` Stefan Kerkmann
0 siblings, 0 replies; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 14:01 UTC (permalink / raw)
To: Ahmad Fatoum, Sascha Hauer, BAREBOX
Hello Ahmad,
On 11.03.24 14:58, Ahmad Fatoum wrote:
> Hello Stefan,
>
> On 11.03.24 14:32, Stefan Kerkmann wrote:
>> Hello Ahmad,
>>
>> On 11.03.24 11:13, Ahmad Fatoum wrote:
>>> Hello Stefan,
>>>
>>> On 11.03.24 10:10, Stefan Kerkmann wrote:
>>>> From: Marc Kleine-Budde <mkl@pengutronix.de>
>>>>
>>>> The Ka-Ro QSXP is a i.MX8M Plus solder down system on module. This
>>>> commit adds support for the SOM on the QSBASE4 RDK.
>>>>
>>>> [1]: https://www.karo-electronics.de/qsxp
>>>>
>>>> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
>>>> Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
>>>> ---
>>>> arch/arm/boards/Makefile | 1 +
>>>> arch/arm/boards/karo-qsxp-ml81/Makefile | 4 +
>>>> arch/arm/boards/karo-qsxp-ml81/board.c | 35 +
>>>> .../flash-header-karo-qsxp-ml81.imxcfg | 9 +
>>>> arch/arm/boards/karo-qsxp-ml81/lowlevel.c | 102 ++
>>>> arch/arm/boards/karo-qsxp-ml81/lowlevel.h | 8 +
>>>> arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c | 1597 ++++++++++++++++++++
>>>
>>> If QSXP is the SoM name, rename the folder name to drop ml81.
>>>
>>
>> See reply to patch 5/6, the full manufacturer part number is `QSXP-ML81`
>> therefore I vote to keep the `ml81` part.
>
> Ok, can you call it QSXP-ML81 in the commit message?
>
Sure, I will change it :-).
>>> JFYI, if you want to dynamic frequency scaling for DDR, you'll need some
>>> more entries here.
>>>
>>
>> I'm unfamiliar with dynamic frequency scaling, so I'm not sure if we
>> need/want more for a first support of this SOM?
>
> No, you don't need more. This is Just For Your Information. Dynamic Frequency
> Scaling can be useful to reduce power usage.
>
Alright, thanks for the heads-up! Depending on the use case of the
product this might become handy in the future.
>
> Cheers,
> Ahmad
>
>
Cheers,
Stefan
--
Pengutronix e.K. | Stefan Kerkmann |
Steuerwalder Str. 21 | https://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-128 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/6] arm: dts: karo: import dts for karo-qsxp-ml81
2024-03-11 10:02 ` Ahmad Fatoum
@ 2024-03-11 14:23 ` Stefan Kerkmann
2024-03-11 14:33 ` Ahmad Fatoum
0 siblings, 1 reply; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 14:23 UTC (permalink / raw)
To: Ahmad Fatoum, Sascha Hauer, BAREBOX
Hello Ahmad,
On 11.03.24 11:02, Ahmad Fatoum wrote:
> Hello Stefan,
>
> On 11.03.24 10:10, Stefan Kerkmann wrote:
>> From: Marc Kleine-Budde <mkl@pengutronix.de>
>>
>> This imports the device tree for the Ka-Ro QSXP, which is a i.MX8M Plus
>> solder down system on module. The sources have been adapted from the
>> offical Ka-Ro github[1], commit a49b38ec97854c0cd9cd83a9f4ae3b56e99a58b6.
>>
>> [1]: https://github.com/karo-electronics/meta-karo-nxp.git
>
> To make it easier to sync with Linux, once the device tree goes upstream,
> could you separate the barebox-specific changes into a separate file?
>
Ack.
>> + model = "Ka-Ro electronics QSXP-ML81 (NXP i.MX8MP) module";
>> + compatible = "karo,imx8mp-qsxp-ml81", "fsl,imx8mp";
>
> Add a compatible for the SoM here: "karo,imx8mp-qsxp".
>
See reply to patch 5/6, the full manufacturer part number is `QSXP-ML81`
therefore I don't think that dropping the `ml81` part is necessary here?
>> +&usb_dwc3_0 {
>> + dr_mode = "peripheral";
>
> I think this should rather be moved into the DTS, because it's a property
> of the baseboard, how he OTG is usd.
>
>
Ack.
>> +&usdhc3 { /* eMMC */
>> + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
>> + assigned-clock-rates = <400000000>;
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> + pinctrl-0 = <&pinctrl_usdhc3>;
>> + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
>> + bus-width = <8>;
>> + no-sd;
>> + no-sdio;
>> + vmmc-supply = <®_vdd_3v3>;
>> + vqmmc-supply = <®_nvcc_nand>;
>> + voltage-ranges = <3300 3300>;
>
> I never used voltage-ranges, but this might be wrong. You can't do
> 200MHz with 3.3v and vqmmc-supply is fixed already at 1.8v, so here
> seem to be no voltage shifters involved at all?
>
You're right, AFAIK the eMMC JEDEC standard mandates 1.8V IOs for HS200
mode. For DDR mode the IO voltage can be 3.3V or 1.8V, according to the
datasheet of the used THGBMNG5D1LBAIL eMMC (if the product pictures are
anything to go by). So the correct voltage ranges property would be
`voltage-ranges = <1800 1800 3300 3300>`?
The line itself was copied verbatim from
https://github.com/karo-electronics/meta-karo-nxp/blob/mickledore/recipes-kernel/linux/linux-karo-6.1/mx8-nxp-bsp/dts/freescale/imx8mp-karo.dtsi#L263
> Either way, it doesn't matter to barebox.
So in the end we just delete it?
>> + non-removable;
>> + status = "okay";
>> +};
>> +
>> +&wdog1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_wdog>;
>> + fsl,ext-reset-output;
>> + status = "okay";
>> +};
>> +
>> +&iomuxc {
>> + pinctrl_i2c1: i2c1grp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
>> + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>> + >;
>> + };
>> +
>> + pinctrl_i2c1_gpio: i2c1-gpiogrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
>> + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
>> + >;
>> + };
>> +
>> + pinctrl_i2c2: i2c2grp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
>> + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>> + >;
>> + };
>> +
>> + pinctrl_i2c2_gpio: i2c2-gpiogrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2
>> + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2
>> + >;
>> + };
>> +
>> + pinctrl_i2c3: i2c3grp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
>> + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>> + >;
>> + };
>> +
>> + pinctrl_i2c3_gpio: i2c3-gpiogrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2
>> + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
>> + >;
>> + };
>> +
>> + pinctrl_i2c4: i2c4grp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
>> + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
>> + >;
>> + };
>> +
>> + pinctrl_i2c4_gpio: i2c4-gpiogrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c2
>> + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c2
>> + >;
>> + };
>> +
>> + pinctrl_pmic: pmicgrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>> + >;
>> + };
>> +
>> + pinctrl_uart1: uart1grp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
>> + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
>> + >;
>> + };
>> +
>> + pinctrl_uart1_rtscts: uart1-rtsctsgrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
>> + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
>> + >;
>> + };
>> +
>> + pinctrl_uart2: uart2grp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
>> + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>> + >;
>> + };
>> +
>> + pinctrl_uart4: uart4grp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
>> + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
>> + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
>> + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
>> + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
>> + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
>> + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_cd: usdhc2-cdgrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3: usdhc3grp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
>> + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
>> + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
>> + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
>> + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
>> + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
>> + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
>> + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
>> + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
>> + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
>> + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
>> + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
>> + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
>> + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
>> + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
>> + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
>> + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
>> + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
>> + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
>> + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
>> + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
>> + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
>> + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
>> + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
>> + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
>> + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
>> + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
>> + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
>> + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
>> + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
>> + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>> + >;
>> + };
>> +
>> + pinctrl_wdog: wdoggrp {
>> + fsl,pins = <
>> + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>> + >;
>> + };
>> +};
>>
>
Cheers,
Stefan
--
Pengutronix e.K. | Stefan Kerkmann |
Steuerwalder Str. 21 | https://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-128 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/6] arm: dts: karo: import dts for karo-qsxp-ml81
2024-03-11 14:23 ` Stefan Kerkmann
@ 2024-03-11 14:33 ` Ahmad Fatoum
2024-03-11 14:48 ` Stefan Kerkmann
0 siblings, 1 reply; 17+ messages in thread
From: Ahmad Fatoum @ 2024-03-11 14:33 UTC (permalink / raw)
To: Stefan Kerkmann, Sascha Hauer, BAREBOX
Hello Stefan,
On 11.03.24 15:23, Stefan Kerkmann wrote:
> Hello Ahmad,
>
> On 11.03.24 11:02, Ahmad Fatoum wrote:
>> Hello Stefan,
>>
>> On 11.03.24 10:10, Stefan Kerkmann wrote:
>>> From: Marc Kleine-Budde <mkl@pengutronix.de>
>>>
>>> This imports the device tree for the Ka-Ro QSXP, which is a i.MX8M Plus
>>> solder down system on module. The sources have been adapted from the
>>> offical Ka-Ro github[1], commit a49b38ec97854c0cd9cd83a9f4ae3b56e99a58b6.
>>>
>>> [1]: https://github.com/karo-electronics/meta-karo-nxp.git
>>
>> To make it easier to sync with Linux, once the device tree goes upstream,
>> could you separate the barebox-specific changes into a separate file?
>>
>
> Ack.
>
>>> + model = "Ka-Ro electronics QSXP-ML81 (NXP i.MX8MP) module";
>>> + compatible = "karo,imx8mp-qsxp-ml81", "fsl,imx8mp";
>>
>> Add a compatible for the SoM here: "karo,imx8mp-qsxp".
Then, why is it a DTS and not a DTSI?
> You're right, AFAIK the eMMC JEDEC standard mandates 1.8V IOs for HS200
> mode. For DDR mode the IO voltage can be 3.3V or 1.8V, according to the
> datasheet of the used THGBMNG5D1LBAIL eMMC (if the product pictures are
> anything to go by). So the correct voltage ranges property would be
> `voltage-ranges = <1800 1800 3300 3300>`?
Your I/O Voltage (vccq) is fixed at 1.8V, so 3300 sounds wrong.
> The line itself was copied verbatim from
> https://github.com/karo-electronics/meta-karo-nxp/blob/mickledore/recipes-kernel/linux/linux-karo-6.1/mx8-nxp-bsp/dts/freescale/imx8mp-karo.dtsi#L263
>
>
>> Either way, it doesn't matter to barebox.
> So in the end we just delete it?
Just delete it.
Cheers,
Ahmad
>
>>> + non-removable;
>>> + status = "okay";
>>> +};
>>> +
>>> +&wdog1 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_wdog>;
>>> + fsl,ext-reset-output;
>>> + status = "okay";
>>> +};
>>> +
>>> +&iomuxc {
>>> + pinctrl_i2c1: i2c1grp {
>>> + fsl,pins = <
>>> + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
>>> + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>>> + >;
>>> + };
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/6] arm: dts: karo: import dts for karo-qsxp-ml81
2024-03-11 14:33 ` Ahmad Fatoum
@ 2024-03-11 14:48 ` Stefan Kerkmann
0 siblings, 0 replies; 17+ messages in thread
From: Stefan Kerkmann @ 2024-03-11 14:48 UTC (permalink / raw)
To: Ahmad Fatoum, Sascha Hauer, BAREBOX
Hello Ahmad,
On 11.03.24 15:33, Ahmad Fatoum wrote:
> Hello Stefan,
>
> On 11.03.24 15:23, Stefan Kerkmann wrote:
>> Hello Ahmad,
>>
>> On 11.03.24 11:02, Ahmad Fatoum wrote:
>>> Hello Stefan,
>>>
>>> On 11.03.24 10:10, Stefan Kerkmann wrote:
>>>> From: Marc Kleine-Budde <mkl@pengutronix.de>
>>>>
>>>> This imports the device tree for the Ka-Ro QSXP, which is a i.MX8M Plus
>>>> solder down system on module. The sources have been adapted from the
>>>> offical Ka-Ro github[1], commit a49b38ec97854c0cd9cd83a9f4ae3b56e99a58b6.
>>>>
>>>> [1]: https://github.com/karo-electronics/meta-karo-nxp.git
>>>
>>> To make it easier to sync with Linux, once the device tree goes upstream,
>>> could you separate the barebox-specific changes into a separate file?
>>>
>>
>> Ack.
>>
>>>> + model = "Ka-Ro electronics QSXP-ML81 (NXP i.MX8MP) module";
>>>> + compatible = "karo,imx8mp-qsxp-ml81", "fsl,imx8mp";
>>>
>>> Add a compatible for the SoM here: "karo,imx8mp-qsxp".
>
> Then, why is it a DTS and not a DTSI?
>
AFAIK, this was a request from Marc to keep it as a DTS. I have no
strong opinion here.
>
>> You're right, AFAIK the eMMC JEDEC standard mandates 1.8V IOs for HS200
>> mode. For DDR mode the IO voltage can be 3.3V or 1.8V, according to the
>> datasheet of the used THGBMNG5D1LBAIL eMMC (if the product pictures are
>> anything to go by). So the correct voltage ranges property would be
>> `voltage-ranges = <1800 1800 3300 3300>`?
>
> Your I/O Voltage (vccq) is fixed at 1.8V, so 3300 sounds wrong.
>
Alright, but what if it wasn't and was adjustable? Just asking out of
curiosity.
>> The line itself was copied verbatim from
>> https://github.com/karo-electronics/meta-karo-nxp/blob/mickledore/recipes-kernel/linux/linux-karo-6.1/mx8-nxp-bsp/dts/freescale/imx8mp-karo.dtsi#L263
>>
>>
>>> Either way, it doesn't matter to barebox.
>> So in the end we just delete it?
>
> Just delete it.
>
Ack.
> Cheers,
> Ahmad
>
>>
>>>> + non-removable;
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&wdog1 {
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&pinctrl_wdog>;
>>>> + fsl,ext-reset-output;
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&iomuxc {
>>>> + pinctrl_i2c1: i2c1grp {
>>>> + fsl,pins = <
>>>> + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
>>>> + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>>>> + >;
>>>> + };
>
>
Cheers,
Stefan
--
Pengutronix e.K. | Stefan Kerkmann |
Steuerwalder Str. 21 | https://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-128 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2024-03-11 14:48 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-03-11 9:10 [PATCH 0/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 1/6] of: introduce of_property_read_s32 Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 2/6] net: phy: micrel: update id table from Linux kernel Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 3/6] net: phy: micrel: add support for ksz9131 phy Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 4/6] arm: dts: karo: import dts for karo-qsxp-ml81 Stefan Kerkmann
2024-03-11 10:02 ` Ahmad Fatoum
2024-03-11 14:23 ` Stefan Kerkmann
2024-03-11 14:33 ` Ahmad Fatoum
2024-03-11 14:48 ` Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 5/6] arm: dts: karo: add karo imx8mp-karo-qsxp-qsbase4 Stefan Kerkmann
2024-03-11 10:05 ` Ahmad Fatoum
2024-03-11 13:25 ` Stefan Kerkmann
2024-03-11 9:10 ` [PATCH 6/6] arm: imx8mp: add karo electronics qsxp imx8mp som support Stefan Kerkmann
2024-03-11 10:13 ` Ahmad Fatoum
2024-03-11 13:32 ` Stefan Kerkmann
2024-03-11 13:58 ` Ahmad Fatoum
2024-03-11 14:01 ` Stefan Kerkmann
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