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X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-104.4 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE, USER_IN_WELCOMELIST,USER_IN_WHITELIST autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH 0/9] tlsf: use 8-byte alignment for normal malloc allocations X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) Ahmad Fatoum writes: > TLSF currently uses only 4-byte alignment on 32-bit platforms, which isn't > enough for ldrd/strd on ARMv7. This series reworks TLSF a bit, so we always > have at least 8 byte alignment. dlmalloc already has 8 byte alignment > minimum, so nothing to do there. I am wondering whether alignment should be increased on 64 bit archs to 16 bytes as well. ARMv8 spec [1] says | exclusive pair access must be aligned to twice the data size, that is, | 128 bits for a pair of 64-bit values. A github issue [2] mentions this alignment too. > While this fixes real issues like what Enrico ran into, I'd suggest we only > this be taken into next only after v2022.10.0 is tagged, This is ok for me; the issue disappeared with reverting the zstd patch. Enrico Footnotes: [1] https://developer.arm.com/documentation/den0024/a/An-Introduction-to-the-ARMv8-Instruction-Sets/The-ARMv8-instruction-sets/Addressing [2] https://github.com/mattconte/tlsf/issues/16 -- SIGMA Chemnitz GmbH Registergericht: Amtsgericht Chemnitz HRB 1750 Am Erlenwald 13 Geschaeftsfuehrer: Grit Freitag, Frank Pyritz 09128 Chemnitz