From: Renaud Barbier <renaud.barbier@abaco.com> To: barebox@lists.infradead.org Cc: Renaud Barbier <renaud.barbier@abaco.com> Subject: [PATCH 1/3] ARM: atomic.h: add 64-bit counter support Date: Fri, 13 Aug 2021 09:16:46 +0100 [thread overview] Message-ID: <1628842608-17031-2-git-send-email-renaud.barbier@abaco.com> (raw) In-Reply-To: <1628842608-17031-1-git-send-email-renaud.barbier@abaco.com> In preparation for the introduction of the FSL IFC nand driver for the layerscape CPU, add 64-bit counter support. Remove functions calling undefined functions. Signed-off-by: Renaud Barbier <renaud.barbier@abaco.com> --- include/asm-generic/atomic-long.h | 63 ------------------------------- include/asm-generic/atomic.h | 49 ++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 63 deletions(-) diff --git a/include/asm-generic/atomic-long.h b/include/asm-generic/atomic-long.h index 322d510f38..fd1fdad20f 100644 --- a/include/asm-generic/atomic-long.h +++ b/include/asm-generic/atomic-long.h @@ -66,69 +66,6 @@ static inline void atomic_long_sub(long i, atomic_long_t *l) atomic64_sub(i, v); } -static inline int atomic_long_sub_and_test(long i, atomic_long_t *l) -{ - atomic64_t *v = (atomic64_t *)l; - - return atomic64_sub_and_test(i, v); -} - -static inline int atomic_long_dec_and_test(atomic_long_t *l) -{ - atomic64_t *v = (atomic64_t *)l; - - return atomic64_dec_and_test(v); -} - -static inline int atomic_long_inc_and_test(atomic_long_t *l) -{ - atomic64_t *v = (atomic64_t *)l; - - return atomic64_inc_and_test(v); -} - -static inline int atomic_long_add_negative(long i, atomic_long_t *l) -{ - atomic64_t *v = (atomic64_t *)l; - - return atomic64_add_negative(i, v); -} - -static inline long atomic_long_add_return(long i, atomic_long_t *l) -{ - atomic64_t *v = (atomic64_t *)l; - - return (long)atomic64_add_return(i, v); -} - -static inline long atomic_long_sub_return(long i, atomic_long_t *l) -{ - atomic64_t *v = (atomic64_t *)l; - - return (long)atomic64_sub_return(i, v); -} - -static inline long atomic_long_inc_return(atomic_long_t *l) -{ - atomic64_t *v = (atomic64_t *)l; - - return (long)atomic64_inc_return(v); -} - -static inline long atomic_long_dec_return(atomic_long_t *l) -{ - atomic64_t *v = (atomic64_t *)l; - - return (long)atomic64_dec_return(v); -} - -static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u) -{ - atomic64_t *v = (atomic64_t *)l; - - return (long)atomic64_add_unless(v, a, u); -} - #define atomic_long_inc_not_zero(l) atomic64_inc_not_zero((atomic64_t *)(l)) #define atomic_long_cmpxchg(l, old, new) \ diff --git a/include/asm-generic/atomic.h b/include/asm-generic/atomic.h index 449cecaabc..6e63b8e8e7 100644 --- a/include/asm-generic/atomic.h +++ b/include/asm-generic/atomic.h @@ -11,7 +11,55 @@ #ifdef CONFIG_SMP #error SMP not supported #endif +#define ATOMIC_INIT(i) { (i) } + +#ifdef CONFIG_64BIT +typedef struct { s64 counter; } atomic64_t; + +#define atomic64_read(v) ((v)->counter) +#define atomic64_set(v, i) (((v)->counter) = (i)) + +static inline void atomic64_add(s64 i, volatile atomic64_t *v) +{ + v->counter += i; +} + +static inline void atomic64_sub(s64 i, volatile atomic64_t *v) +{ + v->counter -= i; +} + +static inline void atomic64_inc(volatile atomic64_t *v) +{ + v->counter += 1; +} + +static inline void atomic64_dec(volatile atomic64_t *v) +{ + v->counter -= 1; +} + +static inline int atomic64_dec_and_test(volatile atomic64_t *v) +{ + s64 val; + + val = v->counter; + v->counter = val -= 1; + + return val == 0; +} +static inline int atomic64_add_negative(s64 i, volatile atomic64_t *v) +{ + s64 val; + + val = v->counter; + v->counter = val += i; + + return val < 0; +} + +#else typedef struct { volatile int counter; } atomic_t; #define ATOMIC_INIT(i) { (i) } @@ -63,6 +111,7 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) { *addr &= ~mask; } +#endif /* Atomic operations are already serializing on ARM */ #define smp_mb__before_atomic_dec() barrier() -- 2.27.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
next prev parent reply other threads:[~2021-08-13 8:19 UTC|newest] Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-13 8:16 [PATCH v3 0/3] NXP IFC nand driver Renaud Barbier 2021-08-13 8:16 ` Renaud Barbier [this message] 2021-08-13 8:16 ` [PATCH 2/3] nand: add " Renaud Barbier 2021-08-13 8:16 ` [PATCH 3/3] ls1046ardb: enable IFC NAND Renaud Barbier 2021-08-23 14:03 ` Sascha Hauer -- strict thread matches above, loose matches on Subject: below -- 2021-08-02 10:40 [PATCH v2 0/3] NXP IFC nand driver Renaud Barbier 2021-08-02 10:40 ` [PATCH 1/3] ARM: atomic.h: add 64-bit counter support Renaud Barbier 2021-08-09 11:01 ` Ahmad Fatoum
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