From: Sascha Hauer <s.hauer@pengutronix.de>
To: barebox@lists.infradead.org, Anees Rehman <anees.r3hman@gmail.com>
Subject: Re: [PATCH] ARM: i.MX7: DDR size detection off-by-one in row_max
Date: Wed, 15 Apr 2026 08:24:39 +0200 [thread overview]
Message-ID: <177623427970.3294550.8925237504260910748.b4-ty@pengutronix.de> (raw)
In-Reply-To: <20260414165812.194029-1-anees.r3hman@gmail.com>
On Tue, 14 Apr 2026 18:58:12 +0200, Anees Rehman wrote:
> The imx7d_ddrc_sdram_size() function passes row_max=15 to
> imx_ddrc_sdram_size(), but the correct value is 16. This causes
> count_bits() to return one less than the actual number of row
> address bits, halving the detected memory size for any i.MX7D
> configuration with 14 row addresses (e.g. 4Gbit LPDDR2).
>
> For example, with 14 row address pins (R0-R13), ADDRMAP6 disables
> row bits 14 and 15. count_bits(15, ...) returns 15-2=13 instead
> of the correct 14, resulting in 256MB detected instead of 512MB
> (single rank) or 512MB instead of 1GB (dual rank).
>
> [...]
Applied, thanks!
[1/1] ARM: i.MX7: DDR size detection off-by-one in row_max
https://git.pengutronix.de/cgit/barebox/commit/?id=bbc393110fa5 (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
prev parent reply other threads:[~2026-04-15 6:25 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-14 16:58 Anees Rehman
2026-04-15 6:24 ` Sascha Hauer [this message]
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