From: Sascha Hauer <s.hauer@pengutronix.de>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: barebox@lists.infradead.org, Ahmad Fatoum <ahmad@a3f.at>
Subject: Re: [PATCH 1/3] ARM: i.MX: boot: correctly handle SRC_SBMR1 override via SRC_GPR9
Date: Fri, 8 May 2020 14:07:31 +0200 [thread overview]
Message-ID: <20200508120731.GL5877@pengutronix.de> (raw)
In-Reply-To: <b7a02590-a63b-9681-c5f5-8475dd85886d@pengutronix.de>
On Fri, May 08, 2020 at 08:41:41AM +0200, Ahmad Fatoum wrote:
> Hello,
>
> On 4/27/20 10:28 AM, Ahmad Fatoum wrote:
> > Hello,
> >
> > On 4/27/20 10:07 AM, Sascha Hauer wrote:
> >> On Mon, Apr 27, 2020 at 09:13:49AM +0200, Ahmad Fatoum wrote:
> >>> `mw 0x20d8040 0x08000030; mw 0x20d8044 0x10000000; reset` issued on an
> >>> i.MX6Q forces boot from the ecspi1. This is because the BootROM reads
> >>> the boot mode out of SRC_GPR9 instead of SRC_SBMR1 whenever SRC_GPR10
> >>> has its 28th bit set.
> >>
> >> Is this documented somewhere? The reference Manual marks SRC_GPR9 and
> >> SRC_GPR10 as
> >>
> >> | This register is used by the ROM code and should not be used
> >> | by application software.
>
> Seems it's indeed documented in the IMX6ULRM (Rev.2 03/27).
> See Table 8-6. Persistent bits.
>
> Can the patches be applied or do you need me to change something?
I just merged them
Sascha
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prev parent reply other threads:[~2020-05-08 12:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-27 7:13 Ahmad Fatoum
2020-04-27 7:13 ` [PATCH 2/3] ARM: i.MX: boot: interpret reserved boot as forced serial Ahmad Fatoum
2020-04-27 7:13 ` [PATCH 3/3] ARM: i.MX6: boot: handle i.MX6UL differences Ahmad Fatoum
2020-04-27 8:07 ` [PATCH 1/3] ARM: i.MX: boot: correctly handle SRC_SBMR1 override via SRC_GPR9 Sascha Hauer
2020-04-27 8:28 ` Ahmad Fatoum
2020-05-08 6:41 ` Ahmad Fatoum
2020-05-08 12:07 ` Sascha Hauer [this message]
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