From: Antony Pavlov <antonynpavlov@gmail.com>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH 3/3] RISC-V: drop old timer handling code
Date: Tue, 30 Mar 2021 01:31:20 +0300 [thread overview]
Message-ID: <20210329223120.442256-4-antonynpavlov@gmail.com> (raw)
In-Reply-To: <20210329223120.442256-1-antonynpavlov@gmail.com>
Use drivers/clocksource/timer-riscv.c driver introduced in
'2ee369dcf7a5 ("clocksource: add driver for RISC-V and CLINT
timers")' instead.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/riscv/lib/Makefile | 2 +-
arch/riscv/lib/riscv_timer.c | 63 ------------------------------------
2 files changed, 1 insertion(+), 64 deletions(-)
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index a9bf68bca5..a4eaa1005d 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -2,7 +2,7 @@
extra-y += barebox.lds
-obj-y += riscv_timer.o dtb.o
+obj-y += dtb.o
obj-pbl-y += sections.o setupc.o reloc.o sections.o runtime-offset.o
obj-$(CONFIG_HAS_ARCH_SJLJ) += setjmp.o longjmp.o
obj-$(CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS) += memcpy.o memset.o memmove.o
diff --git a/arch/riscv/lib/riscv_timer.c b/arch/riscv/lib/riscv_timer.c
deleted file mode 100644
index 919d77d4b5..0000000000
--- a/arch/riscv/lib/riscv_timer.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2017 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/**
- * @file
- * @brief Clocksource based on RISC-V cycle CSR timer
- */
-
-#include <init.h>
-#include <of.h>
-#include <linux/clk.h>
-#include <clock.h>
-
-static uint64_t rdcycle_read(void)
-{
- register unsigned long __v;
-
- __asm__ __volatile__ ("rdcycle %0" : "=r" (__v));
-
- return __v;
-}
-
-static struct clocksource rdcycle_cs = {
- .read = rdcycle_read,
- .mask = CLOCKSOURCE_MASK(32),
-};
-
-static int rdcycle_cs_init(void)
-{
- unsigned int cycle_frequency;
-
- /* default rate: 100 MHz */
- cycle_frequency = 100000000;
-
- if (IS_ENABLED(CONFIG_OFTREE)) {
- struct device_node *np;
- struct clk *clk;
-
- np = of_get_cpu_node(0, NULL);
- if (np) {
- clk = of_clk_get(np, 0);
- if (!IS_ERR(clk)) {
- cycle_frequency = clk_get_rate(clk);
- }
- }
- }
-
- clocks_calc_mult_shift(&rdcycle_cs.mult, &rdcycle_cs.shift,
- cycle_frequency, NSEC_PER_SEC, 10);
-
- return init_clock(&rdcycle_cs);
-}
-postcore_initcall(rdcycle_cs_init);
--
2.30.1
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next prev parent reply other threads:[~2021-03-30 1:19 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-29 22:31 [PATCH 0/3] RISC-V cycle timer fixes Antony Pavlov
2021-03-29 22:31 ` [PATCH 1/3] clocksource: timer-riscv: adapt riscv_timer_get_count_rdcycle() for RV32 Antony Pavlov
2021-03-29 22:31 ` [PATCH 2/3] RISC-V: erizo.dtsi: set timebase-frequency = <24000000> Antony Pavlov
2021-03-29 22:31 ` Antony Pavlov [this message]
2021-03-30 5:36 ` [PATCH 0/3] RISC-V cycle timer fixes Sascha Hauer
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