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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 02/11] clk: rockchip rk3568: Initialize clocks
Date: Tue, 15 Jun 2021 16:16:32 +0200
Message-ID: <20210615141641.31577-3-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20210615141641.31577-1-s.hauer@pengutronix.de>

This initializes the rk3568 clocks in the way U-Boot initializes them as
well.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/rockchip/clk-rk3568.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index e3442b9d6c..8b44e2465b 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1623,6 +1623,12 @@ static void __init rk3568_pmu_clk_init(struct device_node *np)
 				      ARRAY_SIZE(rk3568_pmucru_critical_clocks));
 
 	rockchip_clk_of_add_provider(np, ctx);
+
+	clk_name_set_parent("ppll", "pll_ppll");
+	clk_name_set_parent("clk_rtc_32k", "clk_rtc32k_frac");
+	clk_name_set_rate("clk_rtc_32k", 32768);
+	clk_name_set_rate("pclk_pmu", 100000000);
+	clk_name_set_rate("pll_ppll", 200000000);
 }
 
 static void __init rk3568_clk_init(struct device_node *np)
@@ -1660,6 +1666,28 @@ static void __init rk3568_clk_init(struct device_node *np)
 				      ARRAY_SIZE(rk3568_cru_critical_clocks));
 
 	rockchip_clk_of_add_provider(np, ctx);
+
+	clk_name_set_parent("npll", "pll_npll");
+	clk_name_set_parent("vpll", "pll_vpll");
+	clk_name_set_parent("pclk_bus", "gpll_100m");
+	clk_name_set_parent("clk_sdmmc0", "cpll_50m");
+	clk_name_set_parent("cclk_emmc", "gpll_200m");
+
+	clk_name_set_rate("pll_cpll", 1000000000);
+	clk_name_set_rate("pll_gpll", 1188000000);
+	clk_name_set_rate("armclk", 600000000);
+	clk_name_set_rate("aclk_bus", 150000000);
+	clk_name_set_rate("pclk_bus", 100000000);
+	clk_name_set_rate("aclk_top_high", 300000000);
+	clk_name_set_rate("aclk_top_low", 200000000);
+	clk_name_set_rate("hclk_top", 150000000);
+	clk_name_set_rate("pclk_top", 100000000);
+	clk_name_set_rate("aclk_perimid", 300000000);
+	clk_name_set_rate("hclk_perimid", 150000000);
+	clk_name_set_rate("pll_npll", 1200000000);
+	clk_name_set_rate("pll_apll", 816000000);
+
+	clk_name_set_parent("pclk_top", "gpll_100m");
 }
 
 struct clk_rk3568_inits {
-- 
2.29.2


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  parent reply	other threads:[~2021-06-15 16:46 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-15 14:16 [PATCH 00/11] Rockchip RK3568 support Sascha Hauer
2021-06-15 14:16 ` [PATCH 01/11] clk: Add clk_name_* functions Sascha Hauer
2021-06-15 14:16 ` Sascha Hauer [this message]
2021-06-15 14:16 ` [PATCH 03/11] filetype: Add Rockchip boot image type Sascha Hauer
2021-06-15 14:16 ` [PATCH 04/11] ARM: Rockchip: Add rkimage tool Sascha Hauer
2021-06-15 14:16 ` [PATCH 05/11] ARM: Add relocate_to_adr_full() Sascha Hauer
2021-06-15 14:16 ` [PATCH 06/11] ARM: Rockchip: Add rk3568 dtsi files Sascha Hauer
2021-06-15 14:16 ` [PATCH 07/11] ARM: Rockchip: Add rk3568 support Sascha Hauer
2021-06-15 14:16 ` [PATCH 08/11] ARM: Add atf common support Sascha Hauer
2021-06-15 14:16 ` [PATCH 09/11] ARM: rockchip: Add bootm handler for RKNS images Sascha Hauer
2021-06-15 14:16 ` [PATCH 10/11] ARM: Rockchip: Add rk3568 evb board support Sascha Hauer
2021-06-15 14:16 ` [PATCH 11/11] Add rockchip_v8_defconfig Sascha Hauer

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