From: Sascha Hauer <sha@pengutronix.de>
To: Trent Piepho <tpiepho@gmail.com>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 1/1] ddr: imx8m: Rework ddrphy code and fix DDR-1067 on iMX8MM
Date: Fri, 1 Oct 2021 14:14:12 +0200 [thread overview]
Message-ID: <20211001121412.GS24834@pengutronix.de> (raw)
In-Reply-To: <20210924031446.1515172-1-tpiepho@gmail.com>
On Thu, Sep 23, 2021 at 08:14:46PM -0700, Trent Piepho wrote:
> This code could not decide if it was using speeds in Hz, or MHz, or just
> constants that identify specific speeds.
>
> Rework it to use symbolic constants for all speeds. Use arrays
> for configurations values for all cases. The DDR DRAM speed constants
> will be the array index, so the linear search for the configuration is
> eliminated.
>
> For iMX8MM type SoCs using the integr PLL the speed DDR-1067 with a 266⅔
> MHz clock will now work.
>
> The iM8MQ type SSCG PLL SoCs would previously silently program the PLL
> will zero values if a non-supported DDR rate was used. Now they will
> generate an error.
>
> Note that some PLL tables have entries for speeds that the main entry
> point for the code does not support, so they can't actually ever be
> used. This is not fixed.
>
> Signed-off-by: Trent Piepho <tpiepho@gmail.com>
> ---
> drivers/ddr/imx8m/ddrphy_utils.c | 332 ++++++++++++++-----------------
> 1 file changed, 147 insertions(+), 185 deletions(-)
Applied, thanks
Sascha
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prev parent reply other threads:[~2021-10-01 12:18 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-24 3:14 Trent Piepho
2021-09-29 9:48 ` Ahmad Fatoum
2021-10-01 12:14 ` Sascha Hauer [this message]
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