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From: Sascha Hauer <sha@pengutronix.de>
To: Ahmad Fatoum <ahmad@a3f.at>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH master] RISC-V: interrupts: fix Zifencei emulation on rv64
Date: Mon, 13 Dec 2021 23:13:23 +0100
Message-ID: <20211213221323.GC6003@pengutronix.de> (raw)
In-Reply-To: <20211203063340.1026512-1-ahmad@a3f.at>

On Fri, Dec 03, 2021 at 07:33:40AM +0100, Ahmad Fatoum wrote:
> Zifencei emulaton was added for bare bones 32-bit targets, but the code
> is there on 64-bit too. The instruction skip at the end of the function
> skips 4 bytes, the size of an instruction on both rv32 and rv64. The
> instruction decoder however assumes instructions are size(long) bytes,
> which is 8 > 4 on rv64. Fix this.
> 
> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
> ---
>  arch/riscv/cpu/interrupts.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks

Sascha

> 
> diff --git a/arch/riscv/cpu/interrupts.c b/arch/riscv/cpu/interrupts.c
> index 0e8951b61968..1f2d7b885737 100644
> --- a/arch/riscv/cpu/interrupts.c
> +++ b/arch/riscv/cpu/interrupts.c
> @@ -122,7 +122,7 @@ unsigned long handle_trap(struct pt_regs *regs)
>  		goto skip;
>  
>  	if (regs->cause == 2) { /* illegal instruction */
> -		switch(*(unsigned long *)regs->epc) {
> +		switch(*(u32 *)regs->epc) {
>  		case 0x0000100f: /* fence.i */
>  			goto skip;
>  		default:
> -- 
> 2.33.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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      reply	other threads:[~2021-12-13 22:39 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-03  6:33 Ahmad Fatoum
2021-12-13 22:13 ` Sascha Hauer [this message]

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