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From: Oleksij Rempel <o.rempel@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Oleksij Rempel <o.rempel@pengutronix.de>
Subject: [PATCH v1 2/2] ARM: rpi: set uart0-pl0110 clk to 48MHz
Date: Fri, 14 Jan 2022 09:21:41 +0100	[thread overview]
Message-ID: <20220114082141.302151-2-o.rempel@pengutronix.de> (raw)
In-Reply-To: <20220114082141.302151-1-o.rempel@pengutronix.de>

At least on RPi2 this clock is 48MHz. This issue was not visible,
becouse amba-pl011 driver was not reseting UART controller after
changing baudrate. So, clk settings was not updated for some time.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
---
 arch/arm/boards/raspberry-pi/rpi-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
index 6c5df6fd69..2684bd5ed7 100644
--- a/arch/arm/boards/raspberry-pi/rpi-common.c
+++ b/arch/arm/boards/raspberry-pi/rpi-common.c
@@ -374,7 +374,7 @@ static int rpi_console_clock_init(void)
 	clk = clk_fixed("apb_pclk", 0);
 	clk_register_clkdev(clk, "apb_pclk", NULL);
 
-	clk = clk_fixed("uart0-pl0110", 3 * 1000 * 1000);
+	clk = clk_fixed("uart0-pl0110", 48 * 1000 * 1000);
 	clk_register_clkdev(clk, NULL, "uart0-pl0110");
 	clkdev_add_physbase(clk, BCM2835_PL011_BASE, NULL);
 	clkdev_add_physbase(clk, BCM2836_PL011_BASE, NULL);
-- 
2.30.2


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  reply	other threads:[~2022-01-14  8:23 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-14  8:21 [PATCH v1 1/2] serial: amba-pl011: reset controller on pl011_setbaudrate() Oleksij Rempel
2022-01-14  8:21 ` Oleksij Rempel [this message]
2022-01-14  8:30   ` [PATCH v1 2/2] ARM: rpi: set uart0-pl0110 clk to 48MHz Sascha Hauer
2022-01-14 10:12     ` Oleksij Rempel
2022-01-14 10:17       ` Ahmad Fatoum
2022-01-14 10:39       ` Sascha Hauer

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