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From: Michael Riesch <michael.riesch@wolfvision.net>
To: barebox@lists.infradead.org
Cc: Frank Wunderlich <frank-w@public-files.de>,
	Michael Riesch <michael.riesch@wolfvision.net>
Subject: [PATCH 2/2] usb: dwc3: align dwc3 clocks with binding
Date: Mon,  9 May 2022 13:36:18 +0200	[thread overview]
Message-ID: <20220509113618.1602657-3-michael.riesch@wolfvision.net> (raw)
In-Reply-To: <20220509113618.1602657-1-michael.riesch@wolfvision.net>

The device tree bindings snps,dwc3.yaml and rockchip,dwc3.yaml
specify different clock names. This inconsistency did not matter
in the past as the snps,dwc3 used to be a subnode of the
rockchip,rk3xyz-dwc3 glue node. For the RK356x, however, a
different approach is used and the two nodes are merged.
Therefore, the dwc3 driver must accept both groups of clock names.

This step is a prerequisite for replacing the initial rk3568.dtsi
in arch/arm/dts with the mainline Linux version. For compatibility,
the former is updated accordingly. This also illustrates the
migration from glue node and subnode to a single device tree node.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
 arch/arm/dts/rk3568-bpi-r2-pro.dts |  7 +--
 arch/arm/dts/rk3568-evb1-v10.dts   | 14 +++---
 arch/arm/dts/rk3568.dtsi           | 72 ++++++++++--------------------
 drivers/usb/dwc3/core.c            | 50 ++++++++++++++++-----
 4 files changed, 71 insertions(+), 72 deletions(-)

diff --git a/arch/arm/dts/rk3568-bpi-r2-pro.dts b/arch/arm/dts/rk3568-bpi-r2-pro.dts
index db13f00cd0..da76ab64c1 100644
--- a/arch/arm/dts/rk3568-bpi-r2-pro.dts
+++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts
@@ -560,16 +560,13 @@
 	status = "okay";
 };
 
-&usbdrd_dwc3 {
+&usb_host0_xhci {
 	dr_mode = "host";
 	extcon = <&usb2phy0>;
-};
-
-&usbdrd30 {
 	status = "okay";
 };
 
-&usbhost30 {
+&usb_host1_xhci {
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts
index 4ded9b1735..df5633978d 100644
--- a/arch/arm/dts/rk3568-evb1-v10.dts
+++ b/arch/arm/dts/rk3568-evb1-v10.dts
@@ -547,24 +547,20 @@
 	status = "okay";
 };
 
-&usb_host1_ehci {
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
 	status = "okay";
 };
 
-&usb_host1_ohci {
+&usb_host1_ehci {
 	status = "okay";
 };
 
-&usbdrd_dwc3 {
-	dr_mode = "otg";
-	extcon = <&usb2phy0>;
-};
-
-&usbdrd30 {
+&usb_host1_ohci {
 	status = "okay";
 };
 
-&usbhost30 {
+&usb_host1_xhci {
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
index 28121dbdf3..3c458754af 100644
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -198,62 +198,38 @@
 		};
 	};
 
-	usbdrd30: usbdrd {
-		compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
+	usb_host0_xhci: usb@fcc00000 {
+		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+		reg = <0x0 0xfcc00000 0x0 0x400000>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
-			 <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>;
+			 <&cru ACLK_USB3OTG0>;
 		clock-names = "ref_clk", "suspend_clk",
-			      "bus_clk", "pipe_clk";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
+			      "bus_clk";
+		dr_mode = "otg";
+		phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
+		phy-names = "usb2-phy", "usb3-phy";
+		phy_type = "utmi_wide";
+		resets = <&cru SRST_USB3OTG0>;
+		snps,dis_u2_susphy_quirk;
 		status = "disabled";
-
-		usbdrd_dwc3: dwc3@fcc00000 {
-			compatible = "snps,dwc3";
-			reg = <0x0 0xfcc00000 0x0 0x400000>;
-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-			dr_mode = "otg";
-			phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
-			phy-names = "usb2-phy", "usb3-phy";
-			phy_type = "utmi_wide";
-			resets = <&cru SRST_USB3OTG0>;
-			reset-names = "usb3-otg";
-			snps,dis_enblslpm_quirk;
-			snps,dis-u2-freeclk-exists-quirk;
-			snps,dis-del-phy-power-chg-quirk;
-			snps,dis-tx-ipgap-linecheck-quirk;
-			snps,xhci-trb-ent-quirk;
-		};
 	};
 
-	usbhost30: usbhost {
-		compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
+	usb_host1_xhci: usb@fd000000 {
+		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+		reg = <0x0 0xfd000000 0x0 0x400000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
-			 <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>;
+			 <&cru ACLK_USB3OTG1>;
 		clock-names = "ref_clk", "suspend_clk",
-			      "bus_clk", "pipe_clk";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
+			      "bus_clk";
+		dr_mode = "host";
+		phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>;
+		phy-names = "usb2-phy", "usb3-phy";
+		phy_type = "utmi_wide";
+		resets = <&cru SRST_USB3OTG1>;
+		snps,dis_u2_susphy_quirk;
 		status = "disabled";
-
-		usbhost_dwc3: dwc3@fd000000 {
-			compatible = "snps,dwc3";
-			reg = <0x0 0xfd000000 0x0 0x400000>;
-			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
-			dr_mode = "host";
-			phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>;
-			phy-names = "usb2-phy", "usb3-phy";
-			phy_type = "utmi_wide";
-			resets = <&cru SRST_USB3OTG1>;
-			reset-names = "usb3-host";
-			snps,dis_enblslpm_quirk;
-			snps,dis-u2-freeclk-exists-quirk;
-			snps,dis-del-phy-power-chg-quirk;
-			snps,dis-tx-ipgap-linecheck-quirk;
-			snps,xhci-trb-ent-quirk;
-		};
 	};
 
 	gic: interrupt-controller@fd400000 {
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index fd0ec754e0..30aaef90ac 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -23,6 +23,11 @@
 
 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY	5000 /* ms */
 
+struct dwc3_match_data {
+	const struct clk_bulk_data	*clks;
+	const int			num_clks;
+};
+
 /**
  * dwc3_get_dr_mode - Validates and sets dr_mode
  * @dwc: pointer to our context structure
@@ -326,12 +331,6 @@ err0:
 	return ret;
 }
 
-static const struct clk_bulk_data dwc3_core_clks[] = {
-	{ .id = "ref" },
-	{ .id = "bus_early" },
-	{ .id = "suspend" },
-};
-
 /*
  * dwc3_frame_length_adjustment - Adjusts frame length if required
  * @dwc3: Pointer to our controller context structure
@@ -1098,20 +1097,23 @@ static void dwc3_coresoft_reset(struct dwc3 *dwc)
 
 static int dwc3_probe(struct device_d *dev)
 {
+	const struct dwc3_match_data *match;
 	struct dwc3		*dwc;
 	int			ret;
 
 	dwc = xzalloc(sizeof(*dwc));
 	dev->priv = dwc;
 
-	dwc->clks = xmemdup(dwc3_core_clks, sizeof(dwc3_core_clks));
+	match = device_get_match_data(dev);
+	dwc->clks = xmemdup(match->clks, match->num_clks *
+			    sizeof(struct clk_bulk_data));
 	dwc->dev = dev;
 	dwc->regs = dev_get_mem_region(dwc->dev, 0) + DWC3_GLOBALS_REGS_START;
 
 	dwc3_get_properties(dwc);
 
 	if (dev->device_node) {
-		dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
+		dwc->num_clks = match->num_clks;
 
 		if (of_find_property(dev->device_node, "clocks", NULL)) {
 			ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
@@ -1176,12 +1178,40 @@ static void dwc3_remove(struct device_d *dev)
 	clk_bulk_put(dwc->num_clks, dwc->clks);
 }
 
+static const struct clk_bulk_data dwc3_core_clks[] = {
+	{ .id = "ref" },
+	{ .id = "bus_early" },
+	{ .id = "suspend" },
+};
+
+static const struct dwc3_match_data dwc3_default = {
+	.clks = dwc3_core_clks,
+	.num_clks = ARRAY_SIZE(dwc3_core_clks),
+};
+
+static const struct clk_bulk_data dwc3_core_clks_rk3568[] = {
+	{ .id = "ref_clk" },
+	{ .id = "bus_clk" },
+	{ .id = "suspend_clk" },
+};
+
+static const struct dwc3_match_data dwc3_rk3568 = {
+	.clks = dwc3_core_clks_rk3568,
+	.num_clks = ARRAY_SIZE(dwc3_core_clks_rk3568),
+};
+
 static const struct of_device_id of_dwc3_match[] = {
 	{
-		.compatible = "snps,dwc3"
+		.compatible = "snps,dwc3",
+		.data = &dwc3_default,
+	},
+	{
+		.compatible = "synopsys,dwc3",
+		.data = &dwc3_default,
 	},
 	{
-		.compatible = "synopsys,dwc3"
+		.compatible = "rockchip,rk3568-dwc3",
+		.data = &dwc3_rk3568,
 	},
 	{ },
 };
-- 
2.30.2


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  parent reply	other threads:[~2022-05-09 11:38 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-09 11:36 [PATCH 0/2] align rk356x drivers as preparation for mainline dts Michael Riesch
2022-05-09 11:36 ` [PATCH 1/2] phy: rockchip: align naneng-combphy clocks and resets with binding Michael Riesch
2022-05-09 11:36 ` Michael Riesch [this message]
2022-05-10  8:11 ` Aw: [PATCH 0/2] align rk356x drivers as preparation for mainline dts Frank Wunderlich
2022-05-11  6:28 ` Sascha Hauer

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