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From: Sascha Hauer <sha@pengutronix.de>
To: Michael Riesch <michael.riesch@wolfvision.net>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller
Date: Mon, 3 Apr 2023 09:32:02 +0200	[thread overview]
Message-ID: <20230403073202.GS19113@pengutronix.de> (raw)
In-Reply-To: <2b65b588-aa9c-b6c7-a020-807ccea5dc58@wolfvision.net>

On Fri, Mar 31, 2023 at 05:42:54PM +0200, Michael Riesch wrote:
> Hi Sascha,
> 
> On 3/28/23 09:40, Sascha Hauer wrote:
> > This series adds support for reading the amount of memory from
> > the DDR controller. This helps on boards which come with
> > different amounts of memory like the Radxa Rock3a.
> > 
> > This series also fixes issues with an upstream TF-A firmware. With this
> > the IRAM where the bootsource is stored is no longer accessible in
> > normal mode. We have to read its contents before starting the TF-A.
> > For this it became necessary to add a common barebox entry function
> > for rk3568, to get a common place to read the IRAM contents.
> 
> Nice, thanks for your efforts! Now it should be possible to remove the
> memory nodes from arch/arm/dts/rk356*, right?
> 
> I tried this on a ROCK3A with 8 GB and the memory calculation returned
> the correct result. There are now two ram devices
> 
>    `-- mem0
>       `-- 0x00000000-0x10fffffff (   4.3 GiB): /dev/ram1
>    `-- mem1
>       `-- 0x00000000-0xef5fffff (   3.7 GiB): /dev/ram0
>    `-- mem2
>       `-- 0x00000000-0xffffffffffffffff (   0 Bytes): /dev/mem

At first sight I was a bit puzzled that both memory regions start a 0x0.
That's correct for the devinfo output of course. The output of 'iomem'
would show the situation better here.

> 
> that start at SZ_4G and 0xa00000, respectively.
> 
> However, after loading the kernel the system hangs:
> 
> Loaded kernel to 0x100000000, devicetree at 0x101970000
> 
> Is this a bug in barebox or is something special required to boot the
> kernel from SZ_4G?

I would have guessed that barebox puts the kernel below the malloc area
just as usual. Ok, apparently it doesn't. I haven't found anything in
Documentation/arm64/booting.rst that forbids placing the kernel above
the 32bit boundary. You could verify that the memory nodes barebox
writes meet your expectations by adding some -v to the boot command.
Also earlycon might help to get some output from the kernel.

Sascha

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  reply	other threads:[~2023-04-03  7:33 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-28  7:40 Sascha Hauer
2023-03-28  7:40 ` [PATCH v2 1/6] ARM: dts: rk356x: Add DMC controller node Sascha Hauer
2023-03-28  7:40 ` [PATCH v2 2/6] ARM: Rockchip: implement memory read out from controller Sascha Hauer
2023-03-28  8:18   ` Sascha Hauer
2023-04-03 19:43   ` Sascha Hauer
2023-04-04  6:25     ` Michael Riesch
2023-03-28  7:40 ` [PATCH v2 3/6] ARM: Rockchip: Add rk3568 specific barebox entry function Sascha Hauer
2023-03-28  7:40 ` [PATCH v2 4/6] ARM: Rockchip: rk3568: use rk3568_barebox_entry() Sascha Hauer
2023-04-05  6:48   ` Sascha Hauer
2023-03-28  7:40 ` [PATCH v2 5/6] ARM: Rockchip: make bootsource logic generic to all SoCs Sascha Hauer
2023-03-28  7:40 ` [PATCH v2 6/6] ARM: Rockchip: Do not pass device tree to TF-A Sascha Hauer
2023-03-31 15:42 ` [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Michael Riesch
2023-04-03  7:32   ` Sascha Hauer [this message]
2023-04-03 10:04     ` Michael Riesch

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