[PATCH 6/6] arm: socfpga: agilex5: extract write_qspi_refclk from mailbox

[Michael Tretter <m.tretter@pengutronix.de>]

Currently, the QSPI reference clock rate is stored to a register as a
side effect of requesting access to the QSPI flash via mailbox. This is
surprising and inconvenient.

Return the QSPI reference clock rate to the calling function that
requested QSPI flash access and let the caller decide what to do with
it.

This detangles the mailbox code and the low level code, and eventually
allows to use the clock rate in low level platform code.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/atf.c         | 9 ++++++++-
 arch/arm/mach-socfpga/mailbox_s10.c | 7 ++-----
 include/mach/socfpga/mailbox_s10.h  | 2 +-
 3 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-socfpga/atf.c b/arch/arm/mach-socfpga/atf.c
index 3719bde0e8bb..e1f0a3558b04 100644
--- a/arch/arm/mach-socfpga/atf.c
+++ b/arch/arm/mach-socfpga/atf.c
@@ -14,6 +14,7 @@
 
 static void socfpga_agilex5_qspi_init(void)
 {
+	unsigned long master_ref_clk = 0;
 	int ret;
 
 	ret = socfpga_mailbox_s10_init();
@@ -22,11 +23,17 @@ static void socfpga_agilex5_qspi_init(void)
 		return;
 	}
 
-	ret = socfpga_mailbox_s10_qspi_open();
+	ret = socfpga_mailbox_s10_qspi_open(&master_ref_clk);
 	if (ret) {
 		pr_warn("Failed to request QSPI access: %d\n", ret);
 		return;
 	}
+
+	ret = socfpga_agilex5_write_qspi_refclk(master_ref_clk);
+	if (ret) {
+		pr_warn("Failed to store reference clock: %d\n", ret);
+		return;
+	}
 }
 
 static void __noreturn agilex5_load_and_start_image_via_tfa(void)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 417816673c3d..fdbd7f272866 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -10,7 +10,6 @@
 #include <io.h>
 #include <mach/socfpga/mailbox_s10.h>
 #include <mach/socfpga/soc64-regs.h>
-#include <mach/socfpga/soc64-system-manager.h>
 
 #define MBOX_READL(reg)			\
 	 readl(SOCFPGA_MAILBOX_ADDRESS + (reg))
@@ -294,7 +293,7 @@ int socfpga_mailbox_s10_qspi_close(void)
 			     0, NULL, 0, 0, NULL);
 }
 
-int socfpga_mailbox_s10_qspi_open(void)
+int socfpga_mailbox_s10_qspi_open(unsigned long *master_ref_clk)
 {
 	int ret;
 	u32 resp_buf[1] = {};
@@ -339,9 +338,7 @@ int socfpga_mailbox_s10_qspi_open(void)
 
 	pr_info("QSPI: reference clock at %d kHz\n", clk_rate / 1000);
 
-	ret = socfpga_agilex5_write_qspi_refclk(clk_rate);
-	if (ret)
-		return ret;
+	*master_ref_clk = clk_rate;
 
 	return 0;
 
diff --git a/include/mach/socfpga/mailbox_s10.h b/include/mach/socfpga/mailbox_s10.h
index bba4adbbe877..0033bf40d45b 100644
--- a/include/mach/socfpga/mailbox_s10.h
+++ b/include/mach/socfpga/mailbox_s10.h
@@ -185,7 +185,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
 int socfpga_mailbox_s10_init(void);
 
 int socfpga_mailbox_s10_qspi_close(void);
-int socfpga_mailbox_s10_qspi_open(void);
+int socfpga_mailbox_s10_qspi_open(unsigned long *master_ref_clk);
 int socfpga_mailbox_s10_qspi_get_device_info(u32 *resp_buf, u32 resp_buf_len);
 
 #endif /* _MAILBOX_S10_H_ */

-- 
2.47.3